大理水控初始版本
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..6496c34
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,27 @@
+*.uvgui.*
+*.bak
+*.o
+*.d
+*.crf
+*.__i
+*.bin
+
+*.map
+*.htm
+*.lst
+*.sct
+*.lnp
+*.plg
+*.axf
+*.tra
+*.orig
+*.Opt
+.browse.VC.db
+*.dep
+*._ia
+*build*
+*JLinkLog.txt
+Out
+g401302/outTimer
+g401302/outFlow
+supwisdom/sp_version.h
\ No newline at end of file
diff --git a/COM.ini b/COM.ini
new file mode 100644
index 0000000..f32bf8a
--- /dev/null
+++ b/COM.ini
@@ -0,0 +1,15 @@
+/******************************************************************************/
+/* FLASH.INI: FLASH Initialization File */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>> //
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools. */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
+/* This software may only be used under the terms of a valid, current, */
+/* end user licence from KEIL for a compatible version of KEIL software */
+/* development tools. Nothing else gives you the right to use this software. */
+/******************************************************************************/
+//MODE COM3 9600,1,8,1
+ASSIGN COM3 <S1IN>S1OUT
+
+
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..ea4310f
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,17 @@
+TARGET=g40130x
+UV4=/C/Keil/UV4/Uv4.exe
+
+.PHONY: clean all
+
+timer: clean
+ @echo "build std version ..."
+ $(UV4) -cr -j0 -b g401302/project/g401302.uvproj -t"timer" -o"outTimer/OUTPUTFILE.TXT"
+
+flow: clean
+ @echo "build shu version ..."
+ $(UV4) -cr -j0 -b g401302/project/g401302.uvproj -t"flow" -o"outFlow/OUTPUTFILE.TXT"
+
+all: timer flow
+
+clean:
+
\ No newline at end of file
diff --git a/RAM.ini b/RAM.ini
new file mode 100644
index 0000000..ceb6901
--- /dev/null
+++ b/RAM.ini
@@ -0,0 +1,17 @@
+FUNC void Setup (void) {
+
+ SP = _RDWORD(0x08000000); // Setup Stack Pointer
+
+ PC = _RDWORD(0x08000004); // Setup Program Counter
+
+ _WDWORD(0xE000ED08, 0x08004000); // Setup Vector Table Offset Register
+
+}
+
+
+LOAD CSC105.axf INCREMENTAL // Download
+
+Setup(); // Setup for Running
+
+
+g, main
diff --git a/config.h b/config.h
new file mode 100644
index 0000000..2b0893f
--- /dev/null
+++ b/config.h
@@ -0,0 +1,36 @@
+#ifndef _N_CONFIG_H_
+#define _N_CONFIG_H_
+
+#include "./g401302/src/G401_drv_hw_V01.h"
+#include "./sys_hw/drv_usart.h"
+
+#ifndef int8
+#define int8 signed char
+#endif
+
+#ifndef uint8
+#define uint8 unsigned char
+#endif
+
+#ifndef uint16
+#define uint16 unsigned short
+#endif
+
+#ifndef int16
+#define int16 signed short
+#endif
+
+#ifndef uint32
+#define uint32 unsigned int
+#endif
+
+#ifndef int32
+#define int32 signed int
+#endif
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#endif
+
diff --git a/g401302/hex/STM32IAPCombine51.hex b/g401302/hex/STM32IAPCombine51.hex
new file mode 100644
index 0000000..1e44517
--- /dev/null
+++ b/g401302/hex/STM32IAPCombine51.hex
@@ -0,0 +1,1026 @@
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diff --git a/g401302/hex/readme.txt b/g401302/hex/readme.txt
new file mode 100644
index 0000000..8a9f258
--- /dev/null
+++ b/g401302/hex/readme.txt
@@ -0,0 +1,14 @@
+Éú³É°üº¬bootloaderºÍapplicationµÄºÏ²¢.hex,²»ÐèÒª¼ÓÃÜ
+1£¬ÔÚapplicationĿ¼Ï±àдmerge.iniÎļþ
+2£¬ÔÚhexĿ¼Ï·ÅbootloaderµÄ.hexÎļþ£¬ÕâÀïÊÇSTM32IAPCombine.hex
+3£¬keil optionsÀïµÄdebugÀïÃæÑ¡Ôñuse simulator£¬°´ctrl+F5ÔÚhexĿ¼ÏÂÉú³ÉºÏ²¢.hex,ÕâÀïÊÇwaterctrl_combine.hex
+4£¬´ò¿ªseggerÏÂJ-Flash
+1) File ->open data file (Ñ¡ÔñÉú³ÉµÄwaterctrl_combine.hex)
+2) Option->
+project settings --Target InterfaceÑ¡ÔñSWD
+project settings --CPUÑ¡ÔñDevice,ST STM32F101RB,¹´Ñ¡Check core ID
+3)target --connect,Á¬½Ó³É¹¦ºó°´F7ÏÂÔØ£¬F9ÔËÐÐ
+
+
+##STM32IAPCombine51.hex G401302µÄbootloader
+##STM32IAPCombine50.hex G401300µÄbootloader
\ No newline at end of file
diff --git a/g401302/lib/G401_drv_hw_V04.lib b/g401302/lib/G401_drv_hw_V04.lib
new file mode 100644
index 0000000..d744d92
--- /dev/null
+++ b/g401302/lib/G401_drv_hw_V04.lib
Binary files differ
diff --git a/g401302/lib/g401_uart5_v001.lib b/g401302/lib/g401_uart5_v001.lib
new file mode 100644
index 0000000..94ae122
--- /dev/null
+++ b/g401302/lib/g401_uart5_v001.lib
Binary files differ
diff --git a/g401302/project/JLinkSettings.ini b/g401302/project/JLinkSettings.ini
new file mode 100644
index 0000000..2d53bb4
--- /dev/null
+++ b/g401302/project/JLinkSettings.ini
@@ -0,0 +1,35 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="UNSPECIFIED"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/g401302/project/g401302.uvopt b/g401302/project/g401302.uvopt
new file mode 100644
index 0000000..156579a
--- /dev/null
+++ b/g401302/project/g401302.uvopt
@@ -0,0 +1,1388 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>flow</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>8000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>..\outFlow\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <Books>
+ <Book>
+ <Number>0</Number>
+ <Title>Reference Manual</Title>
+ <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+ </Book>
+ <Book>
+ <Number>1</Number>
+ <Title>Technical Reference Manual</Title>
+ <Path>datashts\arm\cortex_m3\r1p1\DDI0337E_CORTEX_M3_R1P1_TRM.PDF</Path>
+ </Book>
+ <Book>
+ <Number>2</Number>
+ <Title>Generic User Guide</Title>
+ <Path>datashts\arm\cortex_m3\r2p1\DUI0552A_CORTEX_M3_DGUG.PDF</Path>
+ </Book>
+ </Books>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-REMAP</SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
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+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>9</GroupNumber>
+ <FileNumber>58</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\msgpack\cwpack.c</PathWithFileName>
+ <FilenameWithoutPath>cwpack.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/g401302/project/g401302.uvproj b/g401302/project/g401302.uvproj
new file mode 100644
index 0000000..eb083a6
--- /dev/null
+++ b/g401302/project/g401302.uvproj
@@ -0,0 +1,1439 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>flow</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>STM32F103RC</Device>
+ <Vendor>STMicroelectronics</Vendor>
+ <Cpu>IRAM(0x20000000-0x2000BFFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\ST\STM32F10x\startup_stm32f10x_hd.s" ("STM32 High Density Line Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL040000)</FlashDriverDll>
+ <DeviceId>4230</DeviceId>
+ <RegisterFile>stm32f10x.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+ <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>..\outFlow\</OutputDirectory>
+ <OutputName>G401302_flow</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>1</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>..\outFlow\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd /c gitver.bat</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>fromelf --bin -o ..\outFlow\@l.bin ..\outFlow\@l.axf</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-REMAP</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>7</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\merge.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>Segger\JL2CM3.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4099</DriverSelection>
+ </Flash1>
+ <Flash2>Segger\JL2CM3.dll</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0xc000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x8000000</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x8004000</StartAddress>
+ <Size>0x3c000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0xc000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls>--c99 --diag_suppress=188 -DFLOWSENSOR</MiscControls>
+ <Define>STM32F10X_HD,USE_STDPERIPH_DRIVER,HW_V02</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\src;..\lib;..\..\icc_apdu_lib;..\..\st_fw_lib\inc;..\..\st_fw_lib;..\..\lcd;.\;..\..\sys_hw;..\..\zk;..\..\app_drv;..\..\libqr;..\..\msgpack;</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x08000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>lcd</GroupName>
+ <Files>
+ <File>
+ <FileName>glcd.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\glcd.c</FilePath>
+ </File>
+ <File>
+ <FileName>graphics.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\graphics.c</FilePath>
+ </File>
+ <File>
+ <FileName>graphs.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\graphs.c</FilePath>
+ </File>
+ <File>
+ <FileName>text.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\text.c</FilePath>
+ </File>
+ <File>
+ <FileName>text_tiny.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\text_tiny.c</FilePath>
+ </File>
+ <File>
+ <FileName>unit_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\unit_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>glcd_spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\glcd_spi.c</FilePath>
+ </File>
+ <File>
+ <FileName>ST7565R.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\ST7565R.c</FilePath>
+ </File>
+ <File>
+ <FileName>spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\spi.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>icc_apdu_lib</GroupName>
+ <Files>
+ <File>
+ <FileName>des.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\icc_apdu_lib\des.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>sw</GroupName>
+ <Files>
+ <File>
+ <FileName>nec_apdu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\src\nec_apdu.c</FilePath>
+ </File>
+ <File>
+ <FileName>nec_hardware.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\src\nec_hardware.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_it.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\src\stm32f10x_it.c</FilePath>
+ </File>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_card.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_card.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_communicate.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_communicate.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_consume.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_consume.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_data.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_data.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_des.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_des.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_display.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_display.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_flash.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_flash.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_menu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_menu.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_msgpack.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_msgpack.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_util.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_util.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_upgrade.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_upgrade.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>lib</GroupName>
+ <Files>
+ <File>
+ <FileName>G401_drv_hw_V04.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\lib\G401_drv_hw_V04.lib</FilePath>
+ </File>
+ <File>
+ <FileName>g401_uart5_v001.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\lib\g401_uart5_v001.lib</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>st_fw_lib</GroupName>
+ <Files>
+ <File>
+ <FileName>core_cm3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\core_cm3.c</FilePath>
+ </File>
+ <File>
+ <FileName>misc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\misc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_adc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_adc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_bkp.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_bkp.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_can.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_can.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_cec.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_cec.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_crc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_crc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_dac.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_dac.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_dbgmcu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_dbgmcu.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_dma.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_dma.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_exti.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_exti.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_flash.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_flash.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_fsmc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_fsmc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_gpio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_gpio.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_i2c.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_i2c.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_pwr.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_pwr.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_iwdg.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_iwdg.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_rcc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_rcc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_rtc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_rtc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_sdio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_sdio.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_spi.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_tim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_tim.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_usart.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_usart.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_wwdg.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_wwdg.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_stm32f10x.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\system_stm32f10x.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_stm32f10x_hd.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\st_fw_lib\startup_stm32f10x_hd.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>sys_hw</GroupName>
+ <Files>
+ <File>
+ <FileName>keypad.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\sys_hw\keypad.c</FilePath>
+ </File>
+ <File>
+ <FileName>drv_adc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\sys_hw\drv_adc.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>zk</GroupName>
+ <Files>
+ <File>
+ <FileName>gb2312_16.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\zk\gb2312_16.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>libqr</GroupName>
+ <Files>
+ <File>
+ <FileName>qrencode.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\libqr\qrencode.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>msgpack</GroupName>
+ <Files>
+ <File>
+ <FileName>cwpack.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\msgpack\cwpack.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>timer</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>STM32F103RC</Device>
+ <Vendor>STMicroelectronics</Vendor>
+ <Cpu>IRAM(0x20000000-0x2000BFFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\ST\STM32F10x\startup_stm32f10x_hd.s" ("STM32 High Density Line Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL040000)</FlashDriverDll>
+ <DeviceId>4230</DeviceId>
+ <RegisterFile>stm32f10x.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+ <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>..\outTimer\</OutputDirectory>
+ <OutputName>G401302_timer</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>1</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>..\outTimer\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd /c gitver.bat</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>fromelf --bin -o ..\outTimer\@l.bin ..\outTimer\@l.axf</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-REMAP</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>5</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\merge.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>Segger\JL2CM3.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4099</DriverSelection>
+ </Flash1>
+ <Flash2>Segger\JL2CM3.dll</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0xc000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x8000000</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x8004000</StartAddress>
+ <Size>0x3c000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0xc000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls>--c99 --diag_suppress=188</MiscControls>
+ <Define>STM32F10X_HD,USE_STDPERIPH_DRIVER,HW_V02</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\src;..\lib;..\..\icc_apdu_lib;..\..\st_fw_lib\inc;..\..\st_fw_lib;..\..\lcd;.\;..\..\sys_hw;..\..\zk;..\..\app_drv;..\..\libqr;..\..\msgpack;</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x08000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>lcd</GroupName>
+ <Files>
+ <File>
+ <FileName>glcd.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\glcd.c</FilePath>
+ </File>
+ <File>
+ <FileName>graphics.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\graphics.c</FilePath>
+ </File>
+ <File>
+ <FileName>graphs.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\graphs.c</FilePath>
+ </File>
+ <File>
+ <FileName>text.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\text.c</FilePath>
+ </File>
+ <File>
+ <FileName>text_tiny.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\text_tiny.c</FilePath>
+ </File>
+ <File>
+ <FileName>unit_tests.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\unit_tests.c</FilePath>
+ </File>
+ <File>
+ <FileName>glcd_spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\glcd_spi.c</FilePath>
+ </File>
+ <File>
+ <FileName>ST7565R.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\ST7565R.c</FilePath>
+ </File>
+ <File>
+ <FileName>spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\lcd\spi.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>icc_apdu_lib</GroupName>
+ <Files>
+ <File>
+ <FileName>des.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\icc_apdu_lib\des.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>sw</GroupName>
+ <Files>
+ <File>
+ <FileName>nec_apdu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\src\nec_apdu.c</FilePath>
+ </File>
+ <File>
+ <FileName>nec_hardware.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\src\nec_hardware.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_it.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\src\stm32f10x_it.c</FilePath>
+ </File>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_card.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_card.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_communicate.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_communicate.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_consume.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_consume.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_data.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_data.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_des.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_des.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_display.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_display.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_flash.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_flash.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_menu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_menu.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_msgpack.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_msgpack.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_util.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_util.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_upgrade.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\supwisdom\sp_upgrade.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>lib</GroupName>
+ <Files>
+ <File>
+ <FileName>G401_drv_hw_V04.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\lib\G401_drv_hw_V04.lib</FilePath>
+ </File>
+ <File>
+ <FileName>g401_uart5_v001.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\lib\g401_uart5_v001.lib</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>st_fw_lib</GroupName>
+ <Files>
+ <File>
+ <FileName>core_cm3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\core_cm3.c</FilePath>
+ </File>
+ <File>
+ <FileName>misc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\misc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_adc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_adc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_bkp.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_bkp.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_can.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_can.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_cec.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_cec.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_crc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_crc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_dac.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_dac.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_dbgmcu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_dbgmcu.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_dma.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_dma.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_exti.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_exti.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_flash.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_flash.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_fsmc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_fsmc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_gpio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_gpio.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_i2c.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_i2c.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_pwr.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_pwr.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_iwdg.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_iwdg.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_rcc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_rcc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_rtc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_rtc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_sdio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_sdio.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_spi.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_spi.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_tim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_tim.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_usart.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_usart.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f10x_wwdg.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\src\stm32f10x_wwdg.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_stm32f10x.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\st_fw_lib\system_stm32f10x.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_stm32f10x_hd.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\st_fw_lib\startup_stm32f10x_hd.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>sys_hw</GroupName>
+ <Files>
+ <File>
+ <FileName>keypad.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\sys_hw\keypad.c</FilePath>
+ </File>
+ <File>
+ <FileName>drv_adc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\sys_hw\drv_adc.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>zk</GroupName>
+ <Files>
+ <File>
+ <FileName>gb2312_16.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\zk\gb2312_16.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>libqr</GroupName>
+ <Files>
+ <File>
+ <FileName>qrencode.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\libqr\qrencode.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>msgpack</GroupName>
+ <Files>
+ <File>
+ <FileName>cwpack.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\msgpack\cwpack.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/g401302/project/gitver.bat b/g401302/project/gitver.bat
new file mode 100644
index 0000000..996c3ce
--- /dev/null
+++ b/g401302/project/gitver.bat
@@ -0,0 +1,10 @@
+@echo off
+SET LINE1=#ifndef GIT_VERSION
+SET LINE2=#define GIT_VERSION
+SET LINE3=#endif
+
+FOR /F %%I IN ('git describe --dirty --always --tags --abbrev=4') DO SET VERSTR=%%I
+
+echo %LINE1% > ../../supwisdom/sp_version.h
+echo %LINE2% ^"%VERSTR%^" >> ../../supwisdom/sp_version.h
+echo %LINE3% >> ../../supwisdom/sp_version.h
\ No newline at end of file
diff --git a/g401302/project/merge.ini b/g401302/project/merge.ini
new file mode 100644
index 0000000..8efd9d0
--- /dev/null
+++ b/g401302/project/merge.ini
@@ -0,0 +1,16 @@
+/******************************************************************************/
+/* FLASH.INI: FLASH Initialization File */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>> //
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools. */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
+/* This software may only be used under the terms of a valid, current, */
+/* end user licence from KEIL for a compatible version of KEIL software */
+/* development tools. Nothing else gives you the right to use this software. */
+/******************************************************************************/
+LOAD ..\hex\STM32IAPCombine51.hex // Download
+save ..\hex\G401302_combine.hex 0x08000000,0x0803FFFF
+//g,main
+
+
diff --git a/g401302/src/G401_drv_hw_V01.h b/g401302/src/G401_drv_hw_V01.h
new file mode 100644
index 0000000..0a63590
--- /dev/null
+++ b/g401302/src/G401_drv_hw_V01.h
@@ -0,0 +1,623 @@
+
+#ifndef __G401_HWDRV_LIB_H__
+#define __G401_HWDRV_LIB_H__
+
+#include "stdint.h"
+#include "stm32f10x.h"
+#include "drv_usart.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+/*
+ ³õʼ»¯Ê±»ù¶¨Ê±Æ÷(1ms)
+*/
+extern u32 SysTick_cfg(void);
+/*
+ Çý¶¯Ê¹ÓÃSYSTICK²úÉúʱ»ù£¬²¢ÅäÖÃSYSTICKΪ1msÒç³öÖжϣ¬Ó¦ÓòãÐèÍê
+ ³ÉSYSTICKÖжϷþÎñº¯ÊýSysTick_Handler£¬²¢µ÷ÓÃTimerTickº¯Êý£¬
+ Íê³ÉÏÔʾɨÃ衢ͨѶËùÐ趨ʱµÈ²Ù×÷
+*/
+extern void TimerTick(void);
+
+
+/*
+ »ñÈ¡Çý¶¯²ãά»¤µÄ32λms¼¶µÎ´ðµ±Ç°Öµ£¬¸Ãֵÿms¸üÐÂ1´Î£¬Ã¿´Î¼Ó1
+*/
+extern u32 timer_get_ticker(void);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+/*
+ ¹¦ÄÜ: ¼ÆËãÖ¸¶¨³¤¶ÈÊý¾ÝÁ÷µÄcrcУÑéÖµ
+ ÊäÈë: pBuffer£¬Êý¾ÝÁ÷Ö¸Õë BufferLength: Êý¾ÝÁ÷×Ö½Ú³¤¶È
+ Êä³ö: crc16
+*/
+extern u16 calcCRC( u8 *pBuffer, u16 BufferLength);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//RTCÇý¶¯Ïà¹Ø
+//ʱ¼ä½á¹¹Ìå
+typedef struct
+{
+ uint8_t year; //Äê
+ uint8_t month; //ÔÂ
+ uint8_t day; //ÈÕ
+ uint8_t week; //ÐÇÆÚ
+ uint8_t hour; //ʱ
+ uint8_t minute; //·Ö
+ uint8_t second; //Ãë
+}_SystemTime ;
+/*
+ RTC³õʼ»¯
+*/
+extern void rtc_init(void);
+/*
+ »ñȡϵͳÈÕÆÚ
+*/
+extern uint8_t rtc_get_time(_SystemTime* t);
+
+/*
+ ÉèÖÃϵͳÈÕÆÚ
+*/
+extern uint8_t rtc_set_time(_SystemTime* t);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//EEPROMÏà¹Ø
+
+////#define E2PROM_SIZE (64*1024/8UL)
+/*
+ ʹÄÜE2PROMд±£»¤
+*/
+extern void e2prom_lock(void);
+/*
+ ʧÄÜE2PROMд±£»¤
+*/
+extern void e2prom_unlock(void);
+/*********************************************
+*¹¦ÄÜ:I2C×ÜÏß³õʼ»¯,Ö÷³ÌÐòÊ×Ïȵ÷ÓøóÌÐò
+*²ÎÊý:time_factor ÑÓʱϵÊý,Ò»°ã´«0£¬Ê¹ÓÃĬÈϵľÍÐÐ
+*********************************************/
+extern void e2prom_init(u32 time_factor);
+
+/******************************************************************************
+¹¦ÄÜ£º´ÓÖ¸¶¨µØÖ·¿ªÊ¼¶ÁÈ¡Ö¸¶¨³¤¶ÈµÄÊý¾Ý
+²ÎÊý£º
+ *dest_buff - ´æ·Å¶Á³öÊý¾ÝµÄÖ¸Õë
+ addr - ¿ªÊ¼µØÖ·
+ len - Òª¶Á³öµÄ³¤¶È
+·µ»ØÖµ£º
+ 0 - ³É¹¦
+ 1 - ʧ°Ü
+******************************************************************************/
+extern u8 e2prom_read(u8 *dest_buff, u16 addr, u16 len);
+
+/******************************************************************************
+¹¦ÄÜ£ºÐ´EEPROM¡£ÏòÖ¸¶¨µØÖ·¿ªÊ¼Ð´ÈëÖ¸¶¨³¤¶ÈµÄÊý¾Ý¡£
+²ÎÊý£º
+ *src_buff - ´æ·ÅдÈëÊý¾ÝµÄÖ¸Õë
+ addr - ¿ªÊ¼µØÖ·
+ len - ҪдÈëµÄ³¤¶È
+·µ»ØÖµ£º
+ 0 - ³É¹¦
+ 1 - ʧ°Ü
+******************************************************************************/
+extern u8 e2prom_write(u8 *src_buff, u16 addr, u16 len);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//ADCÏà¹Ø
+/*
+ ADC³õʼ»¯
+*/
+//extern void adc_init(void);
+/*
+ Ó¦ÓòãÐèÍê³ÉSYSTICKÖжϷþÎñº¯ÊýDMA1_Channel1_IRQHandler£¬²¢µ÷ÓÃDMA1_Channel1_readº¯Êý
+*/
+extern void DMA1_Channel1_read(void);
+/*
+ ²»ÐèÒªÌṩ
+*/
+//extern uint16_t adc_get_val(uint8_t ch);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//·§ÃÅÇý¶¯Ïà¹Ø
+#define valve_state_on 1
+#define valve_state_off 0
+
+/*
+ ³õʼ»¯·§ÃÅÇý¶¯IO
+*/
+extern void valve_init(void);
+
+/*
+ ÉèÖ÷§ÃÅ״̬
+ state: valve_state_on »ò valve_state_off
+*/
+extern void valve_sta_set(uint8_t sta);
+
+/*
+ »ñÈ¡·§ÃÅ״̬
+ ·µ»ØÖµ: valve_state_on »ò valve_state_off
+*/
+extern uint8_t valve_sta_get(void);
+
+/*
+ ·§ÃÅ¿ØÖÆÂß¼£¬Ð趨ÆÚµ÷ÓÃÒÑÇý¶¯·§ÃÅ¿ØÖÆ״̬»ú£¬½¨Òé
+ ÔÚÖ÷Ñ»·Öе÷ÓÃ
+*/
+extern void valve_ctrl(void);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//Á÷Á¿¼ÆÏà¹Ø
+/*
+ Á÷Á¿¼Æ³õʼ»¯
+*/
+extern void initFlowSensorDriver(void);
+/*
+ ¸üÐÂÁ÷Á¿¼ÆÂö³å¼ÆÊýÖµ£¬Ð趨ÆÚµ÷Óøú¯Êý£¬½¨ÒéÔÚSysTick_Handlerµ÷ÓÃ
+*/
+//extern void flowsensor_update_count(void);
+/*
+ »ñÈ¡Á÷Á¿¼ÆÂö³å¼ÆÊýÖµ
+*/
+extern u32 flowsensor_get_count(void);
+/*
+ ÉèÖÃÁ÷Á¿¼ÆÂö³å¼ÆÊýÖµ
+*/
+extern void flowsensor_set_count(u32 val);
+
+/*
+ »ñÈ¡Á÷Á¿¼ÆµçÁ÷AD²ÉÑùÖµ£¬ÒÔ´ËÅжÏÁ÷Á¿¼ÆÊÇ·ñÒì³££¬½¨ÒéÔÚÖ÷Ñ»·Öе÷ÓÃ(µçÁ÷Öµ=ADÖµ/4095*3.3/9.1)
+*/
+extern u16 flowsensor_sta(void);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//¼üÅÌÏà¹Ø
+//¼üÖµ¶¨Òå
+#define KEY_NONE ( 0u) //¿ÕÏÐ״̬
+#define KEY_DIG0 (10u) //Êý×Ö¼ü0
+#define KEY_DIG1 ( 1u) //Êý×Ö¼ü1
+#define KEY_DIG2 ( 2u) //Êý×Ö¼ü2
+#define KEY_DIG3 ( 3u) //Êý×Ö¼ü3
+#define KEY_DIG4 ( 4u) //Êý×Ö¼ü4
+#define KEY_DIG5 ( 5u) //Êý×Ö¼ü5
+#define KEY_DIG6 ( 6u) //Êý×Ö¼ü6
+#define KEY_DIG7 ( 7u) //Êý×Ö¼ü7
+#define KEY_DIG8 ( 8u) //Êý×Ö¼ü8
+#define KEY_DIG9 ( 9u) //Êý×Ö¼ü9
+#define KEY_ENTER (12u) //È·Èϼü
+#define KEY_CANCEL (11u) //È¡Ïû¼ü
+
+/*
+ ¼üÅ̳õʼ»¯
+*/
+//extern uint8_t keypad_init(void);
+/*
+ ¶ÁÈ¡°´¼üÖµ
+*/
+//extern uint8_t keypad_get_key(void);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//flashÏà¹Ø
+
+//¹æ¸ñ¶¨Òå
+#define FLASH_PAGE_SIZE_W25X32 256
+#define FLASH_SIZE (4 * 1024 * 1024)
+#define FLASH_PAGE_NUM 8192
+#define FLASH_SECTOR_SIZE (4*1024)
+#define FLASH_SECTOR_NUMBER 512
+#define FLASH_BLOCK_SIZE (64*1024)
+#define FLASH_BLOCK_NUM 64
+//·µ»ØÖµ
+#define NC_OK 0 //²Ù×÷³É¹¦
+#define NC_FlashErr 0x0000ffff //´íÎó
+#define NC_ElseERR 0x01 //ÆäÓà´íÎó
+#define NC_Writeable 0x02 //ÔÊÐíд
+
+/*
+ ³õʼ»¯
+*/
+extern u32 HW_Flash_Init(void);
+/*
+ ¶ÁDEVICE ID
+*/
+extern void HW_FLASH_JEDEC_ID(uint8_t *buf);
+
+/*
+ ¶ÁFLASH
+*/
+extern u32 HW_Flash_Read(uint32_t addr, uint32_t size, uint8_t *buffer);
+/*
+ Ò³²Á³ý
+*/
+extern u32 HW_Flash_PageErase(uint32_t page);
+/*
+ Ò³±à³Ì
+*/
+extern u32 Flash_Page_Program(uint32_t addr, uint32_t size, uint8_t *pbuf);
+/*
+ ÕûƬ²Á³ý£ºÐèÒªºÜ³¤Ê±¼ä£¬Êµ¼Ê²âÊÔ40s
+*/
+extern u32 HW_Flash_ChipErase(void);
+/*
+ ²»´ø²Á³ýµÄд
+*/
+extern u32 HW_Flash_NotEraseWrite(uint32_t dest, uint32_t size, uint8_t *src);
+/*
+ ´ø²Á³ýµÄд
+*/
+extern u32 HW_Flash_SmartWrite(uint32_t addr, uint32_t size, uint8_t *src);
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//¿´ÃŹ·Ïà¹Ø
+/*
+ ¹¦ÄÜ:³õʼ»¯¿´ÃŹ·
+*/
+extern void initWatchDog(void);
+/*
+ ι¹·£¬ÐèÒªÔÚÖ÷Ñ»·Öе÷ÓÃ
+*/
+extern void feedWatchDog(void);
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//mifare one hw lib
+
+#define KEYA 0x60 //AÃÜÂë
+#define KEYB 0x61 //BÃÜÂë
+
+//²ÎÊýRequestMode£º
+#define PICC_REQ_ALL 0x52
+#define PICC_REQ_IDLE 0x26
+
+/*
+ ³õʼ»¯¶Á¿¨½Ó¿Ú
+*/
+extern void HW_SPI_RF_CfgInit(void);
+
+/*
+
+ ¹¦ÄÜ: RC530Éϵ縴λ
+ 1. ½«RC530´Óµôµçģʽ»½ÐÑ£¬²¢Íê³É³õʼ»¯
+ 2. »ò½«RC530ÖØи´Î»
+*/
+ extern u8 M1_RCReset(void);
+
+/*
+ ¹¦ÄÜ: È¡µÃ¿¨ÐòÁкÅ
+ Êä³ö: uchar *pSN - ¿¨ÐòÁкÅ
+ ·µ»Ø: 0-²Ù×÷³É¹¦ ÆäËûÖµ-²Ù×÷ʧ°Ü
+*/
+extern u8 GetM1SN( u8 *pSN );
+
+/*
+
+ ¹¦ÄÜ: Ñ°¿¨
+ ²ÎÊý: RequestMode-Ñ°¿¨Ä£Ê½£¬ÎªIDLE »ò ALL atq-¿¨Æ¬µÄÀàÐÍ ÔÝÎÞÓÃ
+ ·µ»Ø: µ±Îª0x00 ʱ±íʾÓп¨£¬·ñÔòÎÞ¿¨
+*/
+extern u8 M1_Request(u8 RequestMode, u8 * atq );
+
+/*
+
+ ¹¦ÄÜ: ¼ÓÔØÃÜÔ¿
+ ²ÎÊý: ÃÜÔ¿
+ ·µ»Ø: 0-²Ù×÷³É¹¦ ÆäËûÖµ-²Ù×÷ʧ°Ü
+*/
+//extern u8 Load_RAM ( u8 * RawCode );
+
+/*
+
+ ¹¦ÄÜ: ͨ¹ý¿éºÅ½øÐÐУÑ飬֧³ÖS50£¬S70¿¨
+ ²ÎÊý: AuthMode-AÃÜÂë »ò BÃÜÂë snr:¿¨Î¨Ò»ºÅ block:¿éºÅ key:ÃÜÔ¿
+ ·µ»Ø: 0-²Ù×÷³É¹¦ ÆäËûÖµ-²Ù×÷ʧ°Ü
+*/
+extern u8 M1_AuthBlk( u8 AuthMode, u8 *Snr, u8 Block, u8 *key );
+
+extern u8 M1_Select(u8 *Snr);
+/*
+ M1_E2Read ¶ÁÈ¡RC500µÄE2ÖеÄÊý¾Ý
+ Addr :E2ÆðʼµØÖ·(Addr < 80H )
+ length :ÒªÇó¶ÁÈ¡µÄ×Ö½ÚÊý( СÓÚµÈÓÚ16 )
+ pBuffer :¶Á³öÊý¾ÝµÄ»º³åÇø
+ ·µ»ØÖµ £º0±íʾд³É¹¦
+*/
+//extern u8 M1_E2Read( u8 Addr, u8 length, u8 * pBuffer);
+
+/*
+ M1_E2Write ½«Êý¾ÝдÈëRC500µÄE2ÖÐ
+ Addr :E2ÆðʼµØÖ·( 0x10 <=Addr < 0x1ff )
+ length :ÒªÇóдÈëµÄ×Ö½ÚÊý( СÓÚµÈÓÚ16 )
+ pBuffer :ҪдÈëÊý¾ÝµÄ»º³åÇø
+ ·µ»ØÖµ £º0±íʾд³É¹¦
+*/
+//extern u8 M1_E2Write( unsigned int Addr, u8 length, u8 * pBuffer);
+
+/*
+ ¹¦ÄÜ£º ¶Á¿¨°åÓ²¼þµôµç£º
+ º¯ÊýÔÐÍ£º void HardPwrDwn() ÔÝûÓÐд
+ ²ÎÊý£º ÎÞ
+ ·µ»ØÖµ£º ÎÞ
+ ˵Ã÷£º
+ ½«¶Á¿¨°åµÄRF¡ªRST¿ØÖÆÏßÖÃΪ¸ßµçƽ£¬¶Á¿¨°å´¦ÓÚÓ²¼þµôµç״̬£¨µçÔ´Õý³£Ìṩ£©¡£
+*/
+extern void M1_HardPwrDwn( void );
+
+/*
+ M1_PCDSn ¶ÁÈ¡RC500µÈ¶Á¿¨Ð¾Æ¬µÄÐòÁкÅ
+ pSn :ÐòÁкŻº³åÇø
+ ·µ»ØÖµ £º0±íʾд³É¹¦
+*/
+extern unsigned char M1_PCDSn( unsigned char * pBuffer);
+
+/*
+ ¹¦ÄÜ£º ¶Á¿¨°å¶Á¿¨Ð¾Æ¬ÉäƵ¹Ø±Õ£º
+ º¯ÊýÔÐÍ£º void M1_RadioOff()
+ ²ÎÊý£º ÎÞ
+ ·µ»ØÖµ£º ÎÞ
+ ˵Ã÷£º
+ ½«¶Á¿¨°åÉϵĶÁ¿¨Ð¾Æ¬µÄÉäƵ·¢Ë͹صô,½µµÍ¹¦ºÄºÍ¶ÔÍâ¸ÉÈÅ
+ ´Ëʱ¶Á¿¨Ð¾Æ¬»¹ÔÚ¹¤×÷.
+*/
+extern void M1_RadioOff( void );
+
+/*
+ ¹¦ÄÜ£º ¶Á¿¨°å¶Á¿¨Ð¾Æ¬ÉäƵ´ò¿ª£º
+ º¯ÊýÔÐÍ£º void M1_RadioOn()
+ ²ÎÊý£º ÎÞ
+ ·µ»ØÖµ£º ÎÞ
+ ˵Ã÷£º
+ ½«¶Á¿¨°åÉϵĶÁ¿¨Ð¾Æ¬µÄÉäƵ·¢ËÍ´ò¿ª
+
+ M1_RadioOn() ºÍ M1_RadioOff()ÊÇÒ»¶Ôº¯Êý,ÓÃÔÚÒ»°ãÇé¿öϵĽÚÄܺͽµµÍÉäƵ¸ÉÈÅÉÏ.
+*/
+extern void M1_RadioOn( void );
+
+/*
+ Fread ¶Á¿éÊý¾Ý
+ Block :¶Á¿éºÅ
+ ReadBuffer :¶Á³öµÄÊý¾ÝµÄ»º³åÇø
+ ·µ»ØÖµ £º0±íʾ¶Á³É¹¦
+*/
+extern u8 M1_Read(u8 Block, u8 * ReadBuffer);
+
+/*
+ Fwrite д¿éÊý¾Ý
+ Block :д¿éºÅ
+ ReadBuffer :ҪдÊý¾ÝµÄ»º³åÇø
+ ·µ»ØÖµ £º0±íʾд³É¹¦
+*/
+extern u8 M1_Write( u8 Block, u8 * WriteBuffer);
+
+/*
+ ¹¦ÄÜ£º ¼ì²é¶Á¿¨Ð¾Æ¬ÊÇ·ñ·¢ÉäÕý³£
+ º¯ÊýÔÐÍ£º u8 M1_TranSta()
+ ²ÎÊý£º ÎÞ
+ ·µ»ØÖµ£º 1 - Ôز¨Î´·¢Éä
+ 0 - Ôز¨·¢Éä
+*/
+//extern u8 M1_TranSta( void );
+
+/*
+ Halt
+ ¹¦ÄÜ£º ÖÕÖ¹¿¨
+ ²ÎÊý: ÎÞ
+ ·µ»ØÖµ£ºµ±Îª0x00 ʱ±íʾ¿¨ÖÕÖ¹³É¹¦
+*/
+extern u8 M1_Halt( void );
+
+/*
+ ¹¦ÄÜ£º Mifare¿¨¿é¶Á(º¬Ñ°¿¨, Ñ¡¿¨, УÑé, ¶Á¿¨(Ò»¿é), ¿É¹©Ñ¡Ôñ)£º
+ ÊäÈ룺 u8 *pSN - ¿¨ÐòÁкÅ
+ u8 Mode - ( ¸ù¾Ý¶¨ÒåµÄ³£Á¿±í½øÐÐ"»ò"×éºÏ )
+ bit0 - AÃÜÂë»òBÃÜÂë( 0 - A 1 - B)
+ bit2 - 0 - Ñ°¿¨ 1 - ²»Ñ°¿¨
+ bit3 - 0 - ²»Ð£ÑéÃÜÂë 1 - ҪУÑéÃÜÂë
+ u8 Block - Òª¶ÁµÄ¿éºÅ
+ u8 *pKey - ÉÈÇø¶ÁдÃÜÂë
+
+ Êä³ö£º u8 *pBuffer - ¶Á³öµÄ16×Ö½ÚÊý¾Ý
+ ·µ»ØÖµ£ºµ±Îª0x00 ʱÕýÈ·¶Á³ö
+*/
+extern u8 M1_BlkRead( u8 Mode, u8 Block, u8 *pSN, u8 * pBuffer, u8 *pKey );
+
+/*
+ ¹¦ÄÜ£º Mifare¿¨¿éд(º¬Ñ°¿¨, Ñ¡¿¨, УÑé, ¶Á¿¨(Ò»¿é), ¿É¹©Ñ¡Ôñ)£º
+ ÊäÈ룺 u8 *pSN - ¿¨ÐòÁкÅ
+ u8 Mode - ( ¸ù¾Ý¶¨ÒåµÄ³£Á¿±í½øÐÐ"»ò"×éºÏ )
+ bit0 - AÃÜÂë»òBÃÜÂë( 0 - A 1 - B)
+ bit2 - 0 - Ñ°¿¨ 1 - ²»Ñ°¿¨
+ bit3 - 0 - ²»Ð£ÑéÃÜÂë 1 - ҪУÑéÃÜÂë
+ u8 Block - Òª¶ÁµÄ¿éºÅ
+ u8 *pKey - ÉÈÇø¶ÁдÃÜÂë
+ u8 *pBuffer - ҪдÈëµÄ16×Ö½ÚÊý¾Ý
+ ·µ»ØÖµ£ºµ±Îª0x00 ʱÕýÈ·¶Á³ö
+*/
+extern u8 M1_BlkWrite( u8 Mode, u8 Block, u8 *pSN, u8 * pBuffer, u8 *pKey );
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//CPU¿¨ºÍESAMÄ£¿é
+
+//¹¦ÄÜ£º³õʼ»¯SAMͨѶ½Ó¿Ú
+//²ÎÊý£ºÎÞ
+//·µ»Ø£ºÎÞ
+extern void ISO7816_USART_Init(void);
+
+//ich¶¨Òå
+#define PROTOCOL_T0_CH1 1 // ESAMÄ£¿é
+#define PROTOCOL_TCL_PCD0 0x80 //·Ç½Ó´¥Ê½¿¨
+
+//¿¨Éϵ磬ÓÃÓÚSAM¿¨À临λ
+//²ÎÊý£ºcid=0
+// ich ͨµÀºÅ
+//·µ»Ø£º0³É¹¦
+extern unsigned short Gen_PowerOnCard(unsigned char cid, int ich);
+
+//¹Ø±ÕSAM¿¨µçÔ´
+//²ÎÊý£ºich ͨµÀºÅ
+extern void Gen_PowerOffCard(int ich);
+
+//¹¦ÄÜ£º¿¨¸´Î»Ç°³õʼ»¯Ïà¹ØÊý¾Ý½á¹¹£¨ÓÃÓÚSAM»ò¿¨Æ¬£©
+//²ÎÊý£ºcid=0
+// ich ͨµÀºÅ
+void Gen_ResetInfo( unsigned char cid, int ich );
+//¹¦ÄÜ£º¿¨¸´Î»£¨¿ÉÓÃÓÚ¸´Î»SAM»ò¿¨Æ¬£©
+//²ÎÊý£ºcid=0
+// ich ͨµÀºÅ
+//·µ»Ø£º0³É¹¦
+extern unsigned short Gen_ResetCard(unsigned char cid, int ich);
+
+//¹¦ÄÜ£ºActivation of a PICC in IDLE mode.£¨ÓÃÓÚ¿¨Æ¬£©
+//²ÎÊý£ºbr (IN) Baudrate for MIFARE communication 0 106 kBaud
+// atq (OUT) Answer to Request
+// sak (OUT) Select acknowledge
+// uid (OUT) up to 10 bytes UID
+// uid_len (OUT) length of the UID
+//·µ»Ø£º0 ok
+extern short Mf500PiccActivateIdle(unsigned char br,
+ unsigned char *atq,
+ unsigned char *sak,
+ unsigned char *uid,
+ unsigned char *uid_len);
+
+//¹¦ÄÜ£ºSends the PICC into the halt state.
+//²ÎÊý£ºNone
+//·µ»Ø£º0 ok
+//extern short Mf500PiccHalt(void);
+
+//¹¦ÄÜ£ºÔÚÉäƵ¿¨¼ÓµçÇÒ½øÈë144433-4Çé¿öϲâÊÔ¿¨Æ¬µÄ´æÔÚ
+//²ÎÊý£ºÎÞ
+//·µ»Ø£º0 ¿¨´æÔÚ
+// ÆäËû ¿¨²»´æÔÚ
+extern unsigned char PICC_TclCheckRFRounge(void);
+
+//¹¦ÄÜ£ºÊý¾Ý½»»»£¨¿ÉÓÃÓÚ¸´Î»SAM»ò¿¨Æ¬£©
+//²ÎÊý£ºcid=0
+// nad_send=0
+// cmd_buf ÃüÁ³åÇø
+// cmd_len ÃüÁ¶È
+// ExpectedResponseLength ÆÚÍû¿¨Æ¬»Ø¸´µÄÊý¾Ý³¤¶È
+// rec_buf ÓÃÓÚ»ñÈ¡·µ»ØÊý¾ÝµÄÖ¸Õë
+// rec_buf_len ʵ¼Ê½ÓÊÕµ½µÄÊý¾Ý³¤¶È
+// ich ͨµÀºÅ
+//·µ»Ø£º0³É¹¦
+extern unsigned short Gen_Exchange(unsigned char cid,
+ unsigned char nad_send,
+ unsigned char *cmd_buf,
+ unsigned char cmd_len,
+ unsigned char ExpectedResponseLength,
+ unsigned char **rec_buf,
+ unsigned char *rec_buf_len,
+ int ich);
+
+//¹¦ÄÜ: ÉèÖÃ3DES(Ë«±¶³¤)ÃÜÔ¿
+//²ÎÊý: 16×Ö½ÚÃÜÔ¿Öµ
+//·µ»Ø: 0 ³É¹¦
+// ÆäËû ʧ°Ü
+//extern u8 des_set_keys(u8 key[16]);
+
+//¹¦ÄÜ: 3des¼ÓÃÜ
+//²ÎÊý: src[8] ÊäÈë8×Ö½ÚÃ÷ÎÄÊý¾Ý
+// dest[8] Êä³ö8×Ö½ÚÃÜÎÄÊý¾Ý
+//·µ»Ø: ÎÞ
+//extern void des_encrypt(u8 src [ 8 ], u8 dest [ 8 ]);
+
+//¹¦ÄÜ: 3des½âÃÜ
+//²ÎÊý: src[8] ÊäÈë8×Ö½ÚÃÜÎÄÊý¾Ý
+// dest[8] Êä³ö8×Ö½ÚÃ÷ÎÄÊý¾Ý
+//·µ»Ø: ÎÞ
+//extern void des_decrypt(u8 src [ 8 ], u8 dest [ 8 ]);
+
+//¹¦ÄÜ: ²Á³ýESAM¿ªÆÕ¿¨½á¹¹£¬²¢Ìæ»»³õʼÖ÷¿ØÃÜԿΪ16×Ö½ÚÈ«0
+//²ÎÊý: ÎÞ
+//·µ»Ø: 0x9000 ³É¹¦
+// 0x0000 ²»ÊÇ¿ªÆÕ³õʼESAM¿¨¿Õ¼ä£¬²»ÄܽøÐвÁ³ý²Ù×÷
+// ÆäËû ʧ°Ü
+//extern u16 erase_mf(void);
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//CANͨѶÏà¹Ø
+typedef struct
+{
+ unsigned int id; /* 29 bit identifier */
+ unsigned char data[8]; /* Data field */
+ unsigned char len; /* Length of data field in bytes */
+ unsigned char ch; /* Object channel */
+ unsigned char format; /* 0 - STANDARD, 1- EXTENDED IDENTIFIER */
+ unsigned char type; /* 0 - DATA FRAME, 1 - REMOTE FRAME */
+}CAN_msg; //CANͨѶÏûÏ¢¶¨Òå
+
+//CANͨѶͨµÀ¶¨Òå(Object channel)
+#define DEF_CAN_CHANNEL_SEND 0x01
+#define DEF_CAN_CHANNEL_RECV 0x01
+
+//CANÖ¡¸ñʽ
+#define STANDARD_FORMAT 0
+#define EXTENDED_FORMAT 1
+
+//CANÖ¡ÀàÐÍ
+#define DATA_FRAME 0
+#define REMOTE_FRAME 1
+
+
+/**********************************************************************************************
+;º¯ÊýÔÐÍ£ºunsigned int APP_CAN_Init( U32 baud, U08 addr )
+;º¯Êý¹¦ÄÜ£º³õʼ»¯ºÍÆô¶¯CAN¿ØÖÆÆ÷
+;Êä È룺baud - CAN²¨ÌØÂÊ addr - ´Ó»úµØÖ·
+;·µ »Ø Öµ£º0 - ³É¹¦ ÆäËû - ʧ°Ü
+**********************************************************************************************/
+extern unsigned int APP_CAN_Init( u32 baud, u8 addr );
+
+//ʹÓÃCAN¿ØÖÆÆ÷·¢ËÍÏûÏ¢
+extern unsigned int CAN_Send(unsigned int ctrl, CAN_msg *msg, unsigned short timeout);
+
+//CAN¿ØÖÆÆ÷½ÓÊÕÏûÏ¢
+extern unsigned int CAN_Recieve( CAN_msg *msg );
+
+//»ñÈ¡CAN·¢ËÍ״̬ 0£ºÃ»·¢ËÍ 1£ºÔÚ·¢ËÍ
+extern unsigned char Get_CAN_TxState(void);
+
+//»ñÈ¡CAN·¢ËÍ״̬ 0£ºÃ»½ÓÊÕ 1£ºÔÚ½ÓÊÕ
+extern unsigned char Get_CAN_RxState(void);
+
+extern void USB_HP_CAN1_TX (void);
+
+
+extern void USB_LP_CAN1_RX0(void);
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//ÏÔʾÏà¹Ø
+/**
+ * ´ò¿ª±³¹â
+ */
+void glcd_bkl_on(void);
+
+/**
+ * ¹Ø±Õ±³¹â
+ */
+void glcd_bkl_off(void);
+
+/**
+ * ³õʼ»¯LCDÏÔʾ
+ */
+void glcd_init(void);
+
+/**
+ * ÏÔʾÊý¾Ý
+ */
+void glcd_write(void);
+
+/**
+ * Çå³ýÏÔʾ
+ */
+void glcd_clear(void);
+
+/**
+ * Çå³ýÏÔʾ»º³åÇø
+ */
+void glcd_clear_buffer(void);
+
+//ÏÔʾ²¿·ÖÇë²Î¼ûËùÌṩԴÂ룬ÐèÒªµÄ×ÔÐÐÔö¼Ó
+
+#endif
diff --git a/g401302/src/nec_apdu.c b/g401302/src/nec_apdu.c
new file mode 100644
index 0000000..5e31693
--- /dev/null
+++ b/g401302/src/nec_apdu.c
@@ -0,0 +1,100 @@
+#include <string.h>
+#include "../../nec_hardware.h"
+#include "../../nec_apdu.h"
+
+#define RETCODE_OK 0x9000
+
+int8 psam_poweron(uint8 cid)
+{
+ return Gen_PowerOnCard(cid, PROTOCOL_T0_CH1);
+}
+void psam_powreoff(uint8 cid)
+{
+ Gen_PowerOffCard(cid);
+}
+
+static uint8 gPICC_SNR[8]; /* å¡çSNå? */
+int8 card_request(uint8* sak,uint8 snr[8])
+{
+ uint8 gPICC_SNR_LEN; /* æ?è·åçå¡çSNæ°æ®é¿åº¦ */
+ uint8 gPICC_ATQA[2]; /* */
+ uint8 gPICC_SAK; /* */
+
+ if(!Mf500PiccActivateIdle(0, gPICC_ATQA, &gPICC_SAK, gPICC_SNR, &gPICC_SNR_LEN))
+ {
+ *sak = gPICC_SAK;
+ memcpy(snr,gPICC_SNR,8);
+ return 0;
+ }
+ return -1;
+}
+int8 card_m1_mode(uint8 cardphyid[8])
+{
+ uint8 buff[2];
+ if(M1_Request(PICC_REQ_IDLE, buff))
+ {
+ if(M1_Request(PICC_REQ_IDLE, buff))
+ {
+ return -1;
+ }
+ }
+ if(!GetM1SN(cardphyid))
+ {
+ if(!M1_Select(cardphyid))
+ {
+ return 0;
+ }
+ }
+ return -1;
+}
+int8 card_rf_reset(void)
+{
+ return M1_RCReset();
+}
+int8 card_cpu_mode(void)
+{
+ Gen_ResetInfo(0, PROTOCOL_TCL_PCD0);
+ return Gen_ResetCard(0, PROTOCOL_TCL_PCD0);
+}
+int8 card_cpu_exist(void)
+{
+ return PICC_TclCheckRFRounge();
+}
+
+void card_radio_on(void)
+{
+ M1_RadioOn();
+}
+void card_radio_off(void)
+{
+ M1_RadioOff();
+}
+uint16 card_m1_auth(uint8* cardphyid,uint8 blockno, uint8 key[6])
+{
+ return M1_AuthBlk(KEYA,cardphyid,blockno,key);
+}
+uint16 card_m1_read(uint8 blockno,uint8 readbuf[16])
+{
+ return M1_Read(blockno,readbuf);
+}
+uint16 card_m1_write(uint8 blockno,uint8 writebuf[16])
+{
+ return M1_Write(blockno,writebuf);
+}
+uint16 card_cpu_exchange(uint8* cmd_buf,
+ uint8 cmd_len,
+ uint8 ExpectedResponseLength,
+ uint8** rec_buf,
+ uint8* rec_buf_len)
+{
+ uint16 ret;
+ ret =Gen_Exchange(0,0, cmd_buf, cmd_len, ExpectedResponseLength, rec_buf, rec_buf_len,
+ PROTOCOL_TCL_PCD0);
+ if(ret != RETCODE_OK)
+ {
+ return Gen_Exchange(0,0, cmd_buf, cmd_len, ExpectedResponseLength, rec_buf, rec_buf_len,
+ PROTOCOL_TCL_PCD0);
+ }
+ return RETCODE_OK;
+}
+
diff --git a/g401302/src/nec_hardware.c b/g401302/src/nec_hardware.c
new file mode 100644
index 0000000..3f86ff3
--- /dev/null
+++ b/g401302/src/nec_hardware.c
@@ -0,0 +1,59 @@
+#include "../../nec_hardware.h"
+
+/*Ó²¼þ³õʼ»¯*/
+uint16 sp_init(void)
+{
+ valve_init();
+ initFlowSensorDriver();
+ SysTick_cfg();
+ e2prom_init(0);
+ HW_Flash_Init();
+ rtc_init();
+ glcd_init();
+ usart_init();
+ initWatchDog();
+
+ HW_SPI_RF_CfgInit();
+
+ ISO7816_USART_Init(); //SAMÄ£¿é³õʼ»¯
+
+ if(Gen_PowerOnCard(0,PROTOCOL_T0_CH1)) //¸´Î»SAMÄ£¿éʧ°Ü
+ {
+ return 1;
+ }
+ return 0;
+}
+/*ι¹·*/
+void sp_feed_dog(void)
+{
+ feedWatchDog();
+}
+
+/*Ö÷Ñ»·µ÷Óà ·§ÃÅ¿ØÖÆ*/
+void sp_valve_control(void)
+{
+ valve_ctrl();
+}
+/*Ö÷Ñ»·µ÷Óà Âö³å¼ÆÊý¸üпØÖÆ*/
+void sp_flowsensor_control(void)
+{
+ //flowsensor_update_count();
+}
+
+/*»ñÈ¡µ±Ç°Á÷Á¿¼ÆÂö³å¼ÆÊý*/
+uint32 sp_flowsensor_get_count(void)
+{
+ return flowsensor_get_count();
+}
+
+/*Á÷Á¿¼ÆÂö³å¼ÆÊýÇåÁã */
+void sp_flowsensor_count_clear(void)
+{
+ flowsensor_set_count(0);
+}
+/*0--Á÷Á¿¼ÆÕý³£ 1--Á÷Á¿¼ÆÒì³£*/
+uint8 sp_flowsensor_check_valid(void)
+{
+ return flowsensor_sta();
+}
+
diff --git a/g401302/src/stm32f10x_it.c b/g401302/src/stm32f10x_it.c
new file mode 100644
index 0000000..82b6810
--- /dev/null
+++ b/g401302/src/stm32f10x_it.c
@@ -0,0 +1,168 @@
+/**
+ ******************************************************************************
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief Main Interrupt Service Routines.
+ * This file provides template for all exceptions handler and
+ * peripherals interrupt service routine.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "G401_drv_hw_V01.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/* Cortex-M3 Processor Exceptions Handlers */
+/******************************************************************************/
+
+/**
+ * @brief This function handles NMI exception.
+ * @param None
+ * @retval None
+ */
+void NMI_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles Hard Fault exception.
+ * @param None
+ * @retval None
+ */
+void HardFault_Handler(void)
+{
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Memory Manage exception.
+ * @param None
+ * @retval None
+ */
+void MemManage_Handler(void)
+{
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Bus Fault exception.
+ * @param None
+ * @retval None
+ */
+void BusFault_Handler(void)
+{
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Usage Fault exception.
+ * @param None
+ * @retval None
+ */
+void UsageFault_Handler(void)
+{
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles SVCall exception.
+ * @param None
+ * @retval None
+ */
+void SVC_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles Debug Monitor exception.
+ * @param None
+ * @retval None
+ */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles PendSVC exception.
+ * @param None
+ * @retval None
+ */
+void PendSV_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles SysTick Handler.
+ * @param None
+ * @retval None
+ */
+void SysTick_Handler(void)
+{
+ TimerTick();
+ ComOverTimeProceed();
+}
+
+void USART1_IRQHandler(void)
+{
+}
+
+void UART5_IRQHandler(void)
+{
+ usart_isr_proc();
+
+ //´Ë´¦¿ÉÌí¼ÓÓ¦Óòã´úÂë
+}
+
+void ADC_IRQHandler(void)
+{
+}
+
+void DMA1_Channel1_IRQHandler(void)
+{
+ //DMA1_Channel1_read();
+}
+void USB_HP_CAN1_TX_IRQHandler (void)
+{
+ USB_HP_CAN1_TX ();
+}
+void USB_LP_CAN1_RX0_IRQHandler (void)
+{
+ USB_LP_CAN1_RX0();
+}
diff --git a/g401302/src/stm32f10x_it.h b/g401302/src/stm32f10x_it.h
new file mode 100644
index 0000000..9fd17c0
--- /dev/null
+++ b/g401302/src/stm32f10x_it.h
@@ -0,0 +1,65 @@
+/**
+ ******************************************************************************
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TIM4_IRQHandler(void);
+void USART1_IRQHandler(void);
+void UART5_IRQHandler(void);
+void DMAChannel4_IRQHandler(void);
+void DMAChannel5_IRQHandler(void);
+void EXTI0_IRQHandler(void);
+void EXTI1_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+void USB_HP_CAN1_TX_IRQHandler (void);
+void USB_LP_CAN1_RX0_IRQHandler (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/icc_apdu_lib/CPU.H b/icc_apdu_lib/CPU.H
new file mode 100644
index 0000000..da932ce
--- /dev/null
+++ b/icc_apdu_lib/CPU.H
@@ -0,0 +1,52 @@
+/*
+**************************************************************************************************************
+* C P U Ïà ¹Ø µÄ Ó² ¼þ ¶¨ Òå
+*
+* ×÷ Õߣº ÕŽø
+* °æ ±¾£º
+* ÈÕ ÆÚ£º
+**************************************************************************************************************
+*/
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ ¶¨ Òå
+**************************************************************************************************************
+*/
+ typedef void CPU_VOID;
+ typedef unsigned char CPU_CHAR; /* 8-bit character */
+ typedef unsigned char CPU_BOOLEAN; /* 8-bit boolean or logical */
+ typedef unsigned char CPU_INT08U; /* 8-bit unsigned integer */
+ typedef signed char CPU_INT08S; /* 8-bit signed integer */
+ typedef unsigned short CPU_INT16U; /* 16-bit unsigned integer */
+ typedef signed short CPU_INT16S; /* 16-bit signed integer */
+ typedef unsigned int CPU_INT32U; /* 32-bit unsigned integer */
+ typedef signed int CPU_INT32S; /* 32-bit signed integer */
+ typedef float CPU_FP32; /* 32-bit floating point */
+ typedef double CPU_FP64; /* 64-bit floating point */
+
+
+ typedef unsigned char uchar;
+ typedef unsigned short ushort;
+ typedef unsigned int uint;
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+
+
+#endif
+
diff --git a/icc_apdu_lib/CardErrorCode.h b/icc_apdu_lib/CardErrorCode.h
new file mode 100644
index 0000000..3957e63
--- /dev/null
+++ b/icc_apdu_lib/CardErrorCode.h
@@ -0,0 +1,58 @@
+
+#ifndef CARDERRNO_H
+#define CARDERRNO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// T=CL Error Codes Base Address Start: -1100
+// Base Address End: -1150
+//////////////////////////////////////////////////////////////////////////////
+#define TCL_ERR_BASE_START 0x1000
+
+#define TCL_OK 0
+//#define TCL_NOTAGERR (TCL_ERR_BASE_START +0x1)
+#define TCL_CRCERR (TCL_ERR_BASE_START +0x2)
+//#define TCL_PRITYERR (TCL_ERR_BASE_START +0x3)
+#define TCL_OTHERERR (TCL_ERR_BASE_START +0x4)
+//#define TCL_SERNRERR (TCL_ERR_BASE_START +0x5)
+//#define TCL_BITCOUNTERR (TCL_ERR_BASE_START +0x6)
+//#define TCL_POLLING (TCL_ERR_BASE_START +0x7)
+//#define TCL_RF_CHANNEL (TCL_ERR_BASE_START +0x8)
+//#define TCL_MULTACT_DISABLED (TCL_ERR_BASE_START +0x9)
+//#define TCL_MULTACT_ENABLED (TCL_ERR_BASE_START +0x10)
+//#define TCL_CID_NOT_ACTIVE (TCL_ERR_BASE_START +0x11)
+//#define TCL_BITANTICOLL (TCL_ERR_BASE_START +0x12)
+//#define TCL_UIDLEN (TCL_ERR_BASE_START +0x13)
+#define TCL_CIDINVALID (TCL_ERR_BASE_START +0x14)
+#define TCL_ATSLEN (TCL_ERR_BASE_START +0x15)
+//#define TCL_NO_ATS_AVAILABLE (TCL_ERR_BASE_START +0x16)
+//#define TCL_ATS_ERROR (TCL_ERR_BASE_START +0x17)
+#define TCL_FATAL_PROTOCOL (TCL_ERR_BASE_START +0x18)
+//#define TCL_RECBUF_OVERFLOW (TCL_ERR_BASE_START +0x19)
+//#define TCL_SENDBYTENR (TCL_ERR_BASE_START +0x20)
+//#define TCL_TRANSMERR_HALTED (TCL_ERR_BASE_START +0x21)
+//#define TCL_TRANSMERR_NOTAG (TCL_ERR_BASE_START +0x22)
+//#define TCL_BAUDRATE_NOT_SUPPORTED_PICC (TCL_ERR_BASE_START +0x23)
+//#define TCL_CID_NOT_SUPPORTED (TCL_ERR_BASE_START +0x24)
+//#define TCL_NAD_NOT_SUPPORTED (TCL_ERR_BASE_START +0x25)
+//#define TCL_PROTOCOL_NOT_SUPPORTED (TCL_ERR_BASE_START +0x26)
+#define TCL_PPS_FORMAT (TCL_ERR_BASE_START +0x27)
+//#define TCL_ERROR (TCL_ERR_BASE_START +0x28)
+#define TCL_NADINVALID (TCL_ERR_BASE_START +0x30)
+//#define TCL_OTHER_ERR (TCL_ERR_BASE_START +0x31)
+//#define TCL_BAUDRATE_NOT_SUPPORTED_PCD (TCL_ERR_BASE_START +0x32)
+//#define TCL_CID_ACTIVE (TCL_ERR_BASE_START +0x33)
+
+#define TCL_ERR_BASE_END (TCL_ERR_BASE_START +0x49)
+
+#define TCL_2LAYER_ERR (TCL_ERR_BASE_START +0x80)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CARDERRNO_H
+
diff --git a/icc_apdu_lib/ICC_APDU_LIB.H b/icc_apdu_lib/ICC_APDU_LIB.H
new file mode 100644
index 0000000..4ce4646
--- /dev/null
+++ b/icc_apdu_lib/ICC_APDU_LIB.H
@@ -0,0 +1,68 @@
+/*
+**************************************************************************************************************
+* RF Ä£ ¿é Óë SAM Ä£ ¿é ISO7816 Çý ¶¯ ¿â
+*
+* _____ ISO7816-2 Ó¦ÓÃÐÒéÊý¾Ýµ¥Î» Çý ¶¯_____
+*
+* Ãè Êö£º ½«Ó¦ÓÃÐÒ飨APDU£©Ó°Éäµ½É趨µÄ´«ÊäÐÒé(TPDU)ºÍ½Ó¿ÚÉÏ
+*
+* Åä Öãº
+* CPU :
+* ÍâʱÖÓ :
+* CPUÔËÐÐʱÖÓ :
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.50Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ ¶ÔRFÄ£¿é²Ù×÷ʱµÄSPI½Ó¿Ú¹²ÓÃÎÊÌâµÄ´¦Àí¡£
+*
+* ¿â Ãû£º ICC_APDU_LIB_V2.0.LIB
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º 2.0
+*
+* ÈÕ ÆÚ£º 2009-05-31
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+#ifndef __ICC_APDU_LIB_H__
+#define __ICC_APDU_LIB_H__
+
+
+
+ #include "ICC_APDU_Maper.H"
+ #include "T0T1.H"
+ #include "TCL.H"
+ #include "ISOUSARTDriver.H"
+ #include "MFRC500.h"
+ #include "MfErrNo.h"
+ #include "RICReg.h"
+
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+
+
+#endif
diff --git a/icc_apdu_lib/ICC_APDU_Maper.c b/icc_apdu_lib/ICC_APDU_Maper.c
new file mode 100644
index 0000000..69b1b39
--- /dev/null
+++ b/icc_apdu_lib/ICC_APDU_Maper.c
@@ -0,0 +1,264 @@
+/*
+**************************************************************************************************************
+* ISO7816-1 T0,T1( Ó¦ÓÃÐÒéÊý¾Ýµ¥Î»²ã ) Ó¦ Óà РÒé ²ã Çý ¶¯
+*
+* _____ ISO7816-2 Ó¦ÓÃÐÒéÊý¾Ýµ¥Î» Çý ¶¯_____
+*
+* Ãè Êö£º IC¿¨Ó¦ÓòãÐÒéÓ°Éä³ÌÐò,½«Ó¦ÓÃÐÒ飨APDU£©Ó°Éäµ½É趨µÄ´«ÊäÐÒé(TPDU)ºÍ½Ó¿ÚÉÏ
+*
+* Åä Öãº
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.23AÆƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ T0,T1´«ÊäÐÒé·ûºÏISO7816-2£¬EMV±ê×¼£»
+*
+* ²ã Ãû£º ICC_APDU_Maper.H
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V1.0
+*
+* ÈÕ ÆÚ£º 2008-03-31
+*
+* Copyright (c) 2008 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+ #include "LIB_Includes.H"
+
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+//====>>È«¾Ö±äÁ¿
+ unsigned char ucMemPool[MEMORY_BUFFER_SIZE]; /* ͨÐÅ»º³åÇø,Óû§¿¨Êý¾Ý²Ù×÷µÄʵ¼ÊÄÚ´æ¿Õ¼ä */
+ unsigned char scMemPool[MEMORY_BUFFER_SIZE]; /* ͨÐÅ»º³åÇø,SAM¿¨Êý¾Ý²Ù×÷µÄʵ¼ÊÄÚ´æ¿Õ¼ä */
+
+
+//====>>¾Ö²¿±äÁ¿
+ ICCSTRUCT IccInfo; /* IC¿¨×´Ì¬¶¨Òå */
+ PICCSTRUCT PiccInfo; /* RF¿¨Í¨ÐÅÐÅÏ¢Êý¾Ý½á¹¹ */
+
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+/*
+**************************************************************************************************************
+* ³õ ʼ »¯ ¿¨ ЊϢ Êý ¾Ý ½á ¹¹
+*
+* Ãè Êö£º½Ó´¥Ê½·Ç½Ó´¥Ê½ ³õ ʼ »¯ ¿¨ ЊϢ Êý ¾Ý ½á ¹¹
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+*
+* ·µ »Ø£ºÎÞ
+*
+**************************************************************************************************************
+*/
+ void Gen_ResetInfo( unsigned char cid, int ich )
+ {
+ switch (ich){
+ case PROTOCOL_T0_CH0: //PSAM1
+ case PROTOCOL_T0_CH1: //PSAM2
+ case PROTOCOL_T0_CH2: //½Ó´¥Ê½CPU
+ case PROTOCOL_T1_CH0:
+ ResetIccInfo( cid,&IccInfo );
+ break;
+
+ case PROTOCOL_TCL_PCD0:
+ ResetPiccInfo( cid, &PiccInfo );
+ break;
+ }
+ }
+
+/*
+**************************************************************************************************************
+* ¿¨ ÉÏ µç£¬Àä ¸´ λ
+*
+* Ãè Êö£º½Ó´¥Ê½·Ç½Ó´¥Ê½ ÉϵçÀ临λ
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+ unsigned short Gen_PowerOnCard( unsigned char cid, int ich )
+ {
+ unsigned short rcode = 0x003A;
+ switch (ich){
+ case PROTOCOL_T0_CH0: //PSAM1
+ case PROTOCOL_T0_CH1: //PSAM2
+ case PROTOCOL_T0_CH2: //½Ó´¥Ê½CPU
+ case PROTOCOL_T1_CH0:
+ ResetIccInfo(cid,&IccInfo);
+ rcode = T0PowerOnCard(ich);
+ break;
+
+ case PROTOCOL_TCL_PCD0:
+ rcode = TclGetAts(cid,&PiccInfo);
+ break;
+ }
+ return rcode;
+ }
+
+/*
+**************************************************************************************************************
+* ¿¨ Ï µç
+*
+* Ãè Êö£º¿¨Ïµç
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+ void Gen_PowerOffCard( int ich )
+ {
+ switch (ich){
+ case PROTOCOL_T0_CH0: //PSAM1
+ case PROTOCOL_T0_CH1: //PSAM2
+ case PROTOCOL_T0_CH2: //½Ó´¥Ê½CPU
+ case PROTOCOL_T1_CH0:
+ ResetIccInfo(0,&IccInfo);
+ T0PowerOffCard(ich);
+ break;
+
+ case PROTOCOL_TCL_PCD0:
+ break;
+ }
+ return ;
+ }
+
+/*
+**************************************************************************************************************
+* ¿¨ ÈÈ ¸´ λ
+*
+* Ãè Êö£º½Ó´¥Ê½·Ç½Ó´¥Ê½ ÉϵçÀ临λ
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+ unsigned short Gen_ResetCard( unsigned char cid, int ich )
+ {
+ unsigned short rcode = 0x003A;
+ switch (ich){
+ case PROTOCOL_T0_CH0: //PSAM1
+ case PROTOCOL_T0_CH1: //PSAM2
+ case PROTOCOL_T0_CH2: //½Ó´¥Ê½CPU
+ rcode = T0ResetCard(ich,&IccInfo);
+ //if(IccInfo.T == 1) ich++;
+ break;
+
+ case PROTOCOL_T1_CH0:
+ rcode = T0ResetCard(ich,&IccInfo);
+ break;
+
+ case PROTOCOL_TCL_PCD0:
+ rcode = TclGetAts(cid,&PiccInfo);
+ break;
+ }
+ return rcode;
+ }
+
+/*
+**************************************************************************************************************
+* ¿¨ Êý ¾Ý ½» »» ³Ì Ðò
+*
+* Ãè Êö£º¿¨Êý¾Ý½»»»³ÌÐò,Êý¾Ý´«ÊäÓë½ÓÊÕ ÔÝûÓÐʹÓÃ?
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* nad_send
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+ unsigned short Gen_ChangeISFC( unsigned char cid, unsigned char nad_send, int ich )
+ {
+ unsigned short rcode = 0x003A;
+ switch (ich){
+ case PROTOCOL_T1_CH0:
+ rcode = T1IFSC(cid,nad_send,ich&0xfffffffe);
+ break;
+ }
+ return rcode;
+ }
+
+/*
+**************************************************************************************************************
+* ¿¨ Êý ¾Ý ½» »» ³Ì Ðò
+*
+* Ãè Êö£º¿¨Êý¾Ý½»»»³ÌÐò,Êý¾Ý´«ÊäÓë½ÓÊÕ
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* *cmd_buf ·¢Ë͵ÄÃüÁ³åÇøÖ¸Õë
+* cmd_len ·¢Ë͵ÄÃüÁ¶È
+* ExpectedResponseLength
+* **rec_buf ½ÓÊÕÊý¾Ý»º³åÇøÖ¸Õë
+* *rec_buf_len ½ÓÊÕÊý¾Ý³¤¶È
+* ich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+ unsigned short Gen_Exchange( unsigned char cid,
+ unsigned char nad_send,
+ unsigned char *cmd_buf,
+ unsigned char cmd_len,
+ unsigned char ExpectedResponseLength,
+ unsigned char **rec_buf,
+ unsigned char *rec_buf_len,
+ int ich )
+ {
+ unsigned short rcode = 0x003A;
+// printsend(cmd_buf,cmd_len);
+ switch (ich){
+ case PROTOCOL_T0_CH0: //PSAM1
+ case PROTOCOL_T0_CH1: //PSAM2
+ case PROTOCOL_T0_CH2: //½Ó´¥Ê½CPU
+ rcode = T0Exchange(cmd_buf,cmd_len,rec_buf,rec_buf_len,ich);
+ break;
+
+ case PROTOCOL_T1_CH0:
+ rcode = T1Exchange(cid,nad_send,cmd_buf,cmd_len,rec_buf,rec_buf_len,ich&0xfffffffe);
+ break;
+
+ case PROTOCOL_TCL_PCD0:
+ rcode = TclExchange(cid,nad_send,cmd_buf,cmd_len,ExpectedResponseLength,rec_buf,rec_buf_len);
+ break;
+ }
+// printrcv(*rec_buf,*rec_buf_len);
+ return rcode;
+ }
+
diff --git a/icc_apdu_lib/ICC_APDU_Maper.h b/icc_apdu_lib/ICC_APDU_Maper.h
new file mode 100644
index 0000000..7d7bac2
--- /dev/null
+++ b/icc_apdu_lib/ICC_APDU_Maper.h
@@ -0,0 +1,198 @@
+/*
+**************************************************************************************************************
+* ISO7816-1 T0,T1( Ó¦ÓÃÐÒéÊý¾Ýµ¥Î»²ã ) Ó¦ Óà РÒé ²ã Çý ¶¯
+*
+* _____ ISO7816-2 Ó¦ÓÃÐÒéÊý¾Ýµ¥Î» Çý ¶¯_____
+*
+* Ãè Êö£º ½«Ó¦ÓÃÐÒ飨APDU£©Ó°Éäµ½É趨µÄ´«ÊäÐÒé(TPDU)ºÍ½Ó¿ÚÉÏ
+*
+* Åä Öãº
+* CPU :
+* ÍâʱÖÓ :
+* CPUÔËÐÐʱÖÓ :
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.50Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ T0,T1´«ÊäÐÒé·ûºÏISO7816-2£¬EMV±ê×¼£»
+*
+* ²ã Ãû£º ICC_APDU_Maper.H
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V2.0
+*
+* ÈÕ ÆÚ£º 2009-05-21
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+#ifndef __ICC_APDU_Maper_H__
+#define __ICC_APDU_Maper_H__
+
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+ #define PROTOCOL_T0_CH0 SLOT_PSAM1_ICC /* PSAM1 */
+ #define PROTOCOL_T0_CH1 SLOT_PSAM2_ICC /* PSAM2 */
+ #define PROTOCOL_T0_CH2 SLOT_CPU_ICC /* PSAM3 ÕâÀïÖ÷ÒªÊǽӽӴ¥Ê½CPU¿¨ */
+
+//#define SLOT_PSAM1_ICC 0 // PSAM1
+//#define SLOT_PSAM2_ICC 1 // PSAM2
+//#define SLOT_CPU_ICC 2 // ½Ó´¥Ê½CPU
+
+
+ #define PROTOCOL_T1_CH0 (1<<4)+1 /* PSAM_POWER 7816-3 T=1 */
+
+ #define PROTOCOL_TCL_PCD0 0x80 /* 14443-4 T=CL */
+
+
+ #define MEMORY_BUFFER_SIZE 256 /* ͨÐÅ»º³åÇø´óС¶¨Òå PSAM¿¨µÈ */
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+
+ extern unsigned char ucMemPool[MEMORY_BUFFER_SIZE]; /* ͨÐÅ»º³åÇø,Óû§¿¨Êý¾Ý²Ù×÷µÄʵ¼ÊÄÚ´æ¿Õ¼ä */
+ extern unsigned char scMemPool[MEMORY_BUFFER_SIZE]; /* ͨÐÅ»º³åÇø,SAM¿¨Êý¾Ý²Ù×÷µÄʵ¼ÊÄÚ´æ¿Õ¼ä */
+
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+ extern void Gen_ResetInfo( unsigned char cid, int ich );
+ /* ³õ ʼ »¯ ¿¨ ЊϢ Êý ¾Ý ½á ¹¹ */
+ extern unsigned short Gen_PowerOnCard( unsigned char cid, int ich );
+ /* ¿¨ ÉÏ µç£¬Àä ¸´ λ */
+ extern void Gen_PowerOffCard( int ich );
+ /* ¿¨ Ï µç */
+ extern unsigned short Gen_ResetCard( unsigned char cid, int ich );
+ /* ¿¨ ÈÈ ¸´ λ */
+ extern unsigned short Gen_ChangeISFC( unsigned char cid, unsigned char nad_send, int ich );
+ /* ¿¨ Êý ¾Ý ½» »» ³Ì Ðò */
+ extern unsigned short Gen_Exchange( unsigned char cid, unsigned char nad_send, unsigned char *cmd_buf,
+ unsigned char cmd_len, unsigned char ExpectedResponseLength,
+ unsigned char **rec_buf, unsigned char *rec_buf_len, int ich );
+ /* ¿¨ Êý ¾Ý ½» »» ³Ì Ðò */
+
+
+/*
+**************************************************************************************************************
+* ³õ ʼ »¯ ¿¨ ЊϢ Êý ¾Ý ½á ¹¹
+*
+* Ãè Êö£º½Ó´¥Ê½·Ç½Ó´¥Ê½ ³õ ʼ »¯ ¿¨ ЊϢ Êý ¾Ý ½á ¹¹
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+*
+* ·µ »Ø£ºÎÞ
+*
+**************************************************************************************************************
+*/
+// void Gen_ResetInfo( unsigned char cid, int ich )
+/*
+**************************************************************************************************************
+* ¿¨ ÉÏ µç£¬Àä ¸´ λ
+*
+* Ãè Êö£º½Ó´¥Ê½·Ç½Ó´¥Ê½ ÉϵçÀ临λ
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+// unsigned short Gen_PowerOnCard( unsigned char cid, int ich )
+/*
+**************************************************************************************************************
+* ¿¨ Ï µç
+*
+* Ãè Êö£º¿¨Ïµç
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+// void Gen_PowerOffCard( int ich )
+/*
+**************************************************************************************************************
+* ¿¨ ÈÈ ¸´ λ
+*
+* Ãè Êö£º½Ó´¥Ê½·Ç½Ó´¥Ê½ ÉϵçÀ临λ
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+// unsigned short Gen_ResetCard( unsigned char cid, int ich )
+/*
+**************************************************************************************************************
+* ¿¨ Êý ¾Ý ½» »» ³Ì Ðò
+*
+* Ãè Êö£º¿¨Êý¾Ý½»»»³ÌÐò,Êý¾Ý´«ÊäÓë½ÓÊÕ ÔÝûÓÐʹÓÃ?
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* nad_send
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+// unsigned short Gen_ChangeISFC( unsigned char cid, unsigned char nad_send, int ich )
+/*
+**************************************************************************************************************
+* ¿¨ Êý ¾Ý ½» »» ³Ì Ðò
+*
+* Ãè Êö£º¿¨Êý¾Ý½»»»³ÌÐò,Êý¾Ý´«ÊäÓë½ÓÊÕ
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* *cmd_buf ·¢Ë͵ÄÃüÁ³åÇøÖ¸Õë
+* cmd_len ·¢Ë͵ÄÃüÁ¶È
+* ExpectedResponseLength
+* **rec_buf ½ÓÊÕÊý¾Ý»º³åÇøÖ¸Õë
+* *rec_buf_len ½ÓÊÕÊý¾Ý³¤¶È
+* ich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£ºICErrorCode
+*
+**************************************************************************************************************
+*/
+// unsigned short Gen_Exchange( unsigned char cid,
+// unsigned char nad_send,
+// unsigned char *cmd_buf,
+// unsigned char cmd_len,
+// unsigned char ExpectedResponseLength,
+// unsigned char **rec_buf,
+// unsigned char *rec_buf_len,
+// int ich )
+
+
+
+
+
+
+
+#endif
diff --git a/icc_apdu_lib/ISOUSARTDriver.H b/icc_apdu_lib/ISOUSARTDriver.H
new file mode 100644
index 0000000..24c23d0
--- /dev/null
+++ b/icc_apdu_lib/ISOUSARTDriver.H
@@ -0,0 +1,176 @@
+/*
+**************************************************************************************************************
+* ISO7816 USART µ× ²ã Ó² ¼þ ½Ó ¿Ú Çý ¶¯
+*
+* _____Ó² ¼þ µ× ²ã (7816) Çý ¶¯_____
+*
+* Ãè Êö£º Ö÷ÒªÍê³É
+* 1) Òì²½¿¨²éѯ·½Ê½¶ÁÈ¡/·¢ËÍÒ»¸ö×Ö·û (Ö÷ÒªÊÇÔÚ±¾²ãµ÷ÓÃ)
+* 2) IC¿¨µÄ¸´Î»£¬Éϵ磬ϵ磬¼ì²âµÈÓ²¼þ²Ù×÷ (ÔÚ±¾²ãÓëT0T1²ã»áµ÷ÓÃ)
+* 3) T0,T1ÐÒé´«ÊäÊý¾Ýµ¥ÔªÓ³Éä (Ö÷ÒªÊÇÔÚT0T1²ãµ÷ÓÃ)
+*
+* Åä Öãº
+* CPU :
+* ÍâʱÖÓ :
+* CPUÔËÐÐʱÖÓ :
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.50Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ ¸´Î»Ó¦´ðµÈ¹ý³Ì·ûºÏISO7816-2£¬EMV±ê×¼£»
+*
+* ²ã Ãû£º ISOUSARTDriver.C
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V2.0
+*
+* ÈÕ ÆÚ£º 2008-05-21
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+
+#ifndef __ISOUSARTDriver_H__
+#define __ISOUSARTDriver_H__
+
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+//Óû§¶¨Ê±Æ÷
+#define MAXUSERTIMERS 16 //Óû§¶¨Ê±Æ÷ÊýÁ¿
+#define MAXTIMERSTICK 100000 //Óû§¶¨Ê±Æ÷×î´óʱ¼ä³¤¶È(µ¥Î»1ms)
+//
+#define UERTIMESTATUS_STOP 0 //Óû§¶¨Ê±Æ÷״̬-Í£Ö¹
+#define UERTIMESTATUS_RUN 1 //Óû§¶¨Ê±Æ÷״̬-ÔËÐÐ
+#define UERTIMESTATUS_RINING 2 //Óû§¶¨Ê±Æ÷״̬-µ½Ê±
+#define UERTIMESTATUS_ERROR 3 //Óû§¶¨Ê±Æ÷״̬-µ½Ê±
+
+//Óû§¶¨Ê±Æ÷ID
+#define TID_GENTIMER 0 //ͨÓö¨Ê±Æ÷,ÓÃÓÚÑÓʱDelay
+#define TID_MAINLOOPTIMER 1 //Ö÷Ñ»·¿ØÖÆ¿¨¶¨Ê±Æ÷
+#define TID_ICCCHARTIMER 2 //×Ö·û´«Ê䳬ʱ¶¨Ê±Æ÷
+#define TID_ICCTIMER 3 //IC¿¨¶¨Ê±Æ÷
+#define TID_PICCTIMER 4 //IC¿¨¶¨Ê±Æ÷
+
+#define TID_LEDATIMER 5 //LED-A¶¨Ê±Æ÷
+#define TID_LEDBTIMER 6 //LED-B¶¨Ê±Æ÷
+#define TID_LEDCTIMER 7 //LED-C¶¨Ê±Æ÷
+#define TID_BEEPTIMER 8 //BEEP¶¨Ê±Æ÷
+
+
+//============>> SAM Card USART¶¨Òå
+#define PSAM1_USART USART2 // PSAM1 //ÕŽΰ£¬Ë®¿ØÆ÷ÓõÄÊÇUART2
+//2014.08.19 ¾£Ç¿ G2101300Ë®¿ØÆ÷ SAMʹÓÃUSART3
+#define PSAM2_USART USART3 // PSAM2
+#define CPU_USART USART2 // ½Ó´¥Ê½CPU¿¨
+
+
+//============>> PSAM1 Card
+
+
+#define Pin_SAM1_CARD_IO GPIO_Pin_9 /* PA9 ¿¨Êý¾Ý IRQ 7816*/
+#define Pin_SAM1_CARD_CLK GPIO_Pin_8 /* PA8 ¿¨Ê±ÖÓ IRQ 7816*/
+#define Pin_SAM1_CARD_READY GPIO_Pin_12 /* PA12 ¿¨¾ÍÐ÷¼ì²âÐźŠIRQ 7816*/
+#define Pin_SAM1_CARD_RESET GPIO_Pin_11 /* PA11 ¿¨¸´Î»¿ØÖÆÐźŠRST7816*/
+#define Pin_SAM1_CARD_VCC GPIO_Pin_0 /* PB0 ¿¨µçÔ´¿ØÖÆÐźŠPowerOn*/
+//#define Pin_SAM1_CARD_35 GPIO_Pin_7 /* PC07 µçÔ´µçѹ¿ØÖÆ¿ØÖÆÐźÅ*/
+//#define Pin_SAM1_CARD_CARD GPIO_Pin_8 /* PC08 ¿¨Æ¬²åÈë¼ì²âÐźÅ*/
+
+#define GPIO_SAM1_CARD_IOCLK GPIOA
+#define GPIO_SAM1_CARD_READY GPIOA
+#define GPIO_SAM1_CARD_RESET GPIOA
+#define GPIO_SAM1_CARD_VCC GPIOB
+
+//============>> PSAM2 Card
+//2009.06.04ÑîÎÄÊٸĶ¯£¬°Ñ¹Ü½Å¶¨Òå¸ÄΪCPU¿¨Ë®¿ØÆ÷ÔÀíͼ¶ÔÓ¦µÄ¹Ü½Å
+#define Pin_SAM2_CARD_IO GPIO_Pin_10 /* PB10 ¿¨Êý¾Ý IRQ 7816*/
+#define Pin_SAM2_CARD_CLK GPIO_Pin_11 /* PB10 ¿¨Ê±ÖÓ IRQ 7816*/
+#define Pin_SAM2_CARD_RESET GPIO_Pin_8 /* PA0 ¿¨¸´Î»¿ØÖÆÐźŠRST7816*/
+//2014.08.19 ¾£Ç¿ G2101300Ë®¿ØÆ÷ ²»ÔÙʹÓÃREADY,VCC,VCC_SELECTÐźÅ
+//#define Pin_SAM2_CARD_READY GPIO_Pin_5 /* PA1 ¿¨¾ÍÐ÷¼ì²âÐźŠIRQ 7816*/
+//#define Pin_SAM2_CARD_VCC GPIO_Pin_6 /* PC3 ¿¨µçÔ´¿ØÖÆÐźŠPowerOn*/
+//#define Pin_SAM2_CARD_VCC_SELECT GPIO_Pin_7 /* PA4 ¿¨µçÔ´¿ØÖÆÐźŠPowerOn*/
+
+#define GPIO_SAM2_CARD_IOCLK GPIOB
+#define GPIO_SAM2_CARD_RESET GPIOC
+//2014.08.19 ¾£Ç¿ G2101300Ë®¿ØÆ÷ ²»ÔÙʹÓÃREADY,VCC,VCC_SELECTÐźÅ
+//#define GPIO_SAM2_CARD_READY GPIOB
+//#define GPIO_SAM2_CARD_VCC_SELECT GPIOB
+//#define GPIO_SAM2_CARD_VCC GPIOB
+
+//============>> CPU Card
+
+#define Pin_CPU_CARD_IO GPIO_Pin_8 /* PD8 ¿¨Êý¾Ý IRQ 7816 */
+#define Pin_CPU_CARD_CLK GPIO_Pin_10 /* PD10 ¿¨Ê±ÖÓ IRQ 7816*/
+#define Pin_CPU_CARD_READY GPIO_Pin_1 /* PB1 ¿¨¾ÍÐ÷¼ì²âÐźŠIRQ 7816*/
+#define Pin_CPU_CARD_RESET GPIO_Pin_9 /* PD9 ¿¨¸´Î»¿ØÖÆÐźŠRST7816*/
+#define Pin_CPU_CARD_VCC GPIO_Pin_0 /* PD0 ¿¨µçÔ´¿ØÖÆÐźŠPowerOn*/
+#define Pin_CPU_CARD_35 GPIO_Pin_1 /* PD1 µçÔ´µçѹ¿ØÖÆ¿ØÖÆÐźÅ*/
+#define Pin_CPU_CARD_CARD GPIO_Pin_2 /* PD2 ¿¨Æ¬²åÈë¼ì²âÐźÅ*/
+
+#define GPIO_CPU_CARD_IOCLK GPIOD
+#define GPIO_CPU_CARD_READY GPIOB
+#define GPIO_CPU_CARD_RESET GPIOD
+#define GPIO_CPU_CARD_VCC GPIOD
+#define GPIO_CPU_CARD_35 GPIOD
+#define GPIO_CPU_CARD_CARD GPIOD
+
+///////////////////////
+
+//´®Ðнӿڶ¨Òå
+
+#define SLOT_PSAM1_ICC 0 // PSAM1
+#define SLOT_PSAM2_ICC 1 // PSAM2
+#define SLOT_CPU_ICC 2 // ½Ó´¥Ê½CPU
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+//¶¨Ê±Æ÷½á¹¹¶¨Òå
+typedef struct _SUserTimer{
+ volatile unsigned int Deadline;
+ volatile unsigned int ReLoadTickNum;
+} SUserTimer,*PSUserTimer;
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+
+ extern volatile unsigned int PSAM_TimeTick; /* Current Time Tick */
+ extern SUserTimer UserTimer[MAXUSERTIMERS]; /* User Program Timer*/
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+ extern void ISO7816_USART_Init( void );
+
+ extern void ResetTickCount(void);
+ extern void CheckResetTickCount(void);
+ extern unsigned int BeginTimer(unsigned int TimerID, unsigned int TimerTickCount);
+ extern unsigned int StopTimer(unsigned int TimerID);
+ extern unsigned int GetTimerStatus(const unsigned int TimerID,const int AutoStop);
+ extern void Delay (int tick);
+
+
+
+
+
+
+
+
+
+#endif
+
diff --git a/icc_apdu_lib/ISOUSARTDriver.c b/icc_apdu_lib/ISOUSARTDriver.c
new file mode 100644
index 0000000..2e7d301
--- /dev/null
+++ b/icc_apdu_lib/ISOUSARTDriver.c
@@ -0,0 +1,987 @@
+/*
+**************************************************************************************************************
+* ISO7816 USART µ× ²ã Ó² ¼þ ½Ó ¿Ú Çý ¶¯
+*
+* _____Ó² ¼þ µ× ²ã (7816) Çý ¶¯_____
+*
+* Ãè Êö£º Ö÷ÒªÍê³É
+* 1) Òì²½¿¨²éѯ·½Ê½¶ÁÈ¡/·¢ËÍÒ»¸ö×Ö·û (Ö÷ÒªÊÇÔÚ±¾²ãµ÷ÓÃ)
+* 2) IC¿¨µÄ¸´Î»£¬Éϵ磬ϵ磬¼ì²âµÈÓ²¼þ²Ù×÷ (ÔÚ±¾²ãÓëT0T1²ã»áµ÷ÓÃ)
+* 3) T0,T1ÐÒé´«ÊäÊý¾Ýµ¥ÔªÓ³Éä (Ö÷ÒªÊÇÔÚT0T1²ãµ÷ÓÃ)
+*
+* Åä Öãº
+*
+* ×¢ Ò⣺ ¸´Î»Ó¦´ðµÈ¹ý³Ì·ûºÏISO7816-2£¬EMV±ê×¼£»
+*
+* ²ã Ãû£º ISOUSARTDriver.C
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V1.0
+*
+* ÈÕ ÆÚ£º 2008-03-25
+*
+* Copyright (c) 2008 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+
+#include "LIB_Includes.H"
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+ unsigned short FITable[] = {372,372,558,744,1116,1488,1860,372,128,512,768,1024,1536,2048}; /* FI */
+ unsigned char DITable[] = {1,1,2,4,8,16,32,1,12,20}; /* DI */
+
+volatile unsigned int bFeFlags[3];
+volatile unsigned char bFeCount[3];
+volatile unsigned char ibSlot;
+
+
+ICCSTRUCT *T01CurrentIccInfo; /* ICCSTRUCTÔÚT0T1.hÖж¨ÒåµÄµ±Ç°¿¨ÐÅϢ״̬½á¹¹Ìå */
+
+volatile unsigned int PSAM_TimeTick; /* Current Time Tick */
+SUserTimer UserTimer[MAXUSERTIMERS]; /* User Program Timer*/
+
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* Èí ¼þ ¶¨ ʱ ²¿ ·Ö
+**************************************************************************************************************
+*/
+
+//*--------------------------------------------------------------------------------------
+//* Function Name : ResetTickCount()
+//* Object : systimer tick = 0
+//* Input Parameters :
+//* Output Parameters :
+//*--------------------------------------------------------------------------------------
+void ResetTickCount(void)
+{
+ int TimerID;
+ PSAM_TimeTick = 0;
+ for(TimerID=0;TimerID<MAXUSERTIMERS;TimerID++)
+ {
+ UserTimer[TimerID].Deadline = 0;
+ }
+}
+void update_sam_ticker(void)
+{
+ PSAM_TimeTick++;
+}
+//*--------------------------------------------------------------------------------------
+//* Function Name : CheckResetTickCount()
+//* Object : systimer tick = 0
+//* Input Parameters :
+//* Output Parameters :
+//*--------------------------------------------------------------------------------------
+void CheckResetTickCount(void)
+{
+ int TimerID;
+ for(TimerID=0;TimerID<MAXUSERTIMERS;TimerID++)
+ {
+ if(UserTimer[TimerID].Deadline != 0)
+ {
+ UserTimer[TimerID].Deadline -= 0x10000000;
+ }
+ }
+ PSAM_TimeTick -= 0x10000000;
+}
+//*--------------------------------------------------------------------------------------
+//* Function Name : BeginTimer()
+//* Object : Begin a user timer with tick
+//* Input Parameters :
+//* Output Parameters :
+//*--------------------------------------------------------------------------------------
+unsigned int BeginTimer(unsigned int TimerID, unsigned int TimerTickCount)
+{
+ if( TimerID >= MAXUSERTIMERS) return 0;
+ if(TimerTickCount == 0)
+ TimerTickCount = UserTimer[TimerID].ReLoadTickNum;
+ if(TimerTickCount > MAXTIMERSTICK)
+ TimerTickCount = MAXTIMERSTICK;
+ UserTimer[TimerID].ReLoadTickNum = TimerTickCount;
+ UserTimer[TimerID].Deadline = PSAM_TimeTick+TimerTickCount;
+ return TimerID;
+}
+
+//*--------------------------------------------------------------------------------------
+//* Function Name : StopTimer()
+//* Object : Stop a user timer with tick
+//* Input Parameters :
+//* Output Parameters :
+//*--------------------------------------------------------------------------------------
+unsigned int StopTimer(unsigned int TimerID)
+{
+ if( TimerID >= MAXUSERTIMERS) return UERTIMESTATUS_ERROR;
+ UserTimer[TimerID].Deadline = 0;
+ return TimerID;
+}
+
+//*--------------------------------------------------------------------------------------
+//* Function Name : GetTimerStatus()
+//* Object : Begin a user timer with tick
+//* Input Parameters :
+//* Output Parameters :
+//*--------------------------------------------------------------------------------------
+unsigned int GetTimerStatus(const unsigned int TimerID,const int AutoStop) //·´ÈÆÎÊÌâ
+{
+ unsigned int retcode = UERTIMESTATUS_ERROR;
+
+ if(TimerID > MAXUSERTIMERS)
+ retcode = UERTIMESTATUS_ERROR;
+
+ else if(UserTimer[TimerID].Deadline == 0)
+ retcode = UERTIMESTATUS_STOP;
+ else if(UserTimer[TimerID].Deadline > PSAM_TimeTick)
+ {
+ if((UserTimer[TimerID].Deadline - PSAM_TimeTick) > PSAM_TimeTick+UserTimer[TimerID].ReLoadTickNum)
+ BeginTimer(TimerID,0);
+ else
+ retcode = UERTIMESTATUS_RUN;
+ }
+ else
+ {
+ if(AutoStop)
+ UserTimer[TimerID].Deadline = 0;
+ else
+ UserTimer[TimerID].Deadline = PSAM_TimeTick+UserTimer[TimerID].ReLoadTickNum;
+
+ retcode = UERTIMESTATUS_RINING;
+ }
+ return retcode;
+}
+
+//*--------------------------------------------------------------------------------------
+//* Function Name : Delay()
+//* Object : Delay with tick
+//* Input Parameters :
+//* Output Parameters :
+//*--------------------------------------------------------------------------------------
+//void Delay (int tick) {
+// BeginTimer(TID_GENTIMER,tick);
+// while(GetTimerStatus(TID_GENTIMER,1) != UERTIMESTATUS_RINING);
+//}
+
+/*
+**************************************************************************************************************
+* Èí ¼þ ¶¨ ʱ ²¿ ·Ö END
+**************************************************************************************************************
+*/
+
+unsigned char ISO_GetChar( int ich ); /* Òì²½¿¨²éѯ·½Ê½¶ÁÈ¡Ò»¸ö×Ö·û Ö»ÔÚ±¾ÎļþÖе÷Óà */
+
+
+//ʹÓö¨Ê±Æ÷TIM2 CH4£¬²úÉúESAMʱÖÓÐźÅ
+static void SAM2_CLK_Init(void)
+{
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStruct;
+ TIM_OCInitTypeDef TIM_OCInitStruct;
+
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
+
+ GPIO_PinRemapConfig(GPIO_PartialRemap2_TIM2, ENABLE);
+
+ TIM_TimeBaseInitStruct.TIM_Period = 8;
+ TIM_TimeBaseInitStruct.TIM_Prescaler = 1;
+ TIM_TimeBaseInitStruct.TIM_ClockDivision = 0;
+ TIM_TimeBaseInitStruct.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseInitStruct);
+
+ TIM_OCInitStruct.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStruct.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStruct.TIM_Pulse = 4;
+ TIM_OCInitStruct.TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OC4Init(TIM2, &TIM_OCInitStruct);
+
+ TIM_Cmd(TIM2, ENABLE);
+}
+
+// PSAM2¿¨×ù³õʼ»¯
+void SAM2_Card_Init( void )
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ USART_InitTypeDef USART_InitStructure;
+ USART_ClockInitTypeDef USART_ClockInitStructure;
+
+ /* Enable clocks 36M*/
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC|RCC_APB2Periph_AFIO, ENABLE);
+
+ //=====>> SAM2_CARD_IO | SAM2_CARD_CLK
+ GPIO_InitStructure.GPIO_Pin = Pin_SAM2_CARD_IO;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+ GPIO_Init( GPIO_SAM2_CARD_IOCLK, &GPIO_InitStructure );
+
+ GPIO_InitStructure.GPIO_Pin = Pin_SAM2_CARD_CLK;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init( GPIO_SAM2_CARD_IOCLK, &GPIO_InitStructure );
+
+ //=====>> SAM2_CARD_RESET
+ GPIO_InitStructure.GPIO_Pin = Pin_SAM2_CARD_RESET;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init( GPIO_SAM2_CARD_RESET, &GPIO_InitStructure);
+
+ GPIO_ResetBits(GPIO_SAM2_CARD_RESET, Pin_SAM2_CARD_RESET);
+
+ USART_SetPrescaler(PSAM2_USART, 0x05);
+
+ /* USART1 Guard Time set to 2 Bit */
+ USART_SetGuardTime(PSAM2_USART, 2);
+
+ USART_StructInit(&USART_InitStructure);
+ USART_InitStructure.USART_BaudRate = 10753;
+ USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+ USART_InitStructure.USART_StopBits = USART_StopBits_1_5;
+ USART_InitStructure.USART_Parity = USART_Parity_Even;
+
+
+ USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
+
+ USART_Init(PSAM2_USART, &USART_InitStructure);
+ USART_ClockInit( PSAM2_USART, &USART_ClockInitStructure );
+
+ /* Enable USART2 */
+ USART_Cmd(PSAM2_USART, ENABLE);
+
+ /* Enable the NACK Transmission */
+ USART_SmartCardNACKCmd(PSAM2_USART, ENABLE);
+
+ /* Enable the Smart Card Interface */
+ USART_SmartCardCmd(PSAM2_USART, ENABLE);
+}
+
+/*
+*************************************************************************************************************
+ ³õʼ»¯
+*************************************************************************************************************
+*/
+void ISO7816_USART_Init( void )
+{
+ SAM2_Card_Init();
+ SAM2_CLK_Init();
+
+ /* Configure the System Tick */
+ ResetTickCount();
+}
+
+/*******************************************************************************
+* Function Name : ParityErrorHandler
+* Description : Resends the byte that failed to be received (by the Smartcard)
+* correctly.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ParityErrorHandler(USART_TypeDef * pUSART)
+{
+ bFeFlags[ibSlot] = 1;
+}
+
+//*----------------------------------------------------------------------------
+//* Function Name : isICCardReady
+//* Object : ¼ì²â¿¨¼°µçԴ״̬
+//* Input Parameters : none
+//* Output Parameters : ·µ»ØÖµ£º1-Õý³£,0=¾¯±¨×´Ì¬
+//* Functions called : ¿¨Æ¬PowerOnÒÔºóµ÷ÓÃ
+//*----------------------------------------------------------------------------
+char isICCardReady(int ich)
+{
+ return 1;
+}
+
+
+//*----------------------------------------------------------------------------
+//* Function Name : ICC_ResetCard
+//* Object : ¿¨Èȸ´Î»
+//* Input Parameters : ich = CHNL_ICC/PSAM1_POWER/PSAM2_POWER_ON
+//* Output Parameters : ·µ»ØÖµ£ºICErrorCode
+//* Functions called : none
+//*----------------------------------------------------------------------------
+unsigned short ICC_ResetCard(int ich)
+{
+ u32 y;
+ u32 pps = 0;
+ u8 temp_buffer[12];
+ u8 c_tmp;
+ u8 ta2;
+ USART_InitTypeDef USART_InitStructure;
+ USART_ClockInitTypeDef USART_ClockInitStructure;
+
+ //RESETÖõ͵çƽ£¬½øÈ븴λ״̬
+ GPIO_ResetBits(GPIO_SAM2_CARD_RESET, Pin_SAM2_CARD_RESET);
+ /* Enable USART1 */
+ USART_Cmd(USART3, DISABLE);
+
+ /* Enable the Smart Card Interface */
+ USART_SmartCardCmd(USART3, DISABLE);
+
+ USART_SetPrescaler(USART3, 0x05);
+
+ /* USART1 Guard Time set to 2 Bit */
+ USART_SetGuardTime(USART3, 2);
+
+ USART_StructInit(&USART_InitStructure);
+ USART_InitStructure.USART_BaudRate = 10753 * T01CurrentIccInfo->EXDI;
+ USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+ USART_InitStructure.USART_StopBits = USART_StopBits_1_5;
+ USART_InitStructure.USART_Parity = USART_Parity_Even;
+
+ USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
+
+ USART_Init(USART3, &USART_InitStructure);
+ USART_ClockInit( USART3, &USART_ClockInitStructure );
+
+ /* Enable USART1 */
+ USART_Cmd(USART3, ENABLE);
+
+ /* Enable the NACK Transmission */
+ USART_SmartCardNACKCmd(USART3, ENABLE);
+
+ /* Enable the Smart Card Interface */
+ USART_SmartCardCmd(USART3, ENABLE);
+
+ //Æô¶¯¸´Î»ÐźÅÑÓʱ¶¨Ê±
+ BeginTimer(TID_ICCTIMER, 12);
+ while ( GetTimerStatus(TID_ICCTIMER,1) != UERTIMESTATUS_RINING)
+ {
+ //µÈ´ý40000-45000¸ö¿¨Ê±ÖÓ//¸´Î»ÐźÅʱ¼ä=12ms ¼ÆËãÒÀ¾Ý£º(MCK/13 = 3.68640MHz)£¬12ms Ï൱ÓÚ44236.8¸ö¿¨Ê±ÖÓ£¬Êµ¼Ê¶¨Ê±Ê±¼äµÄ×î´óÖµ
+ if(isICCardReady(ich)==0)
+ {
+ StopTimer(TID_ICCTIMER);
+ break;
+ }
+ }
+
+ //RESETÖøߵçƽ£¬½øÈëATR¶Áȡ״̬
+ GPIO_SetBits(GPIO_SAM2_CARD_RESET, Pin_SAM2_CARD_RESET);
+
+ T01CurrentIccInfo->TS = 0x3b; //Ê×ÏÈĬÈÏÕýÏòÔ¼¶¨
+
+ //¶ÁÈ¡¿¨Ó¦´ðÐòÁÐATR
+ // Read ATR TS
+ T01CurrentIccInfo->TS = ISO_GetChar(ich); //ÕâÀïÐèÒªÒ»¸ö42000CLOCKµÄ³¬Ê±¶¨Ê±
+ if(T01CurrentIccInfo->TS == 0xff)
+ {
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ {
+ if(T01CurrentIccInfo->ICErrorCode==5)
+ {
+ T01CurrentIccInfo->ICErrorCode=0x003A; //¶ÁÈ¡TS³¬Ê±,PSAM¿¨×ùΪ¿Õ£¡
+ }
+ if(T01CurrentIccInfo->ICErrorCode==4)
+ {
+ T01CurrentIccInfo->ICErrorCode=3; //¶Ì·±£»¤,ÊÓͬ½ðÊô½éÖÊ
+ }
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ }
+ if((T01CurrentIccInfo->TS!=0x3b) && (T01CurrentIccInfo->TS!=0x3f))
+ {
+ T01CurrentIccInfo->ICErrorCode=6;
+ return T01CurrentIccInfo->ICErrorCode; //TS²»ÊǺϷ¨µÄIC¿¨£¬¾Ü¾ø
+ }
+ // Read ATR T0
+ T01CurrentIccInfo->T0 = ISO_GetChar(ich);
+ if(T01CurrentIccInfo->T0 == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ y = T01CurrentIccInfo->T0 & 0xF0;
+
+ // Read ATR T1
+ if (y) {
+ if (y & 0x10) // TA[i] //ATR-TA1 TA1´«ËÍFIºÍDIµÄÖµ(T=0ʱΪ0x00»ò0x11,T=1ʱ£¬DÖ§³Ö1¡¢2¡¢4¼°Î´À´ÆäËûµÄÈ¡Öµ)
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ T01CurrentIccInfo->DI = c_tmp & 0x0f;
+ T01CurrentIccInfo->FI = (c_tmp>>4) & 0x0f;
+ pps = 1;
+ if((T01CurrentIccInfo->FI==7)||(T01CurrentIccInfo->FI==8)||(T01CurrentIccInfo->FI>=0x0E))
+ {
+ T01CurrentIccInfo->FI = 1;
+ pps = 0;
+ }
+ if((T01CurrentIccInfo->DI==0)||(T01CurrentIccInfo->DI==7)||(T01CurrentIccInfo->FI>=0x0A))
+ {
+ T01CurrentIccInfo->FI = 1;
+ pps = 0;
+ }
+ if((T01CurrentIccInfo->DI > 1 || T01CurrentIccInfo->FI > 1) && ((T01CurrentIccInfo->T0 & 0xf0)==0x60))
+ {
+ T01CurrentIccInfo->ICErrorCode=6;
+ return T01CurrentIccInfo->ICErrorCode; //TS²»ÊǺϷ¨µÄIC¿¨£¬¾Ü¾ø
+ }
+ }
+ else
+ {
+ T01CurrentIccInfo->DI = 1;
+ T01CurrentIccInfo->FI = 1;
+ pps = 0;
+ }
+ if (y & 0x20) // TB[i] //ATR-TB1 TB1´«ËÍPI1ºÍIIÖµ(±à³ÌµçѹºÍµçÁ÷)
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp != 0x0) //Ö»½ÓÊÜTB1=0µÄÓ¦´ð,±à³ÌµçѹºÍµçÁ÷
+ {
+ T01CurrentIccInfo->ICErrorCode=6;
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ }
+ if (y & 0x40) // TC[i] //ATR-TC1 ´«ËÍNÖµ,±íʾÔö¼Óµ½×îС³ÖÐøʱ¼äµÄ¶îÍâ±£»¤Ê±¼ä(etuÊý)
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+
+ T01CurrentIccInfo->N = c_tmp;
+ }
+ else
+ {
+ T01CurrentIccInfo->N = 2;
+ }
+
+ if (y & 0x80) // TD[i] //ATR-TD1 ÊÇ·ñ»¹Òª·¢Ë͸ü¶àµÄ½Ó¿Ú×Ö½ÚÒÔ¼°ºóÐø´«ÊäËùʹÓõÄÐÒéÀàÐÍ,(½öÖ§³Ö0ºÍ1ÐÒé0x81£¬¾Ü¾øÆäËûÖµ)
+ {
+ T01CurrentIccInfo->TD1 = ISO_GetChar(ich);
+ if(T01CurrentIccInfo->TD1 == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ y = T01CurrentIccInfo->TD1 & 0xF0;
+ T01CurrentIccInfo->T = T01CurrentIccInfo->TD1 & 0x0F; //T=?
+ }
+ else
+ {
+ T01CurrentIccInfo->TD1 = 0;
+ T01CurrentIccInfo->T = 0;
+ y = 0;
+ }
+ }
+
+ //T01CurrentIccInfo->SPMOD = 0; // Ìض¨Ä£Ê½»¹Êǽ»»¥Ä£Ê½
+
+ // Read ATR T2
+ ta2 = 0;
+ if (y) {
+ if (y & 0x10) // TA[i] //ATR-TA2 Ìض¨Ä£Ê½»¹ÊÇÒÔ½»»¥Ä£Ê½
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ {
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ T01CurrentIccInfo->SPMOD = c_tmp; //Ìض¨Ä£Ê½ »¹ÊÇ ½»»¥Ä£Ê½ b8=0ÓиıäÄÜÁ¦£¬=1Î޸ıäÄÜÁ¦£»b5=1²»ÓɽӿÚ×Ö½Ú¶¨Ò壬=0½Ó¿Ú×Ö½Ú¶¨Ò壻b4-b1 ÐÒéT
+ ta2 = 1;
+ }
+ if (y & 0x20) // TB[i] //ATR-TB2 TB2´«ËÍPI2£¬PI2ÓÃÓÚÈ·¶¨IC¿¨ËùÐèµÄ±à³ÌµçѹPµÄÖµ
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp != 0x0) //Ö»½ÓÊÜTB1=0µÄÓ¦´ð,±à³ÌµçѹºÍµçÁ÷
+ {
+ T01CurrentIccInfo->ICErrorCode=6;
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ }
+ if (y & 0x40) // TC[i] //ATR-TC2 TC2 רÓÃÓÚT=0 ÐÒ飬²¢´«Ë͹¤×÷µÈ´ýʱ¼äÕûÊý(WI),¹¤×÷µÈ´ýʱ¼äΪ£º960¡ÁD¡ÁWI
+ {
+ c_tmp = ISO_GetChar(ich);
+ T01CurrentIccInfo->WI = c_tmp;
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ else
+ {
+ T01CurrentIccInfo->WI = 10;
+ }
+ if (y & 0x80) // TD[i] //ATR-TD2 TD2±íʾÊÇ·ñ»¹Òª·¢Ë͸ü¶àµÄ½Ó¿Ú×Ö½ÚÒÔ¼°ºóÐø´«ÊäËùʹÓõÄÐÒéÀàÐÍ(0x31)
+ {
+ T01CurrentIccInfo->TD2 = ISO_GetChar(ich);
+ if(T01CurrentIccInfo->TD2 == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ y = T01CurrentIccInfo->TD2 & 0xF0;
+ }
+ else
+ {
+ T01CurrentIccInfo->TD2 = 0;
+ y = 0;
+ }
+ }
+ else
+ {
+ T01CurrentIccInfo->WI = 10;
+ }
+ // Read ATR T3
+ if (y) {
+ if (y & 0x10) // TA[i] //ATR-TA3 »ØËÍIC¿¨µÄÐÅÏ¢Óò´óСÕûÊý(IFSI)
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ T01CurrentIccInfo->IFSI = c_tmp;
+ }
+ else
+ {
+ T01CurrentIccInfo->IFSI = 32;
+ }
+ if (y & 0x20) // TB[i] //ATR-TB3 ÓÃÀ´¼ÆËãCWTºÍBWTµÄCWIºÍBWIÖµ
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ T01CurrentIccInfo->CWI = c_tmp & 0x07;
+ T01CurrentIccInfo->BWI = (c_tmp & 0x70)>>4;
+ }
+ else
+ {
+ T01CurrentIccInfo->BWI = 0;
+ T01CurrentIccInfo->CWI = 0;
+ }
+ if (y & 0x40) // TC[i] //ATR-TC3 ËùÓõĿé´íÎó¼ì²â´úÂëµÄÀàÐÍ
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ T01CurrentIccInfo->Crc = c_tmp & 0x01;
+ }
+ else
+ {
+ T01CurrentIccInfo->Crc = 0; //CRC
+ }
+ if (y & 0x80) // TD[i] //ATR-TD3 TD3ºóÐøTA
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ if((c_tmp & 0x1f) == 0x1f)
+ c_tmp = ISO_GetChar(ich);
+ }
+ }
+ for(y = 0;y < (T01CurrentIccInfo->T0 & 0x0f) && y < 16; y++)
+ {
+ T01CurrentIccInfo->MRcvBuffer[y] = ISO_GetChar(ich);
+ if(T01CurrentIccInfo->MRcvBuffer[y] == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ T01CurrentIccInfo->MRcvBuffer[y] = 0;
+
+ // Read ATR TCK
+ if (T01CurrentIccInfo->T == 1) {
+ T01CurrentIccInfo->ETCK = ISO_GetChar(ich);
+ if(T01CurrentIccInfo->ETCK == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ else
+ {
+ T01CurrentIccInfo->ETCK = 0;
+ }
+
+ //°´ÕÕATRÖ¸¶¨²ÎÊýÖØгõʼ»¯½Ó¿Ú
+ if(T01CurrentIccInfo->T == 0 || T01CurrentIccInfo->T == 1)
+ {
+ USART_SetGuardTime(USART3, T01CurrentIccInfo->N);
+ USART_StructInit(&USART_InitStructure);
+
+ if(ta2 != 0)
+ {
+ if((T01CurrentIccInfo->SPMOD&0x10) == 0)
+ {
+ USART_InitStructure.USART_BaudRate = 4000000ul/(FITable[T01CurrentIccInfo->FI]/DITable[T01CurrentIccInfo->DI]);
+ }
+ else //ÐÉÌģʽµÄFn/Dn»ñµÃ,ÔÝʱ±£Áôȱʡֵ
+ {
+ USART_InitStructure.USART_BaudRate = 10753* T01CurrentIccInfo->EXDI;
+ }
+ }
+ else
+ {
+ pps = 0;
+ if(pps)
+ {
+ char ISO_PutStr(unsigned char *pch, int len, int ich);
+
+ BeginTimer(TID_ICCTIMER, 10);
+ temp_buffer[0] = 0xFF;
+ temp_buffer[1] = 0x10;
+ temp_buffer[2] = 0x95;//(T01CurrentIccInfo->FI<<4)|(T01CurrentIccInfo->DI);
+ temp_buffer[3] = (temp_buffer[0]^temp_buffer[1])^temp_buffer[2];
+ if(ISO_PutStr(temp_buffer, 4, ich) == 0)
+ {
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ temp_buffer[4] = c_tmp;
+
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ temp_buffer[5] = c_tmp;
+
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ temp_buffer[6] = c_tmp;
+
+ c_tmp = ISO_GetChar(ich);
+ if(c_tmp == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ temp_buffer[7] = c_tmp;
+ if(memcmp(temp_buffer, temp_buffer+4, 4) == 0)
+ {
+ USART_InitStructure.USART_BaudRate = 4000000ul/(FITable[T01CurrentIccInfo->FI]/DITable[T01CurrentIccInfo->DI]);
+ }
+ else //ÐÉÌģʽµÄFn/Dn»ñµÃ,ÔÝʱ±£Áôȱʡֵ
+ {
+ USART_InitStructure.USART_BaudRate = 10753* T01CurrentIccInfo->EXDI;
+ }
+ }
+ }
+ else
+ {
+ USART_InitStructure.USART_BaudRate = 10753* T01CurrentIccInfo->EXDI;
+ }
+ }
+
+ USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+ USART_InitStructure.USART_StopBits = USART_StopBits_1_5;
+ USART_InitStructure.USART_Parity = USART_Parity_Even;
+
+ USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
+
+ USART_Init(USART3, &USART_InitStructure);
+ USART_ClockInit( USART3, &USART_ClockInitStructure );
+
+ /* Enable USART1 */
+ USART_Cmd(USART3, ENABLE);
+
+ /* Enable the NACK Transmission */
+ USART_SmartCardNACKCmd(USART3, ENABLE);
+
+ /* Enable the Smart Card Interface */
+ USART_SmartCardCmd(USART3, ENABLE);
+ }
+ else
+ {
+ T01CurrentIccInfo->ICErrorCode=6;
+ return T01CurrentIccInfo->ICErrorCode; //TS²»ÊǺϷ¨µÄIC¿¨£¬¾Ü¾ø
+ }
+ T01CurrentIccInfo->ICErrorCode = 0;
+ return T01CurrentIccInfo->ICErrorCode;
+}
+
+//*----------------------------------------------------------------------------
+//* Function Name : ICC_PowerOnCard
+//* Object : ¿¨Éϵç,¸´Î»
+//* Input Parameters : ich =
+//* Output Parameters : ·µ»ØÖµ£ºICErrorCode
+//* Functions called : none
+//*----------------------------------------------------------------------------
+unsigned short ICC_PowerOnCard(int ich)
+{
+ int rcode;
+
+ //RESETÖõ͵çƽ£¬½øÈ븴λ״̬
+ GPIO_ResetBits(GPIO_SAM2_CARD_RESET, Pin_SAM2_CARD_RESET);
+
+ //µÈ´ý¿¨µçÔ´¾ÍÐ÷
+ BeginTimer(TID_ICCTIMER, 20); //µÈ´ýµçÔ´¾ÍÐ÷ÐźÅʱ¼ä=10ms Õý³£Çé¿öÏÂLTC1756 5us
+ while (isICCardReady(ich) == 0)
+ { //δ¾ÍÐ÷״̬
+ if(GetTimerStatus(TID_ICCTIMER,1) == UERTIMESTATUS_RINING)
+ {
+ break;
+ }
+ }
+ USART_SmartCardCmd(USART3, ENABLE);
+
+ rcode = ICC_ResetCard(ich);
+ if(rcode)
+ {
+ T01CurrentIccInfo->EXDI = 4;
+ rcode = ICC_ResetCard(ich); //Èȸ´Î»Ê§°Ü,ÔÙÀ´Ò»´Î
+ }
+ return rcode;
+}
+
+//*----------------------------------------------------------------------------
+//* Function Name : ICC_PowerOffCard
+//* Object : ¿¨Ïµç
+//* Input Parameters : ich = CHNL_ICC/PSAM1_POWER/PSAM2_POWER_ON
+//* Output Parameters : none
+//* Functions called : none
+//*----------------------------------------------------------------------------
+void ICC_PowerOffCard(int ich)
+{
+ GPIO_ResetBits(GPIO_SAM2_CARD_RESET, Pin_SAM2_CARD_RESET);
+ BeginTimer(TID_ICCTIMER, 2);
+ while (GetTimerStatus(TID_ICCTIMER,1) != UERTIMESTATUS_RINING){};
+ //ʱÖÓÍ£Ö¹
+ USART_SmartCardCmd(PSAM2_USART, DISABLE);
+ return ;
+}
+
+//*----------------------------------------------------------------------------
+//* Function Name : ISO_GetChar
+//* Object : Òì²½¿¨²éѯ·½Ê½¶ÁÈ¡Ò»¸ö×Ö·û
+//* Input Parameters : ich=IC¿¨½Ó¿Ú
+//* Output Parameters : ·µ»Ø0xffʱ,ÐèÒª¼ì²âICErrorCode£¬ÆäËüֵΪ½ÓÊÕµ½µÄ×Ö·û
+//* Functions called : none
+//*----------------------------------------------------------------------------
+unsigned char ISO_GetChar(int ich)
+{
+ char rcode;
+
+ BeginTimer(TID_ICCCHARTIMER,300); //2011.3.4ºÅÕŽΰµ÷Õû£¬²»µ÷ÕûMAC2УÑ鳬ʱ
+ while(USART_GetFlagStatus(USART3, USART_FLAG_RXNE) == RESET) //ÊÕµ½×Ö·û
+ {
+ if(USART_GetFlagStatus(USART3, USART_FLAG_PE) != RESET) //ÆæżУÑé
+ {
+ USART_ReceiveData(USART3); //¸´Î»×´Ì¬¼Ä´æÆ÷
+ T01CurrentIccInfo->ICErrorCode = 0x0007;
+ return 0xff;
+ }
+ //test
+ if(GetTimerStatus(TID_ICCCHARTIMER,1) == UERTIMESTATUS_RINING) //½ÓÊÕ»ú³¬Ê±
+ {
+ T01CurrentIccInfo->ICErrorCode = 0x0005;
+ return 0xff;
+ }
+ if(isICCardReady(ich)==0)
+ {
+ T01CurrentIccInfo->ICErrorCode = 0x0004;
+ return 0xff;
+ }
+ }
+ T01CurrentIccInfo->ICErrorCode = 0;
+ rcode = USART_ReceiveData(USART3); //½ÓÊÕÒ»¸ö×Ö·û
+ if(T01CurrentIccInfo->TS == 0x3f)
+ rcode = ~rcode;
+ return rcode;}
+
+//*----------------------------------------------------------------------------
+//* Function Name : ISO_GetProcByte
+//* Object : µÃµ½¹ý³Ì×Ö½Ú£¬²¢×÷ÅжϽøÒ»²½½ÓÊÕSW2
+//* Input Parameters : ch=INS,ich=IC¿¨½Ó¿Ú
+//* Output Parameters : ·µ»Ø0=¹ý³Ì×Ö½ÚÓëINSÏàͬ,1-255=´íÎó(T01CurrentIccInfo->ICErrorCode´íÎó´úÂë),6xxx/9xxx=SW1SW2
+//* Functions called : none
+//*----------------------------------------------------------------------------
+unsigned short ISO_GetProcByte(unsigned char ch, int ich)
+{
+ unsigned char cch1,cch2;
+
+// USART3->US_CR = AT91C_US_RETTO; //ÖØÔؽÓÊÕÆ÷³¬Ê±
+ rvccch1:
+ cch1 = ISO_GetChar(ich);
+ if(cch1 == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return (unsigned short)T01CurrentIccInfo->ICErrorCode;
+ if((cch1 == ch || cch1 == ~ch || cch1 == 0x60) && ch != 0x00)
+ {
+ if(cch1 == 0x60)
+ goto rvccch1;
+ return (unsigned short) 0;
+ }
+ else
+ {
+ cch2 = ISO_GetChar(ich);
+ if(cch2 == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return (unsigned short)T01CurrentIccInfo->ICErrorCode;
+ T01CurrentIccInfo->ICErrorCode = (cch1<<8 | cch2);
+ return (unsigned short)T01CurrentIccInfo->ICErrorCode; //SW1.SW2
+ }
+}
+
+//*----------------------------------------------------------------------------
+//* Function Name : ISO_PutStr
+//* Object : Òì²½¿¨²éѯ·½Ê½·¢³öÒ»¸ö×Ö·û´®
+//* Input Parameters : ich=IC¿¨½Ó¿Ú
+//* Output Parameters : ·µ»Ø·Ç0ʱ,ÐèÒª¼ì²âICErrorCode
+//* Functions called : none
+//*----------------------------------------------------------------------------
+char ISO_PutStr(unsigned char *pch, int len, int ich)
+{
+ unsigned char i,rcode;
+ char ch;
+
+ //Æô¶¯ÐźÅÑÓʱ¶¨Ê±//ÎÕÆ濨ÐèÒªÑÓʱ ±¨ÎÄÖ®¼ä
+ BeginTimer(TID_ICCTIMER, 2); //ÐźÅʱ¼ä=1ms
+ while ( GetTimerStatus(TID_ICCTIMER,1) != UERTIMESTATUS_RINING);
+
+ rcode = 0;
+
+ for(i=0;i<len;i++)
+ {
+ ch = pch[i];
+ if(T01CurrentIccInfo->TS == 0x3f)
+ ch = ~ch; //·´ÏòÔ¼¶¨
+
+ ibSlot = ich;
+ bFeFlags[ibSlot] = 0;
+ bFeCount[ibSlot] = 0;
+ USART_SendData(USART3,ch); //·¢ËÍÒ»¸ö×Ö·û
+
+ while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET) //»º³åÆ÷¿Õ£¿
+ {
+ if(bFeFlags[ibSlot])
+ {
+ if(bFeCount[ibSlot] >=3 ) //´«ÊäÖØ·¢£¬´íÎó´ïµ½×î´óÊý
+ {
+ USART_ClearFlag(USART3,USART_FLAG_PE|USART_FLAG_FE|USART_FLAG_NE|USART_FLAG_ORE|USART_FLAG_RXNE|USART_FLAG_TXE); //¸´Î»×´Ì¬¼Ä´æÆ÷
+ T01CurrentIccInfo->ICErrorCode = 0x0007;
+ rcode = T01CurrentIccInfo->ICErrorCode;
+ break;
+ }
+ ibSlot = ich;
+ bFeFlags[ibSlot] = 0;
+ bFeCount[ibSlot]++;
+ USART_SendData(USART3,ch); //ÖØ·¢ËÍÒ»¸ö×Ö·û
+ }
+ if(isICCardReady(ich)==0)
+ {
+ T01CurrentIccInfo->ICErrorCode = 4;
+ rcode = T01CurrentIccInfo->ICErrorCode;
+ break;
+ }
+ }
+ if(rcode != 0)
+ break;
+ }
+ (void)USART_ReceiveData(USART3);
+ return rcode;
+ }
+
+
+//*----------------------------------------------------------------------------
+//* Function Name : ICC_TPDU
+//* Object : ÐÒé´«ÊäÊý¾Ýµ¥ÔªÓ³Éä
+//* Input Parameters : scmd=5×Ö½ÚÃüÁî×Ö·û´®Ö¸Õ루CLA¡¢INS¡¢P1¡¢P2ºÍP3£©,
+//* sdata=·¢ËÍ/½ÓÊÕÊý¾Ý»º³åÈ¥Ö¸Õ룬ctl=ÐÒé¿ØÖÆ×Ö·û£¨¼ûÏÂÊö£©, *rec_bytelen½ÓÊÜÊý¾ÝµÄ³¤¶È£¬ich=IC¿¨½Ó¿Ú
+//* ctl=0ÎÞÊý¾ÝÖ¡scmd[4]=0, ctl=1·¢ËÍÊý¾ÝÖ¡/Ö¡³¤¶ÈÓÉscmd[4]È·¶¨, ctl=2½ÓÊÕÊý¾ÝÖ¡
+//* Output Parameters : ·µ»ØICErrorCode=SW1 SW2»òÕß0-255µÄÎïÀí²ã´íÎó´úÂë
+//* Functions called : none
+//*----------------------------------------------------------------------------
+unsigned short T0_TPDU(unsigned char * scmd, unsigned char * sdata, int ctl, unsigned char *rec_bytelen, int ich)
+{
+ unsigned char cch1;
+ unsigned short rcode,i,ilen;
+
+ USART_ClearFlag(USART3,USART_FLAG_PE|USART_FLAG_FE|USART_FLAG_NE|USART_FLAG_ORE|USART_FLAG_RXNE|USART_FLAG_TXE); //¸´Î»×´Ì¬¼Ä´æÆ÷
+
+ if(ISO_PutStr(scmd, 5, ich) != 0x0) //·¢ËÍÃüÁîÍ·
+ {
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+
+ *rec_bytelen = 0;
+
+ rcode = ISO_GetProcByte(scmd[1], ich);
+ if(rcode == 0)
+ { //·µ»ØÖµÓëINSÏàͬ»òΪ0x60
+ if(ctl == 1)
+ { //¸úËæÃüÁîÊý¾ÝÐèÒª·¢ËÍ
+ if(ISO_PutStr(sdata, scmd[4], ich) != 0x0) //·¢ËÍÊý¾Ý
+ {
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ }
+ else
+ {
+ ilen = scmd[4];
+ for(i=0;i<ilen;i++)
+ {
+ cch1 = ISO_GetChar(ich);
+ if(cch1 == 0xff)
+ if(T01CurrentIccInfo->ICErrorCode!=0)
+ return T01CurrentIccInfo->ICErrorCode;
+ sdata[i]=cch1;
+ }
+ *rec_bytelen = ilen;
+ }
+ rcode = ISO_GetProcByte(0, ich);
+ }
+ T01CurrentIccInfo->ICErrorCode = rcode;
+ return rcode;
+}
+
+//*----------------------------------------------------------------------------
+//* Function Name : T1_TPDU
+//* Object : T=1 ÐÒé´«ÊäÊý¾Ýµ¥ÔªÓ³Éä
+//* Input Parameters :
+//* Output Parameters : ·µ»ØICErrorCode=SW1 SW2»òÕß0-255µÄÎïÀí²ã´íÎó´úÂë
+//* Functions called : none
+//*----------------------------------------------------------------------------
+unsigned short T1_TPDU(unsigned char *send_data,unsigned char send_bytelen,unsigned char *rec_data,unsigned char *rec_bytelen, int ich)
+{
+ unsigned char cch1;
+ unsigned char i,rLen;
+
+ USART_ClearFlag(USART3,USART_FLAG_PE|USART_FLAG_FE|USART_FLAG_NE|USART_FLAG_ORE|USART_FLAG_RXNE|USART_FLAG_TXE); //¸´Î»×´Ì¬¼Ä´æÆ÷
+
+ if(ISO_PutStr(send_data, send_bytelen, ich) != 0x0) //·¢ËÍÊý¾ÝÖ¡
+ {
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+
+ rLen = 3;
+ for(i=0;i<rLen;i++) //½ÓÊÕNAD¡¢PCB¡¢LEN
+ {
+ cch1 = ISO_GetChar(ich);
+ if(cch1 == 0xff)
+ {
+ if(T01CurrentIccInfo->ICErrorCode==5)
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ *(rec_data+i)=cch1;
+ }
+
+ rLen += *(rec_data+2); //Êý¾Ý³¤¶È
+ if(T01CurrentIccInfo->Crc == 1)
+ rLen += 2;
+ else
+ rLen += 1;
+
+ for(i=3;i<rLen;i++) //½ÓÊÕÊý¾ÝÖ¡ºÍLRC
+ {
+ cch1 = ISO_GetChar(ich);
+ if(cch1 == 0xff)
+ {
+ if(T01CurrentIccInfo->ICErrorCode==5)
+ return T01CurrentIccInfo->ICErrorCode;
+ }
+ *(rec_data+i)=cch1;
+ }
+ *rec_bytelen = rLen;
+ T01CurrentIccInfo->ICErrorCode = 0;
+ return T01CurrentIccInfo->ICErrorCode;
+}
+
diff --git a/icc_apdu_lib/LIB_Includes.H b/icc_apdu_lib/LIB_Includes.H
new file mode 100644
index 0000000..1b37e44
--- /dev/null
+++ b/icc_apdu_lib/LIB_Includes.H
@@ -0,0 +1,54 @@
+
+
+#ifndef __LIB_Includes_H__
+#define __LIB_Includes_H__
+
+
+
+ #include <string.h>
+ #include "CPU.H"
+ #include "stm32f10x.h"
+
+ #include "ICC_APDU_LIB.H"
+
+ #include "CardErrorCode.H"
+ #include "Mifare_One_HW_LIB.H"
+
+
+//2009.06.04ÑîÎÄÊٸĶ¯£¬°Ñ¹Ü½Å¶¨Òå¸ÄΪCPU¿¨Ë®¿ØÆ÷ÔÀíͼ¶ÔÓ¦µÄ¹Ü½Å
+#define Pin_Mifare_SCK GPIO_Pin_13
+#define Pin_Mifare_MISO GPIO_Pin_14
+#define Pin_Mifare_MOSI GPIO_Pin_15
+
+#define Pin_Mifare_RST GPIO_Pin_6
+#define Pin_Mifare_NSS GPIO_Pin_12
+
+#define GPIO_MAFIRE_SPI GPIOB
+#define GPIO_MAFIRE_RST GPIOC
+#define GPIO_MAFIRE_NSS GPIOB
+
+
+#define Mifare_SPIx SPI2
+
+
+
+//DataConvert================================================================================
+extern unsigned char * LEIntTo4Str(int i,unsigned char * str);
+extern unsigned char * LEIntTo3Str(int i,unsigned char * str);
+extern unsigned char * LEIntTo2Str(int i,unsigned char * str);
+extern unsigned int BE4StrToInt(unsigned char *str);
+extern unsigned int BE3StrToInt(unsigned char *str);
+extern unsigned short BE2StrToInt(unsigned char *str);
+extern int Compare_two_data(unsigned char *xp1,unsigned char *xp2,unsigned char n);
+extern unsigned char isLeap(unsigned short year);
+extern unsigned char isValidDate(unsigned char * psClock);
+extern unsigned char XOR(unsigned char *buffer,unsigned char length);
+extern unsigned short get_crc_16 (unsigned short start, char *p, unsigned short n);
+extern void CalCrc16(unsigned char* input, unsigned char* Crc16, unsigned int len);
+
+
+
+
+
+#endif
+
diff --git a/icc_apdu_lib/MfErrNo.h b/icc_apdu_lib/MfErrNo.h
new file mode 100644
index 0000000..1d3eeeb
--- /dev/null
+++ b/icc_apdu_lib/MfErrNo.h
@@ -0,0 +1,114 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c), Philips Semiconductors Gratkorn
+//
+// (C)PHILIPS Electronics N.V. 2000
+// All rights are reserved.
+// Philips reserves the right to make changes without notice at any time.
+// Philips makes no warranty, expressed, implied or statutory, including but
+// not limited to any implied warranty of merchantibility or fitness for any
+//particular purpose, or that the use will not infringe any third party patent,
+// copyright or trademark. Philips must not be liable for any loss or damage
+// arising from its use.
+///////////////////////////////////////////////////////////////////////////////
+#ifndef MFERRNO_H
+#define MFERRNO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// Reader Error Codes Base Address Start: 0x2000
+// Base Address End: 0x2999
+//////////////////////////////////////////////////////////////////////////////
+#define READER_ERR_BASE_START (0x2000)
+#define MI_OK (0)
+#define MI_CHK_OK (0)
+#define MI_CRC_ZERO (0)
+// ICODE1 Error Codes
+#define I1_OK (0)
+#define I1_NO_ERR (0)
+
+#define MI_NOTAGERR (READER_ERR_BASE_START + 0x1)
+#define MI_CHK_FAILED (READER_ERR_BASE_START + 0x1)
+#define MI_CRCERR (READER_ERR_BASE_START + 0x2)
+#define MI_CHK_COMPERR (READER_ERR_BASE_START + 0x2)
+#define MI_EMPTY (READER_ERR_BASE_START + 0x3)
+#define MI_AUTHERR (READER_ERR_BASE_START + 0x4)
+#define MI_PARITYERR (READER_ERR_BASE_START + 0x5)
+#define MI_CODEERR (READER_ERR_BASE_START + 0x6)
+
+#define MI_SERNRERR (READER_ERR_BASE_START + 0x8)
+#define MI_KEYERR (READER_ERR_BASE_START + 0x9)
+#define MI_NOTAUTHERR (READER_ERR_BASE_START + 0x10)
+#define MI_BITCOUNTERR (READER_ERR_BASE_START + 0x11)
+#define MI_BYTECOUNTERR (READER_ERR_BASE_START + 0x12)
+#define MI_IDLE (READER_ERR_BASE_START + 0x13)
+#define MI_TRANSERR (READER_ERR_BASE_START + 0x14)
+#define MI_WRITEERR (READER_ERR_BASE_START + 0x15)
+#define MI_INCRERR (READER_ERR_BASE_START + 0x16)
+#define MI_DECRERR (READER_ERR_BASE_START + 0x17)
+#define MI_READERR (READER_ERR_BASE_START + 0x18)
+#define MI_OVFLERR (READER_ERR_BASE_START + 0x19)
+#define MI_POLLING (READER_ERR_BASE_START + 0x20)
+#define MI_FRAMINGERR (READER_ERR_BASE_START + 0x21)
+#define MI_ACCESSERR (READER_ERR_BASE_START + 0x22)
+#define MI_UNKNOWN_COMMAND (READER_ERR_BASE_START + 0x23)
+#define MI_COLLERR (READER_ERR_BASE_START + 0x24)
+#define MI_RESETERR (READER_ERR_BASE_START + 0x25)
+#define MI_INITERR (READER_ERR_BASE_START + 0x25)
+#define MI_INTERFACEERR (READER_ERR_BASE_START + 0x26)
+#define MI_ACCESSTIMEOUT (READER_ERR_BASE_START + 0x27)
+#define MI_NOBITWISEANTICOLL (READER_ERR_BASE_START + 0x28)
+#define MI_QUIT (READER_ERR_BASE_START + 0x30)
+#define MI_CODINGERR (READER_ERR_BASE_START + 0x31)
+#define MI_SENDBYTENR (READER_ERR_BASE_START + 0x51)
+#define MI_CASCLEVEX (READER_ERR_BASE_START + 0x52)
+#define MI_SENDBUF_OVERFLOW (READER_ERR_BASE_START + 0x53)
+#define MI_BAUDRATE_NOT_SUPPORTED (READER_ERR_BASE_START + 0x54)
+#define MI_SAME_BAUDRATE_REQUIRED (READER_ERR_BASE_START + 0x55)
+
+#define MI_WRONG_PARAMETER_VALUE (READER_ERR_BASE_START + 0x60)
+
+// ICODE1 Error Codes
+#define I1_WRONGPARAM (READER_ERR_BASE_START + 0x61)
+#define I1_NYIMPLEMENTED (READER_ERR_BASE_START + 0x62)
+#define I1_TSREADY (READER_ERR_BASE_START + 0x63)
+
+#define I1_TIMEOUT (READER_ERR_BASE_START + 0x70)
+#define I1_NOWRITE (READER_ERR_BASE_START + 0x71)
+#define I1_NOHALT (READER_ERR_BASE_START + 0x72)
+#define I1_MISS_ANTICOLL (READER_ERR_BASE_START + 0x73)
+
+#define I1_COMM_ABORT (READER_ERR_BASE_START + 0x82)
+
+#define MI_BREAK (READER_ERR_BASE_START + 0x99)
+#define MI_NY_IMPLEMENTED (READER_ERR_BASE_START + 0x100)
+#define MI_NO_MFRC (READER_ERR_BASE_START + 0x101)
+#define MI_MFRC_NOTAUTH (READER_ERR_BASE_START + 0x102)
+#define MI_WRONG_DES_MODE (READER_ERR_BASE_START + 0x103)
+#define MI_HOST_AUTH_FAILED (READER_ERR_BASE_START + 0x104)
+
+#define MI_WRONG_LOAD_MODE (READER_ERR_BASE_START + 0x106)
+#define MI_WRONG_DESKEY (READER_ERR_BASE_START + 0x107)
+#define MI_MKLOAD_FAILED (READER_ERR_BASE_START + 0x108)
+#define MI_FIFOERR (READER_ERR_BASE_START + 0x109)
+#define MI_WRONG_ADDR (READER_ERR_BASE_START + 0x110)
+#define MI_DESKEYLOAD_FAILED (READER_ERR_BASE_START + 0x111)
+#define MI_RECBUF_OVERFLOW (READER_ERR_BASE_START + 0x112)
+#define MI_WRONG_SEL_CNT (READER_ERR_BASE_START + 0x114)
+
+#define MI_WRONG_TEST_MODE (READER_ERR_BASE_START + 0x117)
+#define MI_TEST_FAILED (READER_ERR_BASE_START + 0x118)
+#define MI_TOC_ERROR (READER_ERR_BASE_START + 0x119)
+#define MI_COMM_ABORT (READER_ERR_BASE_START + 0x120)
+#define MI_INVALID_BASE (READER_ERR_BASE_START + 0x121)
+#define MI_MFRC_RESET (READER_ERR_BASE_START + 0x122)
+#define MI_WRONG_VALUE (READER_ERR_BASE_START + 0x123)
+#define MI_VALERR (READER_ERR_BASE_START + 0x124)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MFERRNO_H
diff --git a/icc_apdu_lib/MfRc500.h b/icc_apdu_lib/MfRc500.h
new file mode 100644
index 0000000..46ac3a8
--- /dev/null
+++ b/icc_apdu_lib/MfRc500.h
@@ -0,0 +1,182 @@
+/*
+* Copyright (c), Philips Semiconductors Gratkorn / Austria
+*
+* (C)PHILIPS Electronics N.V.2000
+* All rights are reserved. Reproduction in whole or in part is
+* prohibited without the written consent of the copyright owner.
+* Philips reserves the right to make changes without notice at any time.
+* Philips makes no warranty, expressed, implied or statutory, including but
+* not limited to any implied warranty of merchantability or fitness for any
+*particular purpose, or that the use will not infringe any third party patent,
+* copyright or trademark. Philips must not be liable for any loss or damage
+* arising from its use.
+*/
+
+#ifndef MFRC500_H
+#define MFRC500_H
+
+// PCD Configuration
+unsigned short Mf500PcdConfig(void);
+
+// Active Antenna Slave Configuration of the MF RC500.
+unsigned short Mf500ActiveAntennaSlaveConfig(void);
+
+// Active Antenna Master Configuration of the MF RC 500
+unsigned short Mf500ActiveAntennaMasterConfig(void);
+
+// Set default attributes for the baudrate divider
+unsigned short Mf500PcdSetDefaultAttrib(void);
+
+// Set attributes for the baudrate divider
+unsigned short Mf500PcdSetAttrib(unsigned char DSI,
+ unsigned char DRI);
+
+// Get transmission properties of the PCD
+unsigned short Mf500PcdGetAttrib(unsigned char *FSCImax,
+ unsigned char *FSDImax,
+ unsigned char *DSsupp,
+ unsigned char *DRsupp,
+ unsigned char *DREQDS);
+
+// PICC Request command
+unsigned short Mf500PiccRequest(unsigned char req_code,
+ unsigned char *atq);
+
+// PICC Request command for ISO 14443 A-4 Command set
+unsigned short Mf500PiccCommonRequest(unsigned char req_code,
+ unsigned char *atq);
+
+// PICC Anticollision Command
+unsigned short Mf500PiccAnticoll (unsigned char bcnt,
+ unsigned char *snr);
+
+// PICC Cascaded Anticollision Command
+unsigned short Mf500PiccCascAnticoll (unsigned char select_code,
+ unsigned char bcnt,
+ unsigned char *snr);
+
+// PICC Select Command
+unsigned short Mf500PiccSelect(unsigned char *snr,
+ unsigned char *sak);
+
+// PICC Select Command
+unsigned short Mf500PiccCascSelect(unsigned char select_code,
+ unsigned char *snr,
+ unsigned char *sak);
+
+// Activation of a PICC in IDLE mode
+unsigned short Mf500PiccActivateIdle(unsigned char br,
+ unsigned char *atq,
+ unsigned char *sak,
+ unsigned char *uid,
+ unsigned char *uid_len);
+
+// Activation of all PICC's in the RF field
+unsigned short Mf500PiccActivateWakeup(unsigned char br,
+ unsigned char *atq,
+ unsigned char *sak,
+ unsigned char *uid,
+ unsigned char uid_len);
+
+// MIFARE® Authentication
+unsigned short Mf500PiccAuth(unsigned char auth_mode,
+ unsigned char key_sector,
+ unsigned char block);
+
+// MIFARE ® Authentication with keys stored in the MF RC 500's EEPROM.
+unsigned short Mf500PiccAuthE2( unsigned char auth_mode,
+ unsigned char *snr,
+ unsigned char key_sector,
+ unsigned char block);
+
+// Authentication Key Coding
+unsigned short Mf500HostCodeKey(unsigned char *uncoded,
+ unsigned char *coded);
+
+// Key Loading into the MF RC500's EEPROM.
+unsigned short Mf500PcdLoadKeyE2(unsigned char key_type,
+ unsigned char sector,
+ unsigned char *uncoded_keys);
+
+// Authentication with direct key loading form the microcontroller
+unsigned short Mf500PiccAuthKey(unsigned char auth_mode,
+ unsigned char *snr,
+ unsigned char *keys,
+ unsigned char sector);
+
+// PICC Read Block
+unsigned short Mf500PiccRead(unsigned char addr,
+ unsigned char* data);
+
+// PICC Read Block of variable length
+unsigned short Mf500PiccCommonRead(unsigned char cmd,
+ unsigned char addr,
+ unsigned char datalen,
+ unsigned char *data);
+
+// PICC Write Block
+unsigned short Mf500PiccWrite(unsigned char addr,
+ unsigned char *data);
+
+// PICC Write 4 Byte Block
+unsigned short Mf500PiccWrite4(unsigned char addr,
+ unsigned char *data);
+
+// PICC Write Block of variable length
+unsigned short Mf500PiccCommonWrite(unsigned char cmd,
+ unsigned char addr,
+ unsigned char datalen,
+ unsigned char *data);
+
+// PICC Value Block Operation
+unsigned short Mf500PiccValue(unsigned char dd_mode,
+ unsigned char addr,
+ unsigned char *value,
+ unsigned char trans_addr);
+
+// PICC Value Block Operation for Cards with automatic transfer
+unsigned short Mf500PiccValueDebit(unsigned char dd_mode,
+ unsigned char addr,
+ unsigned char *value);
+
+// Exchange Data Blocks PCD --> PICC --> PCD
+unsigned short Mf500PiccExchangeBlock(unsigned char *send_data,
+ unsigned short send_bytelen,
+ unsigned char *rec_data,
+ unsigned short *rec_bytelen,
+ unsigned char append_crc,
+ unsigned long timeout );
+
+// PICC Halt
+unsigned short Mf500PiccHalt(void);
+
+// Reset the reader ic
+unsigned short PcdReset(void);
+
+// Exchange Data Stream PCD --> PICC --> PCD
+unsigned short ExchangeByteStream(unsigned char Cmd,
+ unsigned char *send_data,
+ unsigned short send_bytelen,
+ unsigned char *rec_data,
+ unsigned short *rec_bytelen);
+
+// Set RF communication timeout
+unsigned short PcdSetTmo(unsigned long numberOfEtus);
+
+// Read Serial Number from Reader IC
+unsigned short PcdGetSnr(unsigned char *snr);
+
+// Read EEPROM Memory Block
+unsigned short PcdReadE2(unsigned short startaddr,
+ unsigned char length,
+ unsigned char* data);
+
+// Writes data to the reader IC's EEPROM blocks.
+unsigned short PcdWriteE2( unsigned short startaddr,
+ unsigned char length,
+ unsigned char* data);
+
+// Turns ON/OFF RF field
+unsigned short PcdRfReset(unsigned short ms);
+
+#endif
diff --git a/icc_apdu_lib/MfRc500uC.c b/icc_apdu_lib/MfRc500uC.c
new file mode 100644
index 0000000..d571591
--- /dev/null
+++ b/icc_apdu_lib/MfRc500uC.c
@@ -0,0 +1,1821 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c), Philips Semiconductors Gratkorn
+//
+// (C)PHILIPS Electronics N.V.2000
+// All rights are reserved.
+// Philips reserves the right to make changes without notice at any time.
+// Philips makes no warranty, expressed, implied or statutory, including but
+// not limited to any implied warranty of merchantibility or fitness for any
+//particular purpose, or that the use will not infringe any third party patent,
+// copyright or trademark. Philips must not be liable for any loss or damage
+// arising from its use.
+///////////////////////////////////////////////////////////////////////////////
+#include <string.h>
+#include <stdio.h>
+
+#include "RICReg.h"
+#include "MfRc500.h"
+#include "PICCCmdConst.h"
+#include "MfErrNo.h"
+
+// storage buffer for receive and transmit routines
+//{
+#define MEMORY_BUFFER_SIZE 256
+unsigned char MemPool[MEMORY_BUFFER_SIZE];
+
+unsigned char *MSndBuffer = MemPool; // pointer to the transmit buffer
+unsigned char *MRcvBuffer = MemPool; // pointer to the receive buffer
+//}
+
+extern void HW_SPI_RF_CfgInit(void);
+extern void MFRC500_RstSet(void);
+extern void MFRC500_RstClr(void);
+
+void CalulateCRC(unsigned char *pIndata,unsigned char len,unsigned char *pOutData);
+
+#define READER_RESET MFRC500_RstClr()
+#define READER_CLEAR_RESET MFRC500_RstSet()
+
+// Write one byte to the reader IC address space
+/*!
+* -o address (IN) reader ic register address
+* -o value (IN) 8 bit value
+* return: none
+*
+* Function for writting one char to the reader module
+*
+* The reader module is connected to a 16 bit demultiplexed bus,
+* therefore the address pin of the reader module is mapped as
+* follows: \n
+* uC Reader \n
+* A1 A0 \n
+* A2 A1 \n
+* A3 A2 \n
+*
+* In order to get the correct address, the original address need to
+* be multiplied by 2.
+*/
+
+extern void WriteRawRC(unsigned char value, unsigned char addr);
+
+//! Read one byte from the reader IC address space
+/*!
+* -o address (IN) reader ic register address
+* -o value (IN) 8 bit value
+* return: none
+*
+* Function for reading one char from the reader module
+*
+* The reader module is connected to a 16 bit demultiplexed bus,
+* therefore the address pin of the reader module is mapped as
+* follows: \n
+* uC Reader \n
+* A1 A0 \n
+* A2 A1 \n
+* A3 A2 \n
+*
+* In order to get the correct address, the original address need to
+* be multiplied by 2.
+*/
+extern unsigned char ReadRawRC(unsigned char addr);
+
+
+//! Write one byte to the reader IC address space
+/*!
+* -o address (IN) reader ic register address
+* -o value (IN) 8 bit value
+* return: none
+*
+* This function determines the necessary page address of the
+* reader module and writes the page number to the page
+* register and the value to the specified address.
+*/
+void WriteRC(unsigned char Address, unsigned char value);
+
+//! Write one byte to the reader IC address space
+/*
+* -o address (IN) reader IC register address
+* return: value 8 bit data, read from the reader ic address space
+*
+* This function determines the necessary page address of the
+* reader module and writes the page number to the page
+* register and reads the value from the specified address.
+*/
+unsigned char ReadRC(unsigned char Address);
+
+
+///////////////////////////////////////////////////////////////////////////////
+// G E N E R I C W R I T E
+///////////////////////////////////////////////////////////////////////////////
+void WriteRC(unsigned char Address, unsigned char value)
+{
+ WriteRawRC(value, Address); // write value at the specified
+ // address
+}
+
+///////////////////////////////////////////////////////////////////////////////
+// G E N E R I C R E A D
+///////////////////////////////////////////////////////////////////////////////
+unsigned char ReadRC(unsigned char Address)
+{
+ return ReadRawRC(Address); // read value at the specified
+}
+
+/// Set Reader IC Register Bit
+/*!
+* -o reg (IN)
+* register address
+* -o mask (IN)
+* Bit mask to set
+* return: none
+*
+* This function performs a read - modify - write sequence
+* on the specified register. All bits with a 1 in the mask
+* are set - all other bits keep their original value.
+*/
+void SetBitMask(unsigned char reg,unsigned char mask);
+
+/// Clear Reader IC Register Bit
+/*!
+* -o reg (IN)
+* register address
+* -o mask (IN)
+* Bit mask to clear
+* return: none
+*
+* This function performs a read - modify - write sequence
+* on the specified register. All bits with a 1 in the mask
+* are cleared - all other bits keep their original value.
+*/
+void ClearBitMask(unsigned char reg,unsigned char mask);
+
+/// Flush remaining data from the FIFO
+/*!
+* -o none
+* return: none
+*
+* This function erases all remaining data in the MF RC 500's FIFO .
+* Before writing new data or starting a new command, all remaining data
+* from former commands should be deleted.
+*/
+void FlushFIFO(void);
+
+/// Sleep several milliseconds
+/*
+The implementation of this function depends heavily
+on the microcontroller in use. The measurement need not to be
+very accurate. Only make sure, that the periode is not shorter, than
+the required one.
+*/
+void SleepMs(unsigned short ms)
+{
+ int i;
+ for(i=0;i<4200*ms;i++);
+}
+
+/// Sleep several microseconds
+/*
+The implementation of this function depends heavily
+on the microcontroller in use. The measurement need not to be
+very accurate. Only make sure, that the periode is not shorter, than
+the required one.
+*/
+void SleepUs(unsigned short us)
+{
+ int i;
+ for( i = 0; i < 20 * us; i++ );
+}
+
+///////////////////////////////////////////////////////////////////////
+// S e t T i m e o u t L E N G T H
+///////////////////////////////////////////////////////////////////////
+unsigned short PcdSetTmo(unsigned long tmoLength)
+{
+ WriteRC(TModeReg,0x8D);
+ WriteRC(TPrescalerReg,0x3E);
+ WriteRC(TReloadRegH,0x01);
+ WriteRC(TReloadRegL,0x64);
+ return MI_OK;
+}
+
+//////////////////////////////////////////////////////////////////////
+// R E S E T
+///////////////////////////////////////////////////////////////////////
+unsigned short PcdRfReset(unsigned short ms)
+{
+ char status = MI_OK;
+
+ ClearBitMask(TxControlReg, 0x03); // Tx2RF-En, Tx1RF-En disablen
+ if (ms > 0)
+ {
+ SleepMs(ms); // Delay for 1 ms
+ SetBitMask(TxControlReg, 0x03); // Tx2RF-En, Tx1RF-En enable
+ }
+ return status;
+}
+
+//////////////////////////////////////////////////////////////////////
+// S E T A B I T M A S K
+///////////////////////////////////////////////////////////////////////
+void SetBitMask(unsigned char reg,unsigned char mask) //
+{
+ char tmp = 0x0;
+
+ tmp = ReadRC(reg);
+ WriteRC(reg,tmp | mask); // set bit mask
+}
+
+//////////////////////////////////////////////////////////////////////
+// C L E A R A B I T M A S K
+///////////////////////////////////////////////////////////////////////
+void ClearBitMask(unsigned char reg,unsigned char mask) //
+{
+ char tmp = 0x0;
+
+ tmp = ReadRC(reg);
+ WriteRC(reg,tmp & (~mask)); // clear bit mask
+}
+
+///////////////////////////////////////////////////////////////////////
+// F L U S H F I F O
+///////////////////////////////////////////////////////////////////////
+void FlushFIFO(void)
+{
+ SetBitMask(FIFOLevelReg, 0x80);
+}
+
+void CalulateCRC(unsigned char *pIndata,unsigned char len,unsigned char *pOutData)
+{
+ unsigned char i,n;
+ ClearBitMask(DivIrqReg,0x04);
+ WriteRC(CommandReg,PCD_IDLE);
+ SetBitMask(FIFOLevelReg,0x80);
+ for (i=0; i<len; i++)
+ { WriteRC(FIFODataReg, *(pIndata+i)); }
+ WriteRC(CommandReg, PCD_CALCCRC);
+ i = 0xFF;
+ do
+ {
+ n = ReadRC(DivIrqReg);
+ i--;
+ }
+ while ((i!=0) && !(n&0x04));
+ pOutData[0] = ReadRC(CRCResultRegL);
+ pOutData[1] = ReadRC(CRCResultRegM);
+}
+
+
+
+//M1¿¨²Ù×÷½Ó¿Ú
+#define M1_BIT_AUTH 0x08 // bit3 ÃÜÂëУÑé¿ØÖÆλ - 0 - ²»Ð£ÑéÃÜÂë 1 - ҪУÑéÃÜÂë
+#define M1_BIT_RQST 0x04 // bit2 Ñ°¿¨¿ØÖÆλ - 0 - Ñ°¿¨ 1 - ²»Ñ°¿¨
+#define M1_BIT_AUTHTYPE 0x03 // bit1 bit0ÃÜÂë¿ØÖÆλ - AÃÜÂë»òBÃÜÂë( 0 - A 1 - B)
+
+#define MI_ERR 0x02
+
+#define M1_OK 0x00
+#define M1_ERR_REQUEST 0x01
+#define M1_ERR_ANTI 0x02
+#define M1_ERR_SELECT 0x03
+#define M1_ERR_READ 0x05
+#define M1_ERR_WRITE 0x06
+#define M1_ERR_AUTH 0x07
+#define M1_ERR_TIMEOUT 0x11
+#define M1_ERR_COMM 0x12
+#define M1_ERR_BITS 0x13
+#define M1_ERR_ACK 0x14
+#define M1_ERR_AUTH1 0x15
+#define M1_ERR_AUTH2 0x16
+#define M1_ERR_SNRCHK 0x17
+#define M1_ERR_RCVBITS 0x18
+#define M1_ERR_BADCOMMAND 0x19
+#define M1_ERR_PCDFAIL 0x30
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£ºÍ¨¹ýRC522ºÍISO14443¿¨Í¨Ñ¶
+//²ÎÊý˵Ã÷£ºCommand[IN]:RC522ÃüÁî×Ö
+// pInData[IN]:ͨ¹ýRC522·¢Ë͵½¿¨Æ¬µÄÊý¾Ý
+// InLenByte[IN]:·¢ËÍÊý¾ÝµÄ×Ö½Ú³¤¶È
+// pOutData[OUT]:½ÓÊÕµ½µÄ¿¨Æ¬·µ»ØÊý¾Ý
+// *pOutLenBit[OUT]:·µ»ØÊý¾ÝµÄ볤¶È
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdComMF522(unsigned char Command,
+ unsigned char *pInData,
+ unsigned char InLenByte,
+ unsigned char *pOutData,
+ unsigned int *pOutLenBit)
+{
+ unsigned short status = MI_ERR;
+ unsigned char irqEn = 0x00;
+ unsigned char waitFor = 0x00;
+ unsigned char lastBits;
+ unsigned char n;
+ unsigned int i;
+
+ switch (Command)
+ {
+ case PCD_AUTHENT:
+ irqEn = 0x12;
+ waitFor = 0x10;
+ break;
+ case PCD_TRANSCEIVE:
+ irqEn = 0x77;
+ waitFor = 0x30;
+ break;
+ default:
+ break;
+ }
+
+ WriteRC(ComIEnReg,irqEn|0x80);
+ ClearBitMask(ComIrqReg,0x80);
+ WriteRC(CommandReg,PCD_IDLE);
+ SetBitMask(FIFOLevelReg,0x80);
+
+ for (i=0; i<InLenByte; i++)
+ { WriteRC(FIFODataReg, pInData[i]); }
+ WriteRC(CommandReg, Command);
+
+
+ if (Command == PCD_TRANSCEIVE)
+ { SetBitMask(BitFramingReg,0x80); }
+
+ i = 500;//¸ù¾ÝʱÖÓƵÂʵ÷Õû£¬²Ù×÷M1¿¨×î´óµÈ´ýʱ¼ä25ms
+ do
+ {
+ n = ReadRC(ComIrqReg);
+ i--;
+ }
+ while ((i!=0) && !(n&0x01) && !(n&waitFor));
+ ClearBitMask(BitFramingReg,0x80);
+
+ *pOutLenBit = 0;
+ if (i!=0)
+ {
+ if(!(ReadRC(ErrorReg)&0x1B))
+ {
+ status = MI_OK;
+ if (n & irqEn & 0x01)
+ { status = MI_NOTAGERR; }
+ if (Command == PCD_TRANSCEIVE)
+ {
+ n = ReadRC(FIFOLevelReg);
+ lastBits = ReadRC(ControlReg) & 0x07;
+ if (lastBits)
+ { *pOutLenBit = (n-1)*8 + lastBits; }
+ else
+ { *pOutLenBit = n*8; }
+ if (n == 0)
+ { n = 1; }
+ if (n > 18) //m1¿¨×î´ó18×Ö½Ú
+ { n = 18; }
+ for (i=0; i<n; i++)
+ { pOutData[i] = ReadRC(FIFODataReg); }
+ }
+ }
+ else
+ { status = MI_ERR; }
+
+ }
+
+
+ SetBitMask(ControlReg,0x80); // stop timer now
+ WriteRC(CommandReg,PCD_IDLE);
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£ºÑ°¿¨
+//²ÎÊý˵Ã÷: req_code[IN]:Ñ°¿¨·½Ê½
+// 0x52 = Ñ°¸ÐÓ¦ÇøÄÚËùÓзûºÏ14443A±ê×¼µÄ¿¨
+// 0x26 = Ѱδ½øÈëÐÝÃß״̬µÄ¿¨
+// pTagType[OUT]£º¿¨Æ¬ÀàÐÍ´úÂë
+// 0x4400 = Mifare_UltraLight
+// 0x0400 = Mifare_One(S50)
+// 0x0200 = Mifare_One(S70)
+// 0x0800 = Mifare_Pro(X)
+// 0x4403 = Mifare_DESFire
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdRequest(unsigned char req_code,unsigned char *pTagType)
+{
+ unsigned short status;
+ unsigned int unLen;
+
+ ClearBitMask(Status2Reg,0x08);
+ WriteRC(BitFramingReg,0x07);
+ SetBitMask(TxControlReg,0x03);
+
+ MSndBuffer[0] = req_code;
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 1, MRcvBuffer, &unLen);
+
+ if ((status == MI_OK) && (unLen == 0x10))
+ {
+ if(pTagType)
+ {
+ *pTagType = MRcvBuffer[0];
+ *(pTagType+1) = MRcvBuffer[1];
+ }
+ }
+ else
+ { status = MI_ERR; }
+
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£º·À³åײ
+//²ÎÊý˵Ã÷: pSnr[OUT]:¿¨Æ¬ÐòÁкţ¬4×Ö½Ú
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdAnticoll(unsigned char *pSnr)
+{
+ unsigned short status;
+ unsigned char i,snr_check=0;
+ unsigned int unLen;
+
+ ClearBitMask(Status2Reg,0x08);
+ WriteRC(BitFramingReg,0x00);
+ ClearBitMask(CollReg,0x80);
+
+ MSndBuffer[0] = PICC_ANTICOLL1;
+ MSndBuffer[1] = 0x20;
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 2, MRcvBuffer, &unLen);
+
+ if (status == MI_OK)
+ {
+ for (i=0; i<4; i++)
+ {
+ *(pSnr+i) = MRcvBuffer[i];
+ snr_check ^= MRcvBuffer[i];
+ }
+ if (snr_check != MRcvBuffer[i])
+ { status = MI_ERR; }
+ }
+
+ SetBitMask(CollReg,0x80);
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£ºÑ¡¶¨¿¨Æ¬
+//²ÎÊý˵Ã÷: pSnr[IN]:¿¨Æ¬ÐòÁкţ¬4×Ö½Ú
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdSelect(unsigned char *pSnr, unsigned char* sak)
+{
+ unsigned short status;
+ unsigned char i;
+ unsigned int unLen;
+
+ MSndBuffer[0] = PICC_ANTICOLL1;
+ MSndBuffer[1] = 0x70;
+ MSndBuffer[6] = 0;
+ for (i=0; i<4; i++)
+ {
+ MSndBuffer[i+2] = *(pSnr+i);
+ MSndBuffer[6] ^= *(pSnr+i);
+ }
+ CalulateCRC(MSndBuffer, 7,&MSndBuffer[7]);
+
+ ClearBitMask(Status2Reg,0x08);
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 9, MRcvBuffer, &unLen);
+
+ if ((status == MI_OK) && (unLen == 0x18))
+ {
+ *sak = MRcvBuffer[0];
+ status = MI_OK;
+ }
+ else
+ { status = MI_ERR; }
+
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£ºÑéÖ¤¿¨Æ¬ÃÜÂë
+//²ÎÊý˵Ã÷: auth_mode[IN]: ÃÜÂëÑé֤ģʽ
+// 0x60 = ÑéÖ¤AÃÜÔ¿
+// 0x61 = ÑéÖ¤BÃÜÔ¿
+// addr[IN]£º¿éµØÖ·
+// pKey[IN]£ºÃÜÂë
+// pSnr[IN]£º¿¨Æ¬ÐòÁкţ¬4×Ö½Ú
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdAuthState(unsigned char auth_mode,unsigned char addr,unsigned char *pKey,unsigned char *pSnr)
+{
+ unsigned short status;
+ unsigned int unLen;
+ unsigned char i;
+
+ MSndBuffer[0] = auth_mode;
+ MSndBuffer[1] = addr;
+ for (i=0; i<6; i++)
+ { MSndBuffer[i+2] = *(pKey+i); }
+ for (i=0; i<6; i++)
+ { MSndBuffer[i+8] = *(pSnr+i); }
+
+ status = PcdComMF522(PCD_AUTHENT, MSndBuffer, 12, MRcvBuffer, &unLen);
+ if ((status != MI_OK) || (!(ReadRC(Status2Reg) & 0x08)))
+ { status = MI_ERR; }
+
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£º¶ÁÈ¡M1¿¨Ò»¿éÊý¾Ý
+//²ÎÊý˵Ã÷: addr[IN]£º¿éµØÖ·
+// pData[OUT]£º¶Á³öµÄÊý¾Ý£¬16×Ö½Ú
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdRead(unsigned char addr,unsigned char *pData)
+{
+ unsigned short status;
+ unsigned int unLen;
+ unsigned char i;
+
+ MSndBuffer[0] = PICC_READ16;
+ MSndBuffer[1] = addr;
+ CalulateCRC(MSndBuffer, 2, &MSndBuffer[2]);
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 4, MRcvBuffer, &unLen);
+ if ((status == MI_OK) && (unLen == 0x90))
+ {
+ for (i=0; i<16; i++)
+ { *(pData+i) = MRcvBuffer[i]; }
+ }
+ else
+ { status = MI_ERR; }
+
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£ºÐ´Êý¾Ýµ½M1¿¨Ò»¿é
+//²ÎÊý˵Ã÷: addr[IN]£º¿éµØÖ·
+// pData[IN]£ºÐ´ÈëµÄÊý¾Ý£¬16×Ö½Ú
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdWrite(unsigned char addr,unsigned char *pData)
+{
+ unsigned short status;
+ unsigned int unLen;
+ unsigned char i;
+
+ MSndBuffer[0] = PICC_WRITE16;
+ MSndBuffer[1] = addr;
+ CalulateCRC(MSndBuffer, 2, &MSndBuffer[2]);
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 4, MRcvBuffer, &unLen);
+
+ if ((status != MI_OK) || (unLen != 4) || ((MRcvBuffer[0] & 0x0F) != 0x0A))
+ { status = MI_ERR; }
+
+ if (status == MI_OK)
+ {
+ for (i=0; i<16; i++)
+ { MSndBuffer[i] = *(pData+i); }
+ CalulateCRC(MSndBuffer, 16, &MSndBuffer[16]);
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 18, MRcvBuffer, &unLen);
+ if ((status != MI_OK) || (unLen != 4) || ((MRcvBuffer[0] & 0x0F) != 0x0A))
+ { status = MI_ERR; }
+ }
+
+ return status;
+}
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£ºÃüÁƬ½øÈëÐÝÃß״̬
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdHalt(void)
+{
+ unsigned short status;
+ unsigned int unLen;
+
+ MSndBuffer[0] = PICC_HALT;
+ MSndBuffer[1] = 0;
+ CalulateCRC(MSndBuffer, 2, &MSndBuffer[2]);
+
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, 4, MRcvBuffer, &unLen);
+
+ return status;
+}
+
+extern void HW_SleepUs( unsigned short us );
+
+/////////////////////////////////////////////////////////////////////
+//¹¦ ÄÜ£º¸´Î»RC522
+//·µ »Ø: ³É¹¦·µ»ØMI_OK
+/////////////////////////////////////////////////////////////////////
+unsigned short PcdReset(void)
+{
+ MFRC500_RstSet();
+ HW_SleepUs(500);
+ MFRC500_RstClr();
+ HW_SleepUs(200);
+ MFRC500_RstSet();
+ HW_SleepUs(500);
+
+ WriteRC(CommandReg,PCD_RESETPHASE);
+ WriteRC(ModeReg,0x3D); //ºÍMifare¿¨Í¨Ñ¶£¬CRC³õʼֵ0x6363
+ WriteRC(TReloadRegL,30);
+ WriteRC(TReloadRegH,0);
+ WriteRC(TModeReg,0x8D);
+ WriteRC(TPrescalerReg,0x3E);
+ WriteRC(TxAskReg,0x40);
+
+ return MI_OK;
+}
+
+unsigned char M1_BlkRead(unsigned char Mode,
+ unsigned char Block,
+ unsigned char *pSN,
+ unsigned char *pBuffer,
+ unsigned char *pKey)
+{
+ unsigned char auth_mode;
+ unsigned char buff[20];
+ unsigned char sak;
+
+ if(Mode&M1_BIT_AUTHTYPE&0x01)
+ {
+ auth_mode = PICC_AUTHENT1B;
+ }
+ else
+ {
+ auth_mode = PICC_AUTHENT1A;
+ }
+
+ if((Mode&M1_BIT_RQST) == 0)
+ {
+ if(PcdRequest(PICC_REQIDL, buff))
+ if(PcdRequest(PICC_REQIDL, buff))
+ return MI_ERR;
+
+ if(PcdAnticoll(pSN))
+ return M1_ERR_ANTI;
+
+ if(PcdSelect(pSN, &sak))
+ return M1_ERR_SELECT;
+
+ if(PcdAuthState(auth_mode, Block, pKey, pSN))
+ return M1_ERR_AUTH;
+ }
+ else
+ { if(Mode& M1_BIT_AUTH)
+ {
+ if(PcdAuthState(auth_mode, Block, pKey, pSN))
+ return M1_ERR_AUTH;
+ }
+ }
+
+ if(PcdRead(Block, buff)) //first read
+ return M1_ERR_READ;
+
+ memcpy(pBuffer, buff, 16);
+
+ if(PcdRead(Block, buff)) //second read
+ return M1_ERR_READ;
+ else
+ {
+ if( memcmp(pBuffer, buff, 16))
+ return M1_ERR_READ;
+ }
+
+ return MI_OK;
+}
+
+
+unsigned char M1_BlkWrite( unsigned char Mode,unsigned char Block, unsigned char *pSN, unsigned char * pBuffer, unsigned char *pKey )
+{
+ unsigned char auth_mode;
+ unsigned char buff[20];
+ unsigned char i;
+ unsigned char sak;
+
+ if(Mode&M1_BIT_AUTHTYPE&0x01)
+ {
+ auth_mode = PICC_AUTHENT1B;
+ }
+ else
+ {
+ auth_mode = PICC_AUTHENT1A;
+ }
+ //PcdReset();
+ if((Mode&M1_BIT_RQST) == 0)
+ {
+ if(PcdRequest(PICC_REQIDL, buff))
+ if(PcdRequest(PICC_REQIDL, buff))
+ return MI_ERR;
+
+ if(PcdAnticoll(pSN))
+ return M1_ERR_ANTI;
+
+ if(PcdSelect(pSN, &sak))
+ return M1_ERR_SELECT;
+
+ if(PcdAuthState(auth_mode, Block, pKey, pSN))
+ return M1_ERR_AUTH;
+ }
+ else
+ { if(Mode& M1_BIT_AUTH)
+ {
+ if(PcdAuthState(auth_mode, Block, pKey, pSN))
+ return M1_ERR_AUTH;
+ }
+ }
+
+ if(PcdWrite( Block, pBuffer))
+ return( M1_ERR_WRITE );
+
+ i = 0;
+ if( Block < 128)
+ {
+ if((Block % 4) == 3 )
+ i = 1;
+ }
+ else
+ {
+ if( (Block - 128) % 16 == 15 )
+ i = 1;
+ }
+ if( i == 0 )
+ {
+ if(PcdRead(Block, buff))
+ return M1_ERR_WRITE;
+ else
+ {
+ if(memcmp(pBuffer, buff, 16) != 0)
+ return M1_ERR_WRITE;
+ }
+ }
+
+ return MI_OK;
+}
+
+void M1_RCReset(void)
+{
+ PcdReset();
+}
+
+unsigned char GetM1SN(unsigned char *pSN)
+{
+ if(PcdAnticoll(pSN))
+ return M1_ERR_ANTI;
+
+ return MI_OK;
+}
+
+unsigned char M1_Request(unsigned char RequestMode, unsigned char* atq)
+{
+ if(PcdRequest(RequestMode, atq))
+ return M1_ERR_REQUEST;
+
+ return MI_OK;
+}
+
+unsigned char M1_Anti(unsigned char Bcnt, unsigned char *Snr)
+{
+ if(PcdAnticoll(Snr))
+ return M1_ERR_ANTI;
+
+ return MI_OK;
+}
+
+unsigned char M1_Select(unsigned char *Snr)
+{
+ unsigned char sak;
+
+ if(PcdSelect(Snr, &sak))
+ return M1_ERR_SELECT;
+
+ return MI_OK;
+}
+
+unsigned char M1_AuthBlk(unsigned char AuthMode, unsigned char *Snr, unsigned char Block, unsigned char *key )
+{
+ if(PcdAuthState(AuthMode, Block, key, Snr))
+ return M1_ERR_AUTH;
+
+ return MI_OK;
+}
+
+void M1_HardPwrDwn(void)
+{
+ READER_RESET;
+}
+
+unsigned char M1_PCDSn(unsigned char * pBuffer)
+{
+ return MI_OK;
+}
+
+void M1_RadioOff(void)
+{
+ PcdRfReset(0);
+}
+
+void M1_RadioOn(void)
+{
+ PcdRfReset(1);
+}
+
+unsigned char M1_Read(unsigned char Block, unsigned char* ReadBuffer)
+{
+ if(PcdRead(Block, ReadBuffer))
+ return M1_ERR_READ;
+
+ return MI_OK;
+}
+
+unsigned char M1_Write(unsigned char Block, unsigned char* WriteBuffer)
+{
+ if(PcdWrite(Block, WriteBuffer))
+ return M1_ERR_WRITE;
+
+ return MI_OK;
+}
+
+unsigned char M1_Halt(void)
+{
+ PcdHalt();
+
+ return MI_OK;
+}
+
+
+#if 0
+///////////////////////////////////////////////////////////////////////
+// M I F A R E P I C C A C T I V A T I O N S E Q E N C E
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccActivateIdle(unsigned char br,
+ unsigned char *atq,
+ unsigned char *sak,
+ unsigned char *uid,
+ unsigned char *uid_len)
+{
+ unsigned short status = MI_OK;
+
+ status = M1_Request(PICC_REQIDL,atq);
+ if(status != MI_OK) return status;
+
+ status = M1_Anti(0, uid);
+ if(status != MI_OK) return status;
+ *uid_len = 4;
+
+ if(PcdSelect(uid, sak)) return status;
+
+ return MI_OK;
+}
+
+
+//////////////////////////////////////////////////////////////////////
+// P I C C E X C H A N G E B L O C K
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccExchangeBlock(unsigned char *send_data,
+ unsigned short send_bytelen,
+ unsigned char *rec_data,
+ unsigned short *rec_bytelen,
+ unsigned char append_crc,
+ unsigned long timeout )
+{
+ char status = MI_OK;
+
+ send_bytelen -= 2;
+ if (append_crc)
+ {
+ CalulateCRC(send_data, send_bytelen, send_data+send_bytelen);
+ send_bytelen += 2;
+ }
+
+ PcdSetTmo(timeout);
+
+ status = ExchangeByteStream(PCD_TRANSCEIVE,
+ send_data,
+ send_bytelen,
+ rec_data,
+ rec_bytelen);
+ // even if an error occured, the data should be
+ // returned - for debugging reasons
+
+ if (append_crc)
+ {
+ *rec_bytelen += 2; // for two CRC bytes
+ rec_data[*rec_bytelen - 2] = 0x00;
+ rec_data[*rec_bytelen - 1] = 0x00;
+ }
+
+ return status;
+}
+
+///////////////////////////////////////////////////////////////////////
+// E X C H A N G E B Y T E S T R E A M
+///////////////////////////////////////////////////////////////////////
+unsigned short ExchangeByteStream(unsigned char Cmd,
+ unsigned char *send_data,
+ unsigned short send_bytelen,
+ unsigned char *rec_data,
+ unsigned short *rec_bytelen)
+{
+ unsigned short status = MI_OK;
+ unsigned int unLen;
+
+ FlushFIFO(); // empty FIFO
+
+ if (send_bytelen > 0)
+ {
+ memcpy(MSndBuffer, send_data, send_bytelen); // write n bytes
+
+ // write load command
+ status = PcdComMF522(PCD_TRANSCEIVE, MSndBuffer, send_bytelen, MRcvBuffer, &unLen);
+
+ // copy data to output, even in case of an error
+ *rec_bytelen = unLen/8;
+ if (*rec_bytelen)
+ {
+ memcpy(rec_data, MRcvBuffer, *rec_bytelen);
+ }
+ }
+ else
+ {
+ status = MI_WRONG_PARAMETER_VALUE;
+ }
+ return status;
+}
+#else
+// struct definition for a communication channel between function and ISR
+typedef struct
+ {
+ unsigned char cmd; //!< command code
+ unsigned char irqSource; //!< which interrupts have occured
+ unsigned short status; //!< communication status
+ unsigned short nBytesSent; //!< how many bytes already sent
+ unsigned short nBytesToSend; //!< how many bytes to send
+ unsigned short nBytesReceived;//!< how many bytes received
+ unsigned long nBitsReceived; //!< how many bits received
+ unsigned char collPos; /*!< at which position occured a
+ collision*/
+ unsigned char errFlags; //!< error flags
+ unsigned char saveErrorState;//!< accumulated error flags for
+ //!< multiple responses
+ unsigned char RxAlignWA; //!< workaround for RxAlign = 7
+ unsigned char DisableDF; //!< disable disturbance filter
+ } MfCmdInfo;
+
+// Convinience function for initialising the communication structure.
+#define ResetInfo(info) \
+ info.cmd = 0; \
+ info.status = MI_OK;\
+ info.irqSource = 0; \
+ info.nBytesSent = 0; \
+ info.nBytesToSend = 0; \
+ info.nBytesReceived = 0; \
+ info.nBitsReceived = 0; \
+ info.collPos = 0; \
+ info.errFlags = 0; \
+ info.saveErrorState = 0; \
+ info.RxAlignWA = 0; \
+ info.DisableDF = 0;
+
+// In order to exchange some values between the ISR and the calling function,
+// a struct is provided.
+volatile MfCmdInfo MInfo;
+
+// communication info stucture
+static volatile MfCmdInfo *MpIsrInfo = 0;
+// ISR send buffer
+static volatile unsigned char *MpIsrOut = 0;
+// ISR receive buffer
+static volatile unsigned char *MpIsrIn = 0;
+
+// storage of the last selected serial number including check byte.
+// For multi level serial numbers, only the first 4 bytes are stored.
+unsigned char MLastSelectedSnr[5];
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Interrupt Handler RIC
+///////////////////////////////////////////////////////////////////////////////
+//interrupt (READER_INT)
+void SingleResponseIsr(void)
+{
+ static unsigned char irqBits;
+ static unsigned char irqMask;
+ static unsigned char nbytes;
+ static unsigned char cnt;
+ unsigned int i = 0;
+
+ if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
+ // correctly
+ {
+ MpIsrInfo->errFlags = ReadRC(ErrorReg) & 0x0F; // save error state
+
+ //while( (ReadRC(Status1Reg) & 0x10)) // loop while IRQ pending
+ while(1)
+ {
+ if((i++) > 500) break;
+
+ irqMask = ReadRC(ComIEnReg); // read enabled interrupts
+ // read pending interrupts
+ irqBits = ReadRC(ComIrqReg) & irqMask;
+ MpIsrInfo->irqSource |= irqBits; // save pending interrupts
+
+ if(!(irqBits&0x7F)) break;
+
+ //************ LoAlertIRQ ******************
+ if (irqBits & 0x04) // LoAlert
+ {
+ nbytes = DEF_FIFO_LENGTH - ReadRC(FIFOLevelReg);
+ // less bytes to send, than space in FIFO
+ if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
+ {
+ nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
+ irqMask &= ~0x04;
+ ClearBitMask(ComIEnReg, 0x04); // disable LoAlert IRQ
+ }
+ // write remaining data to the FIFO
+ for ( cnt = 0;cnt < nbytes;cnt++)
+ {
+ WriteRC(FIFODataReg, MpIsrOut[MpIsrInfo->nBytesSent]);
+ MpIsrInfo->nBytesSent++;
+ }
+ if ((ReadRC(Status2Reg) & 0x07) == 0x01)
+ {
+ SetBitMask(BitFramingReg, 0x80);
+ }
+ WriteRC(ComIrqReg, 0x04); // reset IRQ bit
+ }
+
+ //************* TxIRQ Handling **************
+ if (irqBits & 0x40) // TxIRQ
+ {
+ WriteRC(ComIrqReg, 0x40); // reset IRQ bit
+ SetBitMask(ComIEnReg, 0x08); // enable HiAlert Irq for
+ // response
+ if (MpIsrInfo->RxAlignWA) // if cmd is anticollision and 7 bits are known
+ { // switch off parity generation
+ SetBitMask(RFU1D, 0x10); // RxCRC and TxCRC disable, parity disable
+ ClearBitMask(TxModeReg, 0x80);
+ ClearBitMask(RxModeReg, 0x80);
+ }
+ }
+ //**************** RxIRQ Handling *******************************
+ if (irqBits & 0x20) // RxIRQ - possible End of response processing
+ {
+ // no error or collision during
+ if (MpIsrInfo->DisableDF || (MpIsrInfo->errFlags == 0x00))
+ {
+ WriteRC(CommandReg, 0x00); // cancel current command
+ irqBits |= 0x10; // set idle flag in order to signal the end of
+ // processing. For single reponse processing, this
+ // flag is already set.
+ }
+ else // error occured - flush data and continue receiving
+ {
+ MpIsrInfo->saveErrorState = MpIsrInfo->errFlags; // save error state
+ MpIsrInfo->errFlags = 0; // reset error flags for next receiption
+ WriteRC(FIFOLevelReg, 0x80);
+ MpIsrInfo->nBytesReceived = 0x00;
+ irqBits &= ~0x20; // clear interrupt request
+ WriteRC(ComIrqReg, 0x20);
+ }
+ }
+
+ //************* HiAlertIRQ or RxIRQ Handling ******************
+ if (irqBits & 0x38) // HiAlert, Idle or valid RxIRQ
+ {
+ // read some bytes ( length of FIFO queue)
+ // into the receive buffer
+ nbytes = ReadRC(FIFOLevelReg);
+ // read date from the FIFO and store them in the receive buffer
+ do
+ {
+ for ( cnt = 0; cnt < nbytes; cnt++)
+ {
+ // accept no more data, than reserved memory space
+ if (MpIsrInfo->nBytesReceived < MEMORY_BUFFER_SIZE)
+ {
+ MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRC(FIFODataReg);
+ MpIsrInfo->nBytesReceived++;
+ }
+ else
+ {
+ MpIsrInfo->status = MI_RECBUF_OVERFLOW;
+ break;
+ }
+ }
+ // check for remaining bytes
+ nbytes = ReadRC(FIFOLevelReg);
+ }
+ while (MpIsrInfo->status == MI_OK && nbytes > 0);
+ WriteRC(ComIrqReg, 0x28 & irqBits);
+ // reset IRQ bit - idle irq will
+ // be deleted in a seperate section
+ }
+
+ //************* additional HiAlertIRQ Handling ***
+ if (irqBits & 0x08)
+ {
+ // if highAlertIRQ is pending and the receiver is still
+ // running, then the timeout counter should be stopped,
+ // otherwise a timeout could occure while receiving
+ // correct data
+ if ((ReadRC(Status2Reg) & 0x07) == 0x06)
+ {
+ cnt = ReadRC(ControlReg); // read control register
+ WriteRC(ControlReg, cnt|0x80); // stop reader IC timer
+ // write modified register
+ }
+ }
+
+ //************** additional IdleIRQ Handling ******
+ if (irqBits & 0x10) // Idle IRQ
+ {
+ ClearBitMask(ComIEnReg, 0x01);// disable Timer IRQ
+ WriteRC(ComIrqReg, 0x11); // disable Timer IRQ request
+ irqBits &= ~0x01; // clear Timer IRQ in local var
+ MpIsrInfo->irqSource &= ~0x01; // clear Timer IRQ in info var
+ // when idle received, then cancel
+ // timeout
+ MpIsrInfo->irqSource |= 0x10; // set idle-flag in case of valid rx-irq
+ // status should still be MI_OK
+ // no error - only used for wake up
+ }
+
+ //************* TimerIRQ Handling ***********
+ if (irqBits & 0x01) // timer IRQ
+ {
+ WriteRC(ComIrqReg, 0x01); // reset IRQ bit
+ // only if no other error occured
+ if (MpIsrInfo->status == MI_OK)
+ {
+ MpIsrInfo->status = MI_NOTAGERR; // timeout error
+ // otherwise ignore the interrupt
+ }
+ }
+ }
+ }
+}
+
+//////////////////////////////////////////////////////////////////////
+// W R I T E A P C D C O M M A N D
+///////////////////////////////////////////////////////////////////////
+unsigned short PcdSingleResponseCmd(unsigned char cmd,
+ volatile unsigned char* send,
+ volatile unsigned char* rcv,
+ volatile MfCmdInfo *info)
+{
+ unsigned short status = MI_OK;
+ unsigned char lastBits;
+ unsigned char validErrorFlags = 0x1F;
+ unsigned char irqEn = 0x00;
+ unsigned char waitFor = 0x00;
+ unsigned char waterLevelBackup;
+ unsigned int i = 0;
+
+ WriteRC(ComIEnReg, 0); // disable all interrupts
+ WriteRC(ComIrqReg, 0x80); // clear all interrupt requests
+
+ // please pay attention to the sequence of following commands
+ // at first empty the FIFO
+ // second wait for probably e2 programming in progress
+ // third cancel command
+ //
+ // ATTENTION: the guard timer must not expire earlier than 10 ms
+ FlushFIFO(); // flush FIFO buffer
+
+ WriteRC(CommandReg, PCD_IDLE);
+
+ // Set water level to the default value (see. 'PcdBasicRegisterConfiguration()')
+ waterLevelBackup = ReadRC(WaterLevelReg);
+ WriteRC(WaterLevelReg, 0x20);
+
+ // save info structures to module pointers
+ MpIsrInfo = info;
+ MpIsrOut = send;
+ MpIsrIn = rcv;
+
+ info->irqSource = 0x0; // reset interrupt flags
+
+ // depending on the command code, appropriate interrupts are enabled (irqEn)
+ // and the commit interrupt is choosen (waitFor).
+ switch(cmd)
+ {
+ case PCD_IDLE: // nothing else required
+ irqEn = 0x00;
+ waitFor = 0x00;
+ break;
+ case PCD_AUTHENT: //IdleIRq
+ irqEn = 0x12;
+ waitFor = 0x10;
+ break;
+ case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
+ info->nBitsReceived = -((ReadRC(BitFramingReg) >> 4)&0x07);
+ irqEn = 0x77;
+ waitFor = 0x30;
+ break;
+ default:
+ status = MI_UNKNOWN_COMMAND;
+ break;
+ }
+
+ if (status == MI_OK)
+ {
+ // Initialize uC Timer for global Timeout management
+ irqEn |= 0x01; // always enable timout irq
+ waitFor |= 0x01; // always wait for timeout
+
+ WriteRC(ComIEnReg, irqEn); //necessary interrupts are enabled // count up from 1
+ {
+ unsigned char nbytes;
+
+ if(MpIsrInfo->nBytesToSend>DEF_FIFO_LENGTH)
+ {
+ nbytes = DEF_FIFO_LENGTH;
+ }
+ else
+ {
+ nbytes = MpIsrInfo->nBytesToSend;
+ ClearBitMask(ComIEnReg, 0x04); // disable LoAlert IRQ
+ }
+ // write remaining data to the FIFO
+ for ( i = 0;i < nbytes;i++)
+ {
+ WriteRC(FIFODataReg, MpIsrOut[MpIsrInfo->nBytesSent]);
+ MpIsrInfo->nBytesSent++;
+ }
+ }
+
+ WriteRC(CommandReg, cmd); //start command
+ if(cmd == PCD_TRANSCEIVE)
+ SetBitMask(BitFramingReg, 0x80); //start send
+
+ // wait for commmand completion
+ // a command is completed, if the corresponding interrupt occurs
+ // or a timeout is signaled
+ while(1)
+ {
+ SingleResponseIsr();
+ if(waitFor&0x20)
+ {
+ if(MpIsrInfo->irqSource&0x20)
+ {
+ MpIsrInfo->irqSource &= 0x01;
+ if(MpIsrInfo->status == MI_NOTAGERR)
+ MpIsrInfo->status = MI_OK;
+ break;
+ }
+ }
+ else
+ {
+ if(MpIsrInfo->irqSource&0x10) break;
+ }
+
+ if(MpIsrInfo->irqSource&0x01) break;
+
+ if((i++) > 3000) break;
+ }
+
+ SetBitMask(ControlReg, 0x80); // stop timer now
+ WriteRC(ComIEnReg, 0); // disable all interrupts
+ WriteRC(ComIrqReg, 0x80); // clear all interrupt requests
+
+ WriteRC(CommandReg, PCD_IDLE); // reset command register
+
+ status = MpIsrInfo->status; // set status
+ if (MpIsrInfo->irqSource & 0x01) // if timeout expired - look at old error state
+ MpIsrInfo->errFlags |= MpIsrInfo->saveErrorState;
+ MpIsrInfo->errFlags &= validErrorFlags;
+ if (MpIsrInfo->errFlags) // error occured
+ {
+ if (MpIsrInfo->errFlags & 0x08) // collision detected
+ {
+ info->collPos = ReadRC(CollReg)&0x1F; // read collision position
+ status = MI_COLLERR;
+ }
+ else
+ {
+ if (MpIsrInfo->errFlags & 0x02) // parity error
+ {
+ status = MI_PARITYERR;
+ }
+ }
+ if (MpIsrInfo->errFlags & 0x01) // framing error
+ {
+ status = MI_FRAMINGERR;
+ }
+ else
+ if (MpIsrInfo->errFlags & 0x10) // FIFO overflow
+ {
+ FlushFIFO();
+ status = MI_OVFLERR;
+ }
+ else
+ if (MpIsrInfo->errFlags & 0x04) // CRC error
+ {
+ status = MI_CRCERR;
+ }
+ else
+ if (status == MI_OK)
+ status = MI_NY_IMPLEMENTED;
+ // key error occures always, because of
+ // missing crypto 1 keys loaded
+ }
+ // if the last command was TRANSCEIVE, the number of
+ // received bits must be calculated - even if an error occured
+ if (cmd == PCD_TRANSCEIVE || cmd == PCD_RECEIVE)
+ {
+ // number of bits in the last byte
+ lastBits = ReadRC(ControlReg) & 0x07;
+ if (lastBits)
+ info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
+ else
+ info->nBitsReceived += info->nBytesReceived * 8;
+ }
+ }
+
+ MpIsrInfo = 0; // reset interface variables for ISR
+ MpIsrOut = 0;
+ MpIsrIn = 0;
+
+ // restore the previous value for the FIFO water level
+ WriteRC(WaterLevelReg, waterLevelBackup);
+
+ return status;
+}
+
+//////////////////////////////////////////////////////////////////////
+// S E T D E F A U L T C O M M A T T R I B S
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PcdSetDefaultAttrib(void)
+{
+ WriteRC(TModeReg,0x8D);
+ WriteRC(TPrescalerReg,0x3E);
+ WriteRC(TReloadRegH,0x00);
+ WriteRC(TReloadRegL,0x64);
+ WriteRC(TxAskReg,0x40);
+ WriteRC(ModeReg,0x3D);
+ return MI_OK;
+}
+
+///////////////////////////////////////////////////////////////////////
+// M I F A R E A N T I C O L L I S I O N
+// for extended serial numbers
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccCascAnticoll (unsigned char select_code,
+ unsigned char bcnt,
+ unsigned char *snr)
+{
+ unsigned short status = MI_OK;
+ char snr_in[4]; // copy of the input parameter snr
+ char nbytes = 0; // how many bytes received
+ char nbits = 0; // how many bits received
+ char complete = 0; // complete snr recived
+ short i = 0;
+ char byteOffset = 0;
+ unsigned char snr_crc; // check byte calculation
+ unsigned char snr_check;
+ unsigned char dummyShift1; // dummy byte for snr shift
+ unsigned char dummyShift2; // dummy byte for snr shift
+
+ //************* Initialisierung ******************************
+ if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
+ {
+ PcdSetTmo(106);
+
+ memcpy(snr_in,snr,4);
+
+ ClearBitMask(Status2Reg, 0x08);
+ WriteRC(BitFramingReg, 0);
+ ClearBitMask(CollReg, 0x08);
+
+ //************** Anticollision Loop ***************************
+ complete=0;
+ while (!complete && (status == MI_OK) )
+ {
+ // if there is a communication problem on the RF interface, bcnt
+ // could be larger than 32 - folowing loops will be defective.
+ if (bcnt > 32)
+ {
+ status = MI_WRONG_PARAMETER_VALUE;
+ continue;
+ }
+ ResetInfo(MInfo);
+ MInfo.cmd = select_code; // pass command flag to ISR
+ MInfo.DisableDF = 1;
+ //WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
+ ClearBitMask(TxModeReg, 0x80);
+ ClearBitMask(RxModeReg, 0x80);
+ nbits = bcnt % 8; // remaining number of bits
+ if (nbits)
+ {
+ WriteRC(BitFramingReg, nbits << 4 | nbits); // TxLastBits/RxAlign auf nb_bi
+ nbytes = bcnt / 8 + 1;
+ // number of bytes known
+
+ // in order to solve an inconsistancy in the anticollision sequence
+ // (will be solved soon), the case of 7 bits has to be treated in a
+ // separate way
+ if (nbits == 7 )
+ {
+ MInfo.RxAlignWA = 1;
+ MInfo.nBitsReceived = 7; // set flag for 7 bit anticoll, which is evaluated
+ // in the ISRnBitsReceived
+ WriteRC(BitFramingReg, nbits); // reset RxAlign to zero
+ }
+ }
+ else
+ {
+ nbytes = bcnt / 8;
+ }
+
+ MSndBuffer[0] = select_code;
+ MSndBuffer[1] = 0x20 + ((bcnt/8) << 4) + nbits; //number of bytes send
+
+ for (i = 0; i < nbytes; i++) // Sende Buffer beschreiben
+ {
+ MSndBuffer[i + 2] = snr_in[i];
+ }
+ MInfo.nBytesToSend = 2 + nbytes;
+
+ status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
+ MSndBuffer,
+ MRcvBuffer,
+ &MInfo);
+
+ // in order to solve an inconsistancy in the anticollision sequence
+ // (will be solved soon), the case of 7 bits has to be treated in a
+ // separate way
+ if (MInfo.RxAlignWA)
+ {
+ // reorder received bits
+ dummyShift1 = 0x00;
+ for (i = 0; i < MInfo.nBytesReceived; i++)
+ {
+ dummyShift2 = MRcvBuffer[i];
+ MRcvBuffer[i] = (dummyShift1 >> (i+1)) | (MRcvBuffer[i] << (7-i));
+ dummyShift1 = dummyShift2;
+ }
+ MInfo.nBitsReceived -= MInfo.nBytesReceived; // subtract received parity bits
+ // recalculation of collision position
+ if ( MInfo.collPos ) MInfo.collPos += 7 - (MInfo.collPos + 6) / 9;
+ }
+
+ if ( status == MI_OK || status == MI_COLLERR) // no other occured
+ {
+
+ byteOffset = 0;
+ if ( nbits != 0 ) // last byte was not complete
+ {
+ snr_in[nbytes - 1] = snr_in[nbytes - 1] | MRcvBuffer[0];
+ byteOffset = 1;
+ }
+ for ( i =0; i < (4 - nbytes); i++)
+ {
+ snr_in[nbytes + i] = MRcvBuffer[i + byteOffset];
+ }
+ // R e s p o n s e P r o c e s s i n g
+ if ( MInfo.nBitsReceived != (40 - bcnt) ) // not 5 bytes answered
+ {
+ status = MI_BITCOUNTERR;
+ }
+ else
+ {
+ if (status != MI_COLLERR ) // no error and no collision
+ {
+ // SerCh check
+ snr_crc = snr_in[0] ^ snr_in[1] ^ snr_in[2] ^ snr_in[3];
+ snr_check = MRcvBuffer[MInfo.nBytesReceived - 1];
+ if (snr_crc != snr_check)
+ {
+ status = MI_SERNRERR;
+ }
+ else
+ {
+ complete = 1;
+ }
+ }
+ else // collision occured
+ {
+ bcnt = bcnt + MInfo.collPos - nbits;
+ status = MI_OK;
+ }
+ }
+ }
+ }
+ }
+ // transfer snr_in to snr - even in case of an error - for
+ // debugging reasons
+ memcpy(snr,snr_in,4);
+
+ //----------------------Einstellungen aus Initialisierung ruecksetzen
+ SetBitMask(CollReg, 0x80);
+
+ return status;
+}
+
+///////////////////////////////////////////////////////////////////////
+// M I F A R E C O M M O N R E Q U E S T
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccCommonRequest(unsigned char req_code,
+ unsigned char *atq)
+{
+ unsigned short status = MI_OK;
+
+ //************* initialize ******************************
+ if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
+ {
+
+ PcdSetTmo(60);
+
+ ClearBitMask(TxModeReg, 0x80); // RxCRC and TxCRC disable, parity enable
+ ClearBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+
+ ClearBitMask(Status2Reg, 0x08); // disable crypto 1 unit
+ WriteRC(BitFramingReg, 0x07); // set TxLastBits to 7
+ SetBitMask(TxControlReg,0x03);
+
+ ResetInfo(MInfo);
+ MSndBuffer[0] = req_code;
+ MInfo.nBytesToSend = 1;
+ MInfo.DisableDF = 1;
+ status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
+ MSndBuffer,
+ MRcvBuffer,
+ &MInfo);
+ if ((status == MI_OK) && (MInfo.nBitsReceived != 16)) // 2 bytes expected
+ {
+ status = MI_BITCOUNTERR;
+ }
+ if ((status == MI_COLLERR) && (MInfo.nBitsReceived == 16)) //
+ status = MI_OK; // all received tag-types are combined to the 16 bit
+
+ // in any case, copy received data to output - for debugging reasons
+ if (MInfo.nBytesReceived >= 2)
+ {
+ memcpy(atq,(unsigned char*)MRcvBuffer,2);
+ }
+ else
+ {
+ if (MInfo.nBytesReceived == 1)
+ atq[0] = MRcvBuffer[0];
+ else
+ atq[0] = 0x00;
+ atq[1] = 0x00;
+ }
+ }
+ return status;
+}
+///////////////////////////////////////////////////////////////////////
+// M I F A R E C A S C A D E D S E L E C T
+// for extended serial number
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccCascSelect(unsigned char select_code,
+ unsigned char *snr,
+ unsigned char *sak)
+{
+ unsigned short status = MI_OK;
+
+ if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
+ {
+ PcdSetTmo(106);
+
+ //WriteRC(RegChannelRedundancy,0x0F); // RxCRC,TxCRC, Parity enable
+ //ClearBitMask(RegControl,0x08); // disable crypto 1 unit
+
+ //************* Cmd Sequence **********************************
+ ResetInfo(MInfo);
+ MSndBuffer[0] = select_code;
+ MSndBuffer[1] = 0x70; // number of bytes send
+
+ memcpy((unsigned char*)MSndBuffer + 2,snr,4);
+ MSndBuffer[6] = MSndBuffer[2]
+ ^ MSndBuffer[3]
+ ^ MSndBuffer[4]
+ ^ MSndBuffer[5];
+ MInfo.nBytesToSend = 7;
+ MInfo.DisableDF = 1;
+
+ WriteRC(ModeReg, 0x01);
+ SetBitMask(TxModeReg, 0x80);
+ SetBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+ ClearBitMask(Status2Reg, 0x08);
+ status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
+ MSndBuffer,
+ MRcvBuffer,
+ &MInfo);
+
+ *sak = 0;
+ if (status == MI_OK) // no timeout occured
+ {
+ if (MInfo.nBitsReceived != 8) // last byte is not complete
+ {
+ status = MI_BITCOUNTERR;
+ }
+ else
+ {
+ memcpy(MLastSelectedSnr,snr,4);
+ }
+ }
+ // copy received data in any case - for debugging reasons
+ *sak = MRcvBuffer[0];
+ }
+ return status;
+}
+
+///////////////////////////////////////////////////////////////////////
+// M I F A R E P I C C A C T I V A T I O N S E Q E N C E
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccActivateIdle(unsigned char br,
+ unsigned char *atq,
+ unsigned char *sak,
+ unsigned char *uid,
+ unsigned char *uid_len)
+{
+ unsigned char cascade_level;
+ unsigned char sel_code;
+ unsigned char uid_index;
+ unsigned short status = MI_OK;
+ unsigned char cmdASEL;
+
+ *uid_len = 0;
+
+ //call activation with def. divs
+ status = Mf500PcdSetDefaultAttrib();
+ if (status == MI_OK)
+ {
+ status = Mf500PiccCommonRequest(PICC_REQIDL,atq);
+ }
+ if (status == MI_OK)
+ {
+ if((atq[0] & 0x1F) == 0x00) // check lower 5 bits, for tag-type
+ // all tags within this 5 bits have to
+ // provide a bitwise anticollision
+ {
+ status = MI_NOBITWISEANTICOLL;
+ }
+ }
+ if (status == MI_OK)
+ {
+ //Get UID in 1 - 3 levels (standard, [double], [triple] )
+ //-------
+ switch(br)
+ {
+ case 0: cmdASEL = PICC_ANTICOLL1; break;
+ case 1: cmdASEL = PICC_ANTICOLL11; break;
+ case 2: cmdASEL = PICC_ANTICOLL12; break;
+ case 3: cmdASEL = PICC_ANTICOLL13; break;
+ default:
+ status = MI_BAUDRATE_NOT_SUPPORTED; break;
+ }
+ }
+ if (status == MI_OK)
+ {
+ cascade_level = 0;
+ uid_index = 0;
+ do
+ {
+ //Select code depends on cascade level
+ sel_code = cmdASEL + (2 * cascade_level);
+ cmdASEL = PICC_ANTICOLL1; // reset anticollistion level for calculation
+ //ANTICOLLISION
+ status = Mf500PiccCascAnticoll(sel_code, 0, &uid[uid_index]);
+ //SELECT
+ if (status == MI_OK)
+ {
+ status = Mf500PiccCascSelect(sel_code, &uid[uid_index], sak);
+ if (status == MI_OK)
+ {
+ cascade_level++;
+
+ //we differ cascaded and uncascaded UIDs
+ if (*sak & 0x04) // if cascaded, bit 2 is set in answer to select
+ {
+ //this UID is cascaded, remove the cascaded tag that is
+ //0x88 as first of the 4 byte received
+ memmove(&uid[uid_index], &uid[uid_index + 1], 3);
+ uid_index += 3;
+ *uid_len += 3;
+ }
+ else
+ {
+ //this UID is not cascaded -> the length is 4 bytes
+ uid_index += 4;
+ *uid_len += 4;
+ }
+ }
+ }
+ }
+ while((status == MI_OK) // error status
+ && (*sak & 0x04) // no further cascade level
+ && (cascade_level < 3)); // highest cascade level is reached
+ }
+ if (status == MI_OK)
+ {
+ //Exit function, if cascade level is triple and sak indicates another
+ //cascase level.
+ if ((cascade_level == 3) && (*sak & 0x04))
+ {
+ *uid_len = 0;
+ status = MI_CASCLEVEX;
+ }
+ //Mf500PcdSetAttrib(br,br);
+ }
+ return (status);
+}
+
+///////////////////////////////////////////////////////////////////////
+// E X C H A N G E B Y T E S T R E A M
+///////////////////////////////////////////////////////////////////////
+unsigned short ExchangeByteStream(unsigned char Cmd,
+ unsigned char *send_data,
+ unsigned short send_bytelen,
+ unsigned char *rec_data,
+ unsigned short *rec_bytelen)
+{
+ unsigned short status = MI_OK;
+
+ FlushFIFO(); // empty FIFO
+ ResetInfo(MInfo); // initialise ISR Info structure
+
+ if (send_bytelen > 0)
+ {
+ memcpy((unsigned char *)MSndBuffer,send_data,send_bytelen); // write n bytes
+ MInfo.nBytesToSend = send_bytelen;
+ // write load command
+ status = PcdSingleResponseCmd(Cmd,
+ MSndBuffer,
+ MRcvBuffer,
+ &MInfo);
+ *rec_bytelen = MInfo.nBytesReceived;
+ // copy data to output, even in case of an error
+ if (*rec_bytelen)
+ {
+ memcpy(rec_data,(unsigned char *)MRcvBuffer,*rec_bytelen);
+ }
+ }
+ else
+ {
+ status = MI_WRONG_PARAMETER_VALUE;
+ }
+ return status;
+}
+
+//////////////////////////////////////////////////////////////////////
+// P I C C E X C H A N G E B L O C K
+///////////////////////////////////////////////////////////////////////
+unsigned short Mf500PiccExchangeBlock(unsigned char *send_data,
+ unsigned short send_bytelen,
+ unsigned char *rec_data,
+ unsigned short *rec_bytelen,
+ unsigned char append_crc,
+ unsigned long timeout )
+{
+ char status = MI_OK;
+
+ if (append_crc)
+ {
+ // RxCRC and TxCRC enable, parity enable
+ WriteRC(ModeReg, 0x01);
+ SetBitMask(TxModeReg, 0x80);
+ SetBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+ WriteRC(ModeReg, 0x01);
+ send_bytelen -= 2;
+ }
+ else
+ {
+ // RxCRC and TxCRC disable, parity enable
+ ClearBitMask(TxModeReg, 0x80);
+ ClearBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+ }
+
+ PcdSetTmo(timeout);
+
+ status = ExchangeByteStream(PCD_TRANSCEIVE,
+ send_data,
+ send_bytelen,
+ rec_data,
+ rec_bytelen);
+ // even if an error occured, the data should be
+ // returned - for debugging reasons
+
+ if (append_crc)
+ {
+ *rec_bytelen += 2; // for two CRC bytes
+ rec_data[*rec_bytelen - 2] = 0x00;
+ rec_data[*rec_bytelen - 1] = 0x00;
+ }
+
+ return status;
+}
+
+#endif
+
diff --git a/icc_apdu_lib/MfRcSPI.c b/icc_apdu_lib/MfRcSPI.c
new file mode 100644
index 0000000..d7c200c
--- /dev/null
+++ b/icc_apdu_lib/MfRcSPI.c
@@ -0,0 +1,108 @@
+#include "spi.h"
+
+#define Dummy_Byte 0xA5
+
+#define MFRC500_CS_LOW() SPI_SELECT_CH1()
+#define MFRC500_CS_HIGH() SPI_DESELECT_CH1()
+
+#define MFRC500_RST_LOW() GPIO_ResetBits(GPIOC, GPIO_Pin_6)
+#define MFRC500_RST_HIGH() GPIO_SetBits(GPIOC, GPIO_Pin_6)
+
+/*
+**************************************************************************************************************
+* ÑÓ Ê± º¯ Êý uS
+* ×¢ Ò⣺ ¾«¶ÈÎÊÌâ
+**************************************************************************************************************
+*/
+ void HW_SleepUs(uint16_t us)
+{
+ uint32_t i;
+
+ for( i = 0; i < 6 * us; i++);
+}
+
+/*
+**************************************************************************************************************
+* ÑÓ Ê± º¯ Êý mS
+* ×¢ Ò⣺ ¾«¶ÈÎÊÌâ
+**************************************************************************************************************
+*/
+void HW_SleepMs(uint16_t ms)
+{
+ uint32_t i;
+
+ for( i = 0; i < 3361 * ms; i++ );
+}
+
+/*
+**************************************************************************************************************
+* RF SPI Åä Öà ³õ ʼ »¯
+*
+**************************************************************************************************************
+*/
+void HW_SPI_RF_CfgInit(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+ MFRC500_RST_HIGH();
+ spi_init();
+}
+
+uint8_t spi_rc500_send_byte(uint8_t byte)
+{
+ return spi_transive(byte, 100);
+}
+
+
+/*
+**************************************************************************************************************
+* P C D ¶Á Ò» ¸ö ×Ö ½Ú
+*
+* Ò» °ã ¶Á
+*
+**************************************************************************************************************
+*/
+uint8_t ReadRawRC(uint8_t addr)
+{
+ u8 i;
+
+ addr = ((addr<<1)|0x80)&0xfe;
+ MFRC500_CS_LOW();
+ spi_rc500_send_byte(addr);
+ i = spi_rc500_send_byte(Dummy_Byte);
+ MFRC500_CS_HIGH();
+ return i;
+}
+
+/*
+**************************************************************************************************************
+* P C D д Ò» ¸ö ×Ö ½Ú
+*
+* Ò» °ã д
+*
+**************************************************************************************************************
+*/
+void WriteRawRC(uint8_t value, uint8_t addr)
+{
+ addr = (addr << 1) & 0x7e;
+ MFRC500_CS_LOW();
+ spi_rc500_send_byte(addr);
+ spi_rc500_send_byte(value);
+ MFRC500_CS_HIGH();
+}
+
+void MFRC500_RstSet(void)
+{
+ MFRC500_RST_HIGH();
+}
+
+void MFRC500_RstClr(void)
+{
+ MFRC500_RST_LOW();
+}
+
diff --git a/icc_apdu_lib/Mifare_One_HW_LIB.H b/icc_apdu_lib/Mifare_One_HW_LIB.H
new file mode 100644
index 0000000..0ab6ba0
--- /dev/null
+++ b/icc_apdu_lib/Mifare_One_HW_LIB.H
@@ -0,0 +1,423 @@
+/*
+**************************************************************************************************************
+* Mifare One Ó² ¼þ µ× ²ã Çý ¶¯ ¿â
+*
+* _____Ó² ¼þ µ× ²ã Çý ¶¯_____
+*
+* Ãè Êö£º Íê³ÉMifare One¿¨µÄÓ²¼þµ×²ã²Ù×÷£»
+*
+* Åä Öãº
+* CPU :
+* ÍâʱÖÓ :
+* CPUÔËÐÐʱÖÓ :
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.50Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ ³ýReadRC£¬WriteRCº¯ÊýÍ⣬ÆäËüM1¿¨²Ù×÷º¯Êý¶¼ÓÐSPI¶Ë¿ÚÅäÖã¬ËùÒÔÆäËüµØ·½µ÷ÓÃÕâЩº¯Êýʱ£¬¾Í²»ÓýøÐÐ
+* SPI¶Ë¿ÚÅäÖòÙ×÷(HW_SPI_RF_CfgInit)¡£
+*
+* ¿â Ãû£º Mifare_One_HW_V2.0.LIB
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º 2.0
+*
+* ÈÕ ÆÚ£º 2009-05-31
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+
+#ifndef __Mifare_One_HW_LIB_H__
+#define __Mifare_One_HW_LIB_H__
+
+#include "PICCCmdConst.h"
+#include "MFRC500.h"
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+
+// RC500µÄ¼Ä´æÆ÷¶¨ÒåºÍ³£Êý¶¨Òå
+ #define MI_OK (0)
+
+ #define BUFFER_SIZE_RFCard 64
+
+/* SPIÇý¶¯Æ÷ÄÚ²¿×´Ì¬ */
+ #define IDLE 0x00
+ #define BUSY 0x01
+ #define ERROR 0x02
+
+/* ¿¨½Ó¿ÚSPI״̬·µ»ØÖµ */
+ #define RFCI_BUSY 0x00
+ #define RFCI_OK 0x01
+ #define RFCI_ERROR 0x02
+
+//RF¿¨¿ØÖÆÐźÅ
+ #define RFC_RESET (1<<9) /* PA9 RF¿¨¸´Î»¿ØÖÆÐźÅ(½ÚÄÜ¿ØÖÆ) */
+
+/* ¼Ä´æÆ÷¶¨Òå */
+ #define RegPage 0x00 //!< Page Select Register
+ #define RegCommand 0x01 //!< Command Register
+ #define RegFIFOData 0x02 //!< FiFo Register
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+ typedef struct _RFIDesc
+ {
+ volatile unsigned char state;
+ unsigned char command[2];
+ unsigned char dataBuffer[2];
+ } RFIDesc, *pRFIDesc;
+
+ extern RFIDesc gRFIDesc;
+
+
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+//SPI.C
+/*
+**************************************************************************************************************
+* ÑÓ Ê± º¯ Êý uS
+* Thumbģʽ+½»²æģʽ
+*
+* ×¢ Ò⣺ÔËÐÐģʽ²»Ò»Ñù£¬Èí¼þÑÓʱ²»Ò»Ñù¡£
+**************************************************************************************************************
+*/
+ extern void HW_SleepUs( unsigned short us ); /* uSÈí¼þÑÓʱº¯Êý */
+/*
+**************************************************************************************************************
+* ÑÓ Ê± º¯ Êý mS
+* Thumbģʽ+½»²æģʽ
+**************************************************************************************************************
+*/
+ extern void HW_SleepMs( unsigned short ms ); /* mSÈí¼þÑÓʱº¯Êý */
+/*
+**************************************************************************************************************
+* RF SPI Åä Öà ³õ ʼ »¯
+*
+**************************************************************************************************************
+*/
+ extern void HW_SPI_RF_CfgInit( void ); /* SPI RF ÅäÖóõʼ»¯ */
+/*
+**************************************************************************************************************
+* PCD µÈ ´ý ½Ó ÊÕ
+* ÄÚ²¿µ÷ÓÃ
+**************************************************************************************************************
+*/
+ extern unsigned char HW_RFI_WaitReady( unsigned int timeout );
+/*
+**************************************************************************************************************
+* P C D ¶Á Ò» ¸ö ×Ö ½Ú
+*
+*
+**************************************************************************************************************
+*/
+ extern unsigned char ReadRC( unsigned char addr );
+/*
+**************************************************************************************************************
+* P C D д Ò» ¸ö ×Ö ½Ú
+*
+*
+**************************************************************************************************************
+*/
+ extern void WriteRC( unsigned char value, unsigned char addr );
+
+//GetM1Sn.C
+/*
+**************************************************************************************************************
+* ¹¦ ÄÜ£º È¡µÃ¿¨ÐòÁкÅ
+* Êä ³ö£º unsigned char *pSN - ¿¨ÐòÁкÅ
+* ·µ»ØÖµ£º 0³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char GetM1SN( unsigned char *pSN );
+
+//M1_Basic.C
+/*
+**************************************************************************************************************
+* Ö´ÐÐÃüÁîÇ°É趨ÏàÓ¦¼Ä´æÆ÷ ÄÚ²¿µ÷ÓÃ
+**************************************************************************************************************
+*/
+ extern void RcRegRst( void );
+/*
+**************************************************************************************************************
+* È¡RC500ÃüÁî½á¹û
+* cmd : RC530ÃüÁî×Ö
+* RcvBuff : ÃüÁîÕýÈ·Ö´ÐкóÊÕµ½µÄÊý¾Ý
+* ·µ»ØÖµ £ºÃüÁîÖ´ÐÐÇé¿ö
+* B: ÊÇ·ñ³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char RcComResult(unsigned char cmd, unsigned char *RcvBuff);
+/*
+**************************************************************************************************************
+* ¼ÓÔØϵͳÃÜÂëµ½RC530 KeyBuffer
+* ²ÎÊý£º RawCode - Òª¼ÓÔصÄ6×Ö½ÚÃÜÂëµÄÖ¸Õ루´æÓÚIDATAÇø£©
+* ·µ»Ø£º 0 - ²Ù×÷³É¹¦
+* !0 - ²Ù×÷ʧ°Ü
+**************************************************************************************************************
+*/
+ extern unsigned char Load_RAM ( unsigned char * RawCode );
+/*
+**************************************************************************************************************
+*
+* ¹¦ ÄÜ £º Ñ°¿¨
+* ²Î Êý : RequestMode : Ñ°¿¨Ä£Ê½£¬ÎªIDLE »ò ALL
+* atq : ¿¨Æ¬µÄÀàÐÍ ÔÝÎÞÓÃ
+* ·µ »Ø Öµ£º µ±Îª0x00 ʱ±íʾÓп¨£¬·ñÔòÎÞ¿¨
+**************************************************************************************************************
+*/
+ extern unsigned char M1_Request( unsigned char RequestMode, unsigned char * atq );
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ£º ¿¹³åÍ»²âÊÔ
+* ²ÎÊý: Bcnt : ¿¹³åÍ»¿¨ÐòÁкÅÔ¤ÖÃλÊý
+* Snr £ºÔ¤ÖûòµÃµ½µÄ¿¨µÄÐòÁкÅ
+* ·µ»ØÖµ£ºµ±Îª0x00 ʱ±íʾÕýÈ·µÃµ½¿¨µÄÐòÁкţ¬·ñÔòδÕýÈ·µÃµ½
+**************************************************************************************************************
+*/
+ extern unsigned char M1_Anti(unsigned char Bcnt, unsigned char *Snr);
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ£º Ñ¡¿¨
+* ²ÎÊý: Snr £º¿¨µÄÐòÁкÅ
+* ·µ»ØÖµ£ºµ±Îª0x00 ʱ±íʾÕýÈ·Ñ¡¿¨³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char M1_Select( unsigned char *Snr );
+/*
+**************************************************************************************************************
+* Auth_Block £¨Í¨¹ý¿éºÅ½øÐÐУÑ飬֧³ÖS50£¬S70¿¨£©
+* »òÄÜ£º УÑé
+* ²ÎÊý: AuthMode :AÃÜÂë »ò BÃÜÂë
+* Block :¶Áд¿éºÅ
+* Snr :¿¨ÐòÁкÅ
+* ·µ»ØÖµ£º00±íʾÃÜÂëÕýÈ·
+**************************************************************************************************************
+*/
+ extern unsigned char M1_AuthBlk( unsigned char AuthMode, unsigned char *Snr, unsigned char Block, unsigned char *key );
+/*
+**************************************************************************************************************
+* RC530¼Ä´æÆ÷³õʼ»¯
+**************************************************************************************************************
+*/
+ extern unsigned char RCConfig(void);
+/*
+**************************************************************************************************************
+* RC530Éϵ縴λ
+* 1. ½«RC530´Óµôµçģʽ»½ÐÑ£¬²¢Íê³É³õʼ»¯
+* 2. »ò½«RC530ÖØи´Î»
+**************************************************************************************************************
+*/
+ extern unsigned char M1_RCReset(void);
+
+//M1_BlkRead.C
+/*
+**************************************************************************************************************
+*¹¦ÄÜ£º Mifare¿¨¿é¶Á(º¬Ñ°¿¨, Ñ¡¿¨, УÑé, ¶Á¿¨(Ò»¿é), ¿É¹©Ñ¡Ôñ)£º
+*ÊäÈ룺 unsigned char *pSN - ¿¨ÐòÁкÅ
+* unsigned char Mode - ( ¸ù¾Ý¶¨ÒåµÄ³£Á¿±í½øÐÐ"»ò"×éºÏ )
+* bit0 - AÃÜÂë»òBÃÜÂë( 0 - A 1 - B)
+* bit2 - 0 - Ñ°¿¨ 1 - ²»Ñ°¿¨
+* bit3 - 0 - ²»Ð£ÑéÃÜÂë 1 - ҪУÑéÃÜÂë
+* unsigned char Block - Òª¶ÁµÄ¿éºÅ
+* unsigned char *pKey - ÉÈÇø¶ÁдÃÜÂë
+*
+*Êä³ö£º unsigned char *pBuffer - ¶Á³öµÄ16×Ö½ÚÊý¾Ý
+*·µ»ØÖµ£ºµ±Îª0x00 ʱÕýÈ·¶Á³ö
+**************************************************************************************************************
+*/
+ extern unsigned char M1_BlkRead( unsigned char Mode, unsigned char Block, unsigned char *pSN, unsigned char * pBuffer, unsigned char *pKey );
+
+//M1_BlkWrite.C
+/*
+**************************************************************************************************************
+*¹¦ÄÜ£º Mifare¿¨¿éд(º¬Ñ°¿¨, Ñ¡¿¨, УÑé, ¶Á¿¨(Ò»¿é), ¿É¹©Ñ¡Ôñ)£º
+*ÊäÈ룺 unsigned char *pSN - ¿¨ÐòÁкÅ
+* unsigned char Mode - ( ¸ù¾Ý¶¨ÒåµÄ³£Á¿±í½øÐÐ"»ò"×éºÏ )
+* bit0 - AÃÜÂë»òBÃÜÂë( 0 - A 1 - B)
+* bit2 - 0 - Ñ°¿¨ 1 - ²»Ñ°¿¨
+* bit3 - 0 - ²»Ð£ÑéÃÜÂë 1 - ҪУÑéÃÜÂë
+* unsigned char Block - Òª¶ÁµÄ¿éºÅ
+* unsigned char *pKey - ÉÈÇø¶ÁдÃÜÂë
+* unsigned char *pBuffer - ҪдÈëµÄ16×Ö½ÚÊý¾Ý
+*·µ»ØÖµ£ºµ±Îª0x00 ʱÕýÈ·¶Á³ö
+**************************************************************************************************************
+*/
+ extern unsigned char M1_BlkWrite( unsigned char Mode, unsigned char Block, unsigned char *pSN, unsigned char * pBuffer, unsigned char *pKey );
+
+//M1_E2Read.C
+/*
+**************************************************************************************************************
+* M1_E2Read ¶ÁÈ¡RC500µÄE2ÖеÄÊý¾Ý
+* Addr :E2ÆðʼµØÖ·(Addr < 80H )
+* length :ÒªÇó¶ÁÈ¡µÄ×Ö½ÚÊý( СÓÚµÈÓÚ16 )
+* pBuffer :¶Á³öÊý¾ÝµÄ»º³åÇø
+* ·µ»ØÖµ £º0±íʾд³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char M1_E2Read( unsigned char Addr, unsigned char length, unsigned char * pBuffer);
+
+//M1_E2WRITE.C
+/*
+**************************************************************************************************************
+* M1_E2Write ½«Êý¾ÝдÈëRC500µÄE2ÖÐ
+* Addr :E2ÆðʼµØÖ·( 0x10 <=Addr < 0x1ff )
+* length :ÒªÇóдÈëµÄ×Ö½ÚÊý( СÓÚµÈÓÚ16 )
+* pBuffer :ҪдÈëÊý¾ÝµÄ»º³åÇø
+* ·µ»ØÖµ £º0±íʾд³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char M1_E2Write( unsigned int Addr, unsigned char length, unsigned char * pBuffer);
+
+//M1_HardPwrDwn.C
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ£º ¶Á¿¨°åÓ²¼þµôµç£º
+* º¯ÊýÔÐÍ£º void HardPwrDwn() ÔÝûÓÐд
+* ²ÎÊý£º ÎÞ
+* ·µ»ØÖµ£º ÎÞ
+* ˵Ã÷£º
+* ½«¶Á¿¨°åµÄRF¡ªRST¿ØÖÆÏßÖÃΪ¸ßµçƽ£¬¶Á¿¨°å´¦ÓÚÓ²¼þµôµç״̬£¨µçÔ´Õý³£Ìṩ£©¡£
+**************************************************************************************************************
+*/
+ extern void M1_HardPwrDwn( void );
+
+//M1_PCDSn.C
+/*
+**************************************************************************************************************
+* M1_PCDSn ¶ÁÈ¡RC500µÈ¶Á¿¨Ð¾Æ¬µÄÐòÁкÅ
+* pSn :ÐòÁкŻº³åÇø
+* ·µ»ØÖµ £º0±íʾд³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char M1_PCDSn( unsigned char * pBuffer);
+
+//M1_RadioOff.C
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ£º ¶Á¿¨°å¶Á¿¨Ð¾Æ¬ÉäƵ¹Ø±Õ£º
+* º¯ÊýÔÐÍ£º void M1_RadioOff()
+* ²ÎÊý£º ÎÞ
+* ·µ»ØÖµ£º ÎÞ
+* ˵Ã÷£º
+* ½«¶Á¿¨°åÉϵĶÁ¿¨Ð¾Æ¬µÄÉäƵ·¢Ë͹صô,½µµÍ¹¦ºÄºÍ¶ÔÍâ¸ÉÈÅ
+* ´Ëʱ¶Á¿¨Ð¾Æ¬»¹ÔÚ¹¤×÷.
+**************************************************************************************************************
+*/
+ extern void M1_RadioOff( void );
+
+//M1_RadioOn.C
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ£º ¶Á¿¨°å¶Á¿¨Ð¾Æ¬ÉäƵ´ò¿ª£º
+* º¯ÊýÔÐÍ£º void M1_RadioOn()
+* ²ÎÊý£º ÎÞ
+* ·µ»ØÖµ£º ÎÞ
+* ˵Ã÷£º
+* ½«¶Á¿¨°åÉϵĶÁ¿¨Ð¾Æ¬µÄÉäƵ·¢ËÍ´ò¿ª
+*
+* M1_RadioOn() ºÍ M1_RadioOff()ÊÇÒ»¶Ôº¯Êý,ÓÃÔÚÒ»°ãÇé¿öϵĽÚÄܺͽµµÍÉäƵ¸ÉÈÅÉÏ.
+**************************************************************************************************************
+*/
+ extern void M1_RadioOn( void );
+
+//M1_RawRead.C
+/*
+**************************************************************************************************************
+* Fread ¶Á¿éÊý¾Ý
+* Block :¶Á¿éºÅ
+* ReadBuffer :¶Á³öµÄÊý¾ÝµÄ»º³åÇø£¬ÔÚIDATAÇø
+* ·µ»ØÖµ £º0±íʾ¶Á³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char M1_Read(unsigned char Block, unsigned char * ReadBuffer);
+
+//M1_rawWrite.C
+/*
+**************************************************************************************************************
+* Fwrite д¿éÊý¾Ý
+* Block :д¿éºÅ
+* ReadBuffer :ҪдÊý¾ÝµÄ»º³åÇø£¬ÔÚIDATAÇø
+* ·µ»ØÖµ £º0±íʾд³É¹¦
+**************************************************************************************************************
+*/
+ extern unsigned char M1_Write( unsigned char Block, unsigned char * WriteBuffer);
+
+//M1_Timer.C
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ: Æô¶¯Mifare¶Á¿¨Çý¶¯µÄ³¬Ê±¶¨Ê±Æ÷ ÔÝûÓÐд
+**************************************************************************************************************
+*/
+ extern void M1TimerToStart( void );
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ: Í£Ö¹Mifare¶Á¿¨Çý¶¯µÄ³¬Ê±¶¨Ê±Æ÷ ÔÝûÓÐд
+**************************************************************************************************************
+*/
+ extern void M1TimerToStop( void );
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ: È¡µÃMifare¶Á¿¨Çý¶¯µÄ³¬Ê±¶¨Ê±Æ÷״̬ ÔÝûÓÐд
+* ·µ»ØÖµ: 1 - ³¬Ê±¶¨Ê±Æ÷Òç³ö( ³¬Ê± )
+* 0 - ³¬Ê±¶¨Ê±Æ÷δÒç³ö
+**************************************************************************************************************
+*/
+ extern unsigned char M1TimerToSta( void );
+
+//M1_TranSta.C
+/*
+**************************************************************************************************************
+* ¹¦ÄÜ£º ¼ì²é¶Á¿¨Ð¾Æ¬ÊÇ·ñ·¢ÉäÕý³£
+* º¯ÊýÔÐÍ£º unsigned char M1_TranSta()
+* ²ÎÊý£º ÎÞ
+* ·µ»ØÖµ£º 1 - Ôز¨Î´·¢Éä
+* 0 - Ôز¨·¢Éä
+**************************************************************************************************************
+*/
+ extern unsigned char M1_TranSta( void );
+//
+
+
+/*
+**************************************************************************************************************
+* Öµ¿éµÄ¼Ó¼õ²Ù×÷: Íê³ÉBlockÖµ¿éµÄ¼Ó¡¢¼õ¡¢Restore£¬²¢½«Öµ´«ÈëTranBlockÖÐ
+* cmd £º¼Ó(PICC_ADD)¡¢¼õ(PICC_SUB)¡¢Restore(PICC_RESTORE)ÃüÁî
+* Block :ÔÖµ¿éºÅ
+* Value :ËÄ×Ö½ÚÖµÇø£¨Õý£©
+* TranBlock £ºÖµ´«ÈëµÄ¿éºÅ
+* ·µ»ØÖµ £º0±íʾ¶Á³É¹¦£¬ÆäËüΪ´íÎó´úÂë
+**************************************************************************************************************
+*/
+
+ extern unsigned char M1_Value( unsigned char cmd, unsigned char Block, unsigned char * Value, unsigned char TranBlock );
+
+/***************************************************************
+ Halt
+ ¹¦ÄÜ£º ÖÕÖ¹¿¨
+ ²ÎÊý: ÎÞ
+ ·µ»ØÖµ£ºµ±Îª0x00 ʱ±íʾ¿¨ÖÕÖ¹³É¹¦
+****************************************************************/
+extern unsigned char M1_Halt( void );
+
+extern unsigned char PICC_TclCheckRFRounge( void ) ;
+
+
+#endif
+
+
diff --git a/icc_apdu_lib/PICCCmdConst.h b/icc_apdu_lib/PICCCmdConst.h
new file mode 100644
index 0000000..8dbfba0
--- /dev/null
+++ b/icc_apdu_lib/PICCCmdConst.h
@@ -0,0 +1,54 @@
+/*
+* Copyright (c), Philips Semiconductors Gratkorn / Austria
+*
+* (C)PHILIPS Electronics N.V.2000
+* All rights are reserved. Reproduction in whole or in part is
+* prohibited without the written consent of the copyright owner.
+* Philips reserves the right to make changes without notice at any time.
+* Philips makes no warranty, expressed, implied or statutory, including but
+* not limited to any implied warranty of merchantability or fitness for any
+*particular purpose, or that the use will not infringe any third party patent,
+* copyright or trademark. Philips must not be liable for any loss or damage
+* arising from its use.
+*/
+
+/*! \file PICCCmdConst.h
+*
+* Projekt: MF EV X00 Firmware
+*
+* $Workfile:: PICCCmdConst.h $
+* $Modtime:: 5.12.01 6:52 $
+* $Author:: Hb $
+* $Revision:: 1 $
+*
+*/
+#ifndef PICCCMDCONST_H
+#define PICCCMDCONST_H
+
+
+/** \name PICC Commands
+* \ingroup mifare
+* Commands which are handled by the tag
+*
+* Each tag command is written to the reader IC and transfered via RF
+*/
+#define PICC_REQIDL 0x26 //!< request idle
+#define PICC_REQALL 0x52 //!< request all
+#define PICC_ANTICOLL1 0x93 //!< anticollision level 1 106 kBaud
+#define PICC_ANTICOLL11 0x92 //!< anticollision level 1 212 kBaud
+#define PICC_ANTICOLL12 0x94 //!< anticollision level 1 424 kBaud
+#define PICC_ANTICOLL13 0x98 //!< anticollision level 1 848 kBaud
+#define PICC_ANTICOLL2 0x95 //!< anticollision level 2
+#define PICC_ANTICOLL3 0x97 //!< anticollision level 3
+#define PICC_AUTHENT1A 0x60 //!< authentication using key A
+#define PICC_AUTHENT1B 0x61 //!< authentication using key B
+#define PICC_READ16 0x30 //!< read 16 byte block
+#define PICC_WRITE16 0xA0 //!< write 16 byte block
+#define PICC_WRITE4 0xA2 //!< write 4 byte block
+#define PICC_DECREMENT 0xC0 //!< decrement value
+#define PICC_INCREMENT 0xC1 //!< increment value
+#define PICC_RESTORE 0xC2 //!< restore command code
+#define PICC_TRANSFER 0xB0 //!< transfer command code
+#define PICC_HALT 0x50 //!< halt
+
+#endif // PICCCMDCONST_H
diff --git a/icc_apdu_lib/RICReg.H b/icc_apdu_lib/RICReg.H
new file mode 100644
index 0000000..f083a3a
--- /dev/null
+++ b/icc_apdu_lib/RICReg.H
@@ -0,0 +1,115 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c), Philips Semiconductors Gratkorn
+//
+// (C)PHILIPS Electronics N.V. 2000
+// All rights are reserved.
+// Philips reserves the right to make changes without notice at any time.
+// Philips makes no warranty, expressed, implied or statutory, including but
+// not limited to any implied warranty of merchantibility or fitness for any
+//particular purpose, or that the use will not infringe any third party patent,
+// copyright or trademark. Philips must not be liable for any loss or damage
+// arising from its use.
+//////////////////////////////////////////////////////////////////////////////
+/*! \file RICReg.h
+*
+* Register Setting of the reader IC
+*/
+#ifndef RICREG_H
+#define RICREG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//CV520 regs
+// PAGE 0
+#define RFU00 0x00
+#define CommandReg 0x01
+#define ComIEnReg 0x02
+#define DivlEnReg 0x03
+#define ComIrqReg 0x04
+#define DivIrqReg 0x05
+#define ErrorReg 0x06
+#define Status1Reg 0x07
+#define Status2Reg 0x08
+#define FIFODataReg 0x09
+#define FIFOLevelReg 0x0A
+#define WaterLevelReg 0x0B
+#define ControlReg 0x0C
+#define BitFramingReg 0x0D
+#define CollReg 0x0E
+#define RFU0F 0x0F
+/*PAGE 1 */
+#define RFU10 0x10
+#define ModeReg 0x11
+#define TxModeReg 0x12
+#define RxModeReg 0x13
+#define TxControlReg 0x14
+#define TxAskReg 0x15
+#define TxSelReg 0x16
+#define RxSelReg 0x17
+#define RxThresholdReg 0x18
+#define DemodReg 0x19
+#define RFU1A 0x1A
+#define RFU1B 0x1B
+#define MifareReg 0x1C
+#define RFU1D 0x1D
+#define RFU1E 0x1E
+#define SerialSpeedReg 0x1F
+/*PAGE 2 */
+#define RFU20 0x20
+#define CRCResultRegM 0x21
+#define CRCResultRegL 0x22
+#define RFU23 0x23
+#define ModWidthReg 0x24
+#define RFU25 0x25
+#define RFCfgReg 0x26
+#define GsNReg 0x27
+#define CWGsCfgReg 0x28
+#define ModGsCfgReg 0x29
+#define TModeReg 0x2A
+#define TPrescalerReg 0x2B
+#define TReloadRegH 0x2C
+#define TReloadRegL 0x2D
+#define TCounterValueRegH 0x2E
+#define TCounterValueRegL 0x2F
+/* PAGE 3 */
+#define RFU30 0x30
+#define TestSel1Reg 0x31
+#define TestSel2Reg 0x32
+#define TestPinEnReg 0x33
+#define TestPinValueReg 0x34
+#define TestBusReg 0x35
+#define AutoTestReg 0x36
+#define VersionReg 0x37
+#define AnalogTestReg 0x38
+#define TestDAC1Reg 0x39
+#define TestDAC2Reg 0x3A
+#define TestADCReg 0x3B
+#define RFU3C 0x3C
+#define RFU3D 0x3D
+#define RFU3E 0x3E
+#define RFU3F 0x3F
+
+
+#define DEF_FIFO_LENGTH 64 //!< default FIFO size
+
+// P C D - C O M M A N D S
+#define PCD_IDLE 0x00 //È¡Ïûµ±Ç°ÃüÁî
+#define PCD_AUTHENT 0x0E //ÑéÖ¤ÃÜÔ¿ MIFARE ±ê×¼ÈÏÖ¤
+#define PCD_RECEIVE 0x08 //½ÓÊÕÊý¾Ý
+#define PCD_TRANSMIT 0x04 //·¢ËÍÊý¾Ý
+#define PCD_TRANSCEIVE 0x0C //·¢ËͲ¢½ÓÊÕÊý¾Ý
+#define PCD_RESETPHASE 0x0F //¸´Î»
+#define PCD_CALCCRC 0x03 //CRC¼ÆËã
+#define PCD_SOFTRST 0x0F //Èí¼þ¸´Î»
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //RICREG_H
+//////////////////////////////////////////////////////////////////////////////
+// End of File
+//////////////////////////////////////////////////////////////////////////////
diff --git a/icc_apdu_lib/T0T1.c b/icc_apdu_lib/T0T1.c
new file mode 100644
index 0000000..f8f9d7b
--- /dev/null
+++ b/icc_apdu_lib/T0T1.c
@@ -0,0 +1,462 @@
+/*
+**************************************************************************************************************
+* ISO7816-1 T0,T1(Á´ · ²ã) ´« Êä Ð Òé Çý ¶¯
+*
+* _____ ISO7816-2 Á´ · ²ã Çý ¶¯_____
+*
+* Ãè Êö£º Ö÷ÒªÍê³É T0,T1(Êý¾ÝÁ´Â·²ã)´«ÊäÐÒé Êý¾Ý½»»»
+*
+* Åä Öãº
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.05Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ: Thumb-Mode + Use Cross-Module Optimization
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ T0,T1´«ÊäÐÒé·ûºÏISO7816-2£¬EMV±ê×¼£»
+*
+* ²ã Ãû£º T0T1.C
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V1.0
+*
+* ÈÕ ÆÚ£º 2008-03-31
+*
+* Copyright (c) 2008 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+ #include "LIB_Includes.H"
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+// #define MEMORY_BUFFER_SIZE 256
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+// extern unsigned char ucMemPool[]; //µ½Ê±ºòӦȥµô ICC_ADPU_Maper.CÖж¨Òå¹ý
+// extern unsigned char scMemPool[]; //µ½Ê±ºòӦȥµô ICC_ADPU_Maper.CÖж¨Òå¹ý
+
+// ICCSTRUCT *T01CurrentIccInfo; //µ±Ç°²Ù×÷µÄ¿¨ÐÅÏ¢¶¨Òå ISOUSARTDriver.CÖж¨Òå¹ý
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+// extern void SleepUs(unsigned short us);
+/***********************************************
+º¯Êý¹¦ÄÜ£º¶ÔÊý×éÖеÄÔªËؽøÐÐÒì»ò
+Èë¿Ú²ÎÊý£ºbuffer,Êý×éÊ×µØÖ·£»length,Êý×鳤¶È
+***********************************************/
+unsigned char XOR(unsigned char *buffer,unsigned char length)
+{
+ unsigned char result;
+ unsigned char i;
+ result =0;
+ for(i =0;i< length;i++)
+ {
+ result ^=buffer[i];
+ }
+ return(result);
+}
+void CalCrc16(unsigned char* input, unsigned char* Crc16, unsigned int len)
+{
+ unsigned int temp=0x6363;
+ unsigned int i;
+ unsigned char j;
+
+ for( i=0; i<len; i++ )
+ {
+ temp = temp ^((unsigned int)input[i]);
+ for (j = 0; j < 8; j++)
+ {
+ if (temp & 0x0001)
+ {
+ temp = (temp >> 1) ^ 0x8408;
+ }
+ else
+ {
+ temp = (temp >> 1);
+ }
+ }
+ }
+ Crc16[0] = (unsigned char)(temp);
+ Crc16[1] = (unsigned char)(temp>>8);
+}
+/*
+**************************************************************************************************************
+* IC ¿¨ Çå ³ý »ù ±¾ ЊϢ
+*
+* Ãè Êö£º½Ó ´¥ ³õ ʼ »¯ ¿¨ ЊϢ Êý ¾Ý ½á ¹¹
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* cid ÔÝûÓÐʹÓÃ
+*
+* ·µ »Ø£ºÎÞ
+*
+**************************************************************************************************************
+*/
+ void ResetIccInfo( unsigned char cid, ICCSTRUCT *info )
+ {
+ T01CurrentIccInfo = info;
+ info->EXDI = 1;
+ info->blknr = 0;
+ info->MSndBuffer = scMemPool; //·¢ËÍÃüÁ³åÇø SAM¿¨µÄ»º³åÇø£¬¶ÔÓÚ½Ó´¥¿¨Ó¦Ó㬴˴¦ÐèÒªÖØÐÂÉè¼Æ
+ info->MRcvBuffer = scMemPool; //½ÓÊÕÃüÁ³åÇø
+ }
+
+/*
+**************************************************************************************************************
+* IC ¿¨ ÉÏ µç ²¢ ¸´ λ
+*
+* Ãè Êö£ºISO7816 T=0 ÐÒéIC¿¨Éϵ粢¸´Î» Ä¿Ç°T=0,T=1ÐÒ鶼ʹÓô˵÷Óô˺¯Êý?
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£ºÎÞ
+*
+**************************************************************************************************************
+*/
+ unsigned short T0PowerOnCard( int ich )
+ {
+ return ICC_PowerOnCard( ich ); //¿¨ ÉÏ µç ²¢ ¸´ λ
+ }
+
+/*
+**************************************************************************************************************
+* IC ¿¨ Ï µç ´¥ µã ÊÍ ·Å
+*
+* Ãè Êö£ºISO7816 T=0 ÐÒéIC¿¨Ïµ紥µãÊÍ·Å ÉϵçÀ临λºóµ÷ÓÃÁ˴˺¯Êý?
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£ºÎÞ
+*
+**************************************************************************************************************
+*/
+ void T0PowerOffCard( int ich )
+ {
+ ICC_PowerOffCard( ich );
+ }
+
+/*
+**************************************************************************************************************
+* T0 Ð Òé ¿¨ ÈÈ ¸´ λ (À临λ)
+*
+* Ãè Êö£ºISO7816 T=0 ¿¨ ÈÈ ¸´ λ Ä¿Ç°T=0,T=1ÐÒ鶼ʹÓô˸´Î»
+*
+* ²Î Êý£ºich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+* *Info IC¿¨µ±Ç°×´Ì¬¶¨Òå
+*
+* ·µ »Ø£ºÎÞ
+*
+**************************************************************************************************************
+*/
+ unsigned short T0ResetCard( int ich, ICCSTRUCT *Info )
+ {
+ T01CurrentIccInfo = Info; // intialize pointer to Picc info structure
+ // Global pointer to the currently selected Picc
+ // for used in other routine.
+
+ return ICC_ResetCard( ich );
+ }
+
+/*
+**************************************************************************************************************
+* T0 Ð Òé Êý ¾Ý ½» »»
+*
+* Ãè Êö£ºISO7816 T=0´«ÊäÐÒéÊý¾Ý½»»»£¬Ö÷ÒªÊÇͨ¹ý7816ͨ¹ý¿ÚÏß·¢ËÍÊý¾Ý²¢½ÓÊÕÊý¾Ý
+*
+* ²Î Êý£º*send_buf ·¢ËÍÊý¾Ý»º³åÇøÖ¸Õë
+* snd_buf_len ·¢ËÍÊý¾Ý³¤¶È
+* **rec_buf ½ÓÊÕÊý¾Ý»º³åÇøÖ¸Õë
+* *rec_buf_len ½ÓÊÕÊý¾Ý³¤¶È
+* ich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£º²Ù×÷³É¹¦»òʧ°Ü״̬Âë
+*
+**************************************************************************************************************
+*/
+ unsigned short T0Exchange( unsigned char *snd_buf, unsigned char snd_buf_len, unsigned char **rec_buf,
+ unsigned char *rec_buf_len, int ich )
+ {
+ unsigned short rcode;
+
+ memcpy(T01CurrentIccInfo->MSndBuffer,snd_buf,5);
+ if(snd_buf_len > 5)
+ {
+ rcode = T0_TPDU(T01CurrentIccInfo->MSndBuffer, snd_buf+5, 1,rec_buf_len, ich);
+ }
+ else
+ {
+ rcode = T0_TPDU(T01CurrentIccInfo->MSndBuffer, T01CurrentIccInfo->MRcvBuffer, 0, rec_buf_len, ich);
+ }
+ if((rcode & 0xff00) == 0x6100) //·µ»Ø0x61xx xx¾ÍÊÇ·µ»ØµÄ»ØËÍÊý¾Ý³¤¶È
+ {
+ T01CurrentIccInfo->MSndBuffer[0] = 0x00;
+ T01CurrentIccInfo->MSndBuffer[1] = 0xC0;
+ T01CurrentIccInfo->MSndBuffer[2] = 0x00;
+ T01CurrentIccInfo->MSndBuffer[3] = 0x00;
+ T01CurrentIccInfo->MSndBuffer[4] = rcode & 0xff;
+ rcode = T0_TPDU(T01CurrentIccInfo->MSndBuffer, T01CurrentIccInfo->MRcvBuffer, 2, rec_buf_len, ich); //GetResponse
+ //*rec_buf_len = T01CurrentIccInfo->MSndBuffer[4];
+ }
+ else if((rcode & 0xff00) == 0x6C00) //·µ»Ø0x6Cxx xx¾ÍÊÇ·µ»ØµÄ»ØËÍÊý¾Ý³¤¶È
+ {
+ T01CurrentIccInfo->MSndBuffer[4] = rcode & 0xff;
+ rcode = T0_TPDU(T01CurrentIccInfo->MSndBuffer, T01CurrentIccInfo->MRcvBuffer, 2, rec_buf_len, ich); //¼ÓÈëLeºóµÄÃüÁî
+// *rec_buf_len = T01CurrentIccInfo->MSndBuffer[4];
+ }
+ *rec_buf = T01CurrentIccInfo->MRcvBuffer;
+ return rcode;
+ }
+
+/*
+**************************************************************************************************************
+* T1 Ð Òé Êý ¾Ý ½» »»
+*
+* Ãè Êö£ºISO7816 T=1´«ÊäÐÒéÊý¾Ý½»»»£¬Ö÷ÒªÊÇͨ¹ý7816ͨ¹ý¿ÚÏß·¢ËÍÊý¾Ý²¢½ÓÊÕÊý¾Ý
+*
+* ²Î Êý£º
+* cid ÔÝûÓÐʹÓÃ?
+* nad_send
+* *cmd_buf ·¢ËÍÃüÁ³åÇøÖ¸Õë
+* cmd_len ·¢ËÍÃüÁîÊý¾Ý³¤¶È
+* **rec_buf ½ÓÊÕÊý¾Ý»º³åÇøÖ¸Õë
+* *rec_buf_len ½ÓÊÕÊý¾Ý³¤¶È
+* ich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£º²Ù×÷³É¹¦»òʧ°Ü״̬Âë
+*
+**************************************************************************************************************
+*/
+ unsigned short T1Exchange(unsigned char cid, unsigned char nad_send,unsigned char *cmd_buf,
+ unsigned char cmd_len, unsigned char **rec_buf, unsigned char *rec_buf_len, int ich)
+ {
+ short wCardStatus=0, wProtocolStatus=0;
+ unsigned char Send_length,ResponseLength;
+ unsigned char BufIndex;
+
+ BufIndex = 0;
+
+ T01CurrentIccInfo->MSndBuffer[BufIndex++] = nad_send; //NAD
+ T01CurrentIccInfo->MSndBuffer[BufIndex++] = T01CurrentIccInfo->blknr<<6; //PCB
+ T01CurrentIccInfo->MSndBuffer[BufIndex++] = cmd_len; //LEN
+ memcpy(&(T01CurrentIccInfo->MSndBuffer[BufIndex]),cmd_buf,cmd_len);
+ Send_length = BufIndex+cmd_len;
+ if(T01CurrentIccInfo->Crc==1)
+ {
+ CalCrc16(T01CurrentIccInfo->MSndBuffer,T01CurrentIccInfo->MSndBuffer+Send_length,Send_length);
+ Send_length += 2;
+ }
+ else
+ {
+ T01CurrentIccInfo->MSndBuffer[Send_length] = XOR(T01CurrentIccInfo->MSndBuffer,Send_length);
+ Send_length += 1;
+ }
+
+ wProtocolStatus = T1_TPDU(T01CurrentIccInfo->MSndBuffer,Send_length,T01CurrentIccInfo->MRcvBuffer,&ResponseLength,ich);
+
+ if( wProtocolStatus != TCL_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ return (wProtocolStatus);
+ }
+
+ // Check if received block is a S-block for WTX
+ while( (T01CurrentIccInfo->MRcvBuffer[1]&0xe3) == 0xc3 )
+ {
+ T01CurrentIccInfo->MSndBuffer[0] = nad_send;
+ T01CurrentIccInfo->MSndBuffer[1] = 0xe3;
+ T01CurrentIccInfo->MSndBuffer[2] = 1;
+ T01CurrentIccInfo->MSndBuffer[3] = T01CurrentIccInfo->MRcvBuffer[3];
+ Send_length = 4;
+ if(T01CurrentIccInfo->Crc==1)
+ {
+ CalCrc16(T01CurrentIccInfo->MSndBuffer,T01CurrentIccInfo->MSndBuffer+Send_length,Send_length);
+ Send_length += 2;
+ }
+ else
+ {
+ T01CurrentIccInfo->MSndBuffer[Send_length] = XOR(T01CurrentIccInfo->MSndBuffer,Send_length);
+ Send_length += 1;
+ }
+
+ // Communicate the prepared buffer to the card and get its response.
+ wProtocolStatus = T1_TPDU(T01CurrentIccInfo->MSndBuffer,Send_length,T01CurrentIccInfo->MRcvBuffer,&ResponseLength,ich);
+ if( wProtocolStatus != TCL_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ return (wProtocolStatus);
+ }
+ }
+ // Check if received block is a I-block for chain
+ while( (T01CurrentIccInfo->MRcvBuffer[1]&0xA0) == 0x20 ) //ÐèÒªÖØÉè¼Æ
+ {
+// if(T01CurrentIccInfo->blknr != ((T01CurrentIccInfo->MRcvBuffer[1]>>6)&0x01) )
+// {
+// // Error: block number not equal.
+ return (TCL_FATAL_PROTOCOL);
+// }
+// T01CurrentIccInfo->blknr ^= 1; // Toggle block number
+//
+// T01CurrentIccInfo->MSndBuffer[0] = nad_send;
+// T01CurrentIccInfo->MSndBuffer[1] = 0x80 | T01CurrentIccInfo->blknr<<4;
+// T01CurrentIccInfo->MSndBuffer[2] = 0;
+// Send_length = 3;
+// if(T01CurrentIccInfo->Crc==1)
+// {
+// CalCrc16(T01CurrentIccInfo->MSndBuffer,T01CurrentIccInfo->MSndBuffer+Send_length,Send_length);
+// Send_length += 2;
+// }
+// else
+// {
+// T01CurrentIccInfo->MSndBuffer[Send_length] = XOR(T01CurrentIccInfo->MSndBuffer,Send_length);
+// Send_length += 1;
+// }
+//
+// // Communicate the prepared buffer to the card and get its response.
+// wProtocolStatus = T1_TPDU(T01CurrentIccInfo->MSndBuffer,Send_length,T01CurrentIccInfo->MRcvBuffer,&ResponseLength,ich);
+// if( wProtocolStatus != TCL_OK )
+// {
+// // Error: could not exchange info blocks with the card.
+// return (wProtocolStatus);
+// }
+ }
+ // Check the length of the response. It must be > 1 and <= sgbMAX_INFO_FRAME_SIZE in all cases.
+ if( (ResponseLength < 4) || (ResponseLength > 254))
+ {
+ // Error: block with inappropriate number of bytes received from the card.
+ return TCL_FATAL_PROTOCOL;
+ }
+
+ if(nad_send != T01CurrentIccInfo->MRcvBuffer[0])
+ {
+ // Error: nad not equal.
+ return ( TCL_NADINVALID );
+ }
+ if(T01CurrentIccInfo->Crc != 0)
+ {
+ wCardStatus = TCL_FATAL_PROTOCOL;//ÒÔºó´Óж¨Òå
+ }
+
+ if(XOR(T01CurrentIccInfo->MRcvBuffer,ResponseLength) != 0) //½øÐÐLRCУÑé
+ {
+ return ( TCL_CRCERR );
+ }
+ if((T01CurrentIccInfo->MRcvBuffer[1] & 0x80) != 0x00) //²»ÊÇI¿é
+ {
+ switch(T01CurrentIccInfo->MRcvBuffer[1] & 0x0f)
+ {
+ case 0:
+ return TCL_OTHERERR;
+ case 1:
+ return TCL_CRCERR;
+ case 2:
+ return TCL_OTHERERR;
+ }
+ }
+ //block number equal
+ if(T01CurrentIccInfo->blknr != ((T01CurrentIccInfo->MRcvBuffer[1]>>6)&0x01) )
+ {
+ // Error: block number not equal.
+ return (TCL_FATAL_PROTOCOL);
+ }
+ T01CurrentIccInfo->blknr ^= 1; // Toggle block number
+
+ if((ResponseLength-4) == T01CurrentIccInfo->MRcvBuffer[2])
+ {
+ *rec_buf = T01CurrentIccInfo->MRcvBuffer+3;
+ wCardStatus = T01CurrentIccInfo->MRcvBuffer[ResponseLength-3]<<8 | T01CurrentIccInfo->MRcvBuffer[ResponseLength-2];
+ *rec_buf_len = ResponseLength - 4;
+ }
+ else
+ {
+ wCardStatus = TCL_FATAL_PROTOCOL;//ÒÔºó´Óж¨Òå
+ }
+ return wCardStatus;
+ }
+
+/*
+**************************************************************************************************************
+* T1 Ð Òé Êý ¾Ý ´« ËÍ Óë ½Ó ÊÕ
+*
+* Ãè Êö£ºISO7816 T=1´«ÊäÐÒéÊý¾Ý½»»»£¬Ö÷ÒªÊÇͨ¹ý7816ͨ¹ý¿ÚÏß·¢ËÍÊý¾Ý²¢½ÓÊÕÊý¾Ý ÔÝûÓÐʹÓÃ???
+*
+* ²Î Êý£º
+* cid ÔÝûÓÐʹÓÃ?
+* nad_send
+* ich ic¿¨½Ó¿Ú¶¨Òå ϲãÐÒéÑ¡Ôñ
+*
+* ·µ »Ø£º²Ù×÷³É¹¦»òʧ°Ü״̬Âë
+*
+**************************************************************************************************************
+*/
+ unsigned short T1IFSC( unsigned char cid, unsigned char nad_send, int ich )
+ {
+ short wCardStatus=0, wProtocolStatus=0;
+ unsigned char Send_length,ResponseLength;
+
+ T01CurrentIccInfo->MSndBuffer[0] = nad_send;
+ T01CurrentIccInfo->MSndBuffer[1] = 0xC1; //IFSC Request
+ T01CurrentIccInfo->MSndBuffer[2] = 1;
+ T01CurrentIccInfo->MSndBuffer[3] = T01CurrentIccInfo->IFSI;
+ Send_length = 4;
+ if(T01CurrentIccInfo->Crc==1)
+ {
+ CalCrc16(T01CurrentIccInfo->MSndBuffer,T01CurrentIccInfo->MSndBuffer+Send_length,Send_length);
+ Send_length += 2;
+ }
+ else
+ {
+ T01CurrentIccInfo->MSndBuffer[Send_length] = XOR(T01CurrentIccInfo->MSndBuffer,Send_length);
+ Send_length += 1;
+ }
+
+ // Communicate the prepared buffer to the card and get its response.
+ wProtocolStatus = T1_TPDU(T01CurrentIccInfo->MSndBuffer,Send_length,T01CurrentIccInfo->MRcvBuffer,&ResponseLength,ich);
+ if( wProtocolStatus != TCL_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ return (wProtocolStatus);
+ }
+ if( (ResponseLength < 4) || (ResponseLength > 254))
+ {
+ // Error: block with inappropriate number of bytes received from the card.
+ return TCL_FATAL_PROTOCOL;
+ }
+
+ if(nad_send != T01CurrentIccInfo->MRcvBuffer[0])
+ {
+ // Error: nad not equal.
+ return ( TCL_NADINVALID );
+ }
+ if(T01CurrentIccInfo->Crc != 0)
+ {
+ wCardStatus = TCL_FATAL_PROTOCOL;//ÒÔºó´Óж¨Òå
+ }
+
+ if(XOR(T01CurrentIccInfo->MRcvBuffer,ResponseLength) != 0) //½øÐÐLRCУÑé
+ {
+ return ( TCL_CRCERR );
+ }
+ if((T01CurrentIccInfo->MRcvBuffer[1] & 0xE1) != 0xE1) //²»ÊÇS¿éIFSC Ack
+ {
+ return TCL_OTHERERR;
+ }
+ return wCardStatus;
+ }
+
diff --git a/icc_apdu_lib/T0T1.h b/icc_apdu_lib/T0T1.h
new file mode 100644
index 0000000..521a610
--- /dev/null
+++ b/icc_apdu_lib/T0T1.h
@@ -0,0 +1,207 @@
+/*
+**************************************************************************************************************
+* ISO7816-1 T0,T1(Á´ · ²ã,Ó² ¼þ ½Ó ¿Ú ²ã ) ´« Êä Ð Òé Çý ¶¯
+*
+* _____ ISO7816-2 Á´ · ²ã Ó² ¼þ ½Ó ¿Ú ²ã Çý ¶¯_____
+*
+* Ãè Êö£º Ö÷ÒªÍê³É T0,T1(Êý¾ÝÁ´Â·²ã)´«ÊäÐÒé Êý¾Ý½»»»
+*
+* Åä Öãº
+* CPU :
+* ÍâʱÖÓ :
+* CPUÔËÐÐʱÖÓ :
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.50Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ T0,T1´«ÊäÐÒé·ûºÏISO7816-2£¬EMV±ê×¼£»
+*
+* ²ã Ãû£º T0T1.H
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V2.0
+*
+* ÈÕ ÆÚ£º 2009-05-21
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+#ifndef __T0T1_H__
+#define __T0T1_H__
+
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+//========>>IC¿¨µ±Ç°×´Ì¬½á¹¹Ì嶨Òå
+ typedef struct
+ {
+ unsigned char TS; //ATR-TS ½ö½ÓÊÜ3bºÍ3f
+ unsigned char T0; //ATR-T0
+ unsigned char TD1; //ATR-TD1 ÊÇ·ñ»¹Òª·¢Ë͸ü¶àµÄ½Ó¿Ú×Ö½ÚÒÔ¼°ºóÐø´«ÊäËùʹÓõÄÐÒéÀàÐÍ,(½öÖ§³Ö0ºÍ1ÐÒé0x81£¬¾Ü¾øÆäËûÖµ)
+ unsigned char TD2; //ATR-TD2 TD2±íʾÊÇ·ñ»¹Òª·¢Ë͸ü¶àµÄ½Ó¿Ú×Ö½ÚÒÔ¼°ºóÐø´«ÊäËùʹÓõÄÐÒéÀàÐÍ(0x31)
+ unsigned char ETCK; //ATR-TCK ¼ìÑ鸴λӦ´ðÆÚ¼äËù·¢ËÍÊý¾ÝÍêÕûÐÔ
+ unsigned char T; //ÐÒéÀàÐÍ T=0 T=1
+ unsigned char EXDI; //·Ç±ê×¼¸´Î»Ó¦´ðÐòÁеIJ¨ÌØÂÊϵÊý
+ unsigned char SPMOD;//Ìض¨Ä£Ê½ »¹ÊÇ ½»»¥Ä£Ê½ b8=0ÓиıäÄÜÁ¦£¬=1Î޸ıäÄÜÁ¦£»b5=1²»ÓɽӿÚ×Ö½Ú¶¨Ò壬=0½Ó¿Ú×Ö½Ú¶¨Ò壻b4-b1 ÐÒéT
+ unsigned char FI; //ʱÖÓƵÂÊת»»Òò
+ unsigned char DI; //±ÈÌØÂʵ÷½ÚÒò×Ó
+ unsigned char WI; //IC¿¨·¢Ë͵ÄÈÎÒâÒ»¸ö×Ö·ûÆðʼλÉÏÉýÑØÓëÓÉIC¿¨»òÖն˴«Ë͵ÄÇ°Ò»×Ö·ûµÄÆðʼλÉÏÉýÑØÖ®¼äµÄ×î´ó¼ä¸ôµÄ¹¤×÷µÈ´ýʱ¼ä
+ unsigned char PI1; //È·¶¨IC¿¨ËùÐèµÄ×î´ó±à³ÌµçѹPÖµ¡£PI1=0±íʾIC¿¨²»Ê¹ÓÃVpp¡£
+ unsigned char II; //I1ÔÚb6~b7λÖж¨Ò壬ÓÃÓÚÈ·¶¨IC¿¨ËùÐèµÄ×î´ó±à³ÌµçÁ÷IÖµ¡£PI1=0±íʾ²»Ê¹Óô˲ÎÊý
+ unsigned char N; //TC1´«ËÍNÖ®Öµ£¬NΪ¶îÍâ±£»¤Ê±¼ä
+ unsigned char IFSI; //±íʾIC¿¨ÐÅÏ¢Óò´óСµÄ³õʼֵÕûÊý
+ unsigned char BWI; //¿éµÈ´ýʱ¼äÕûÊý(Block Waiting Time Integer)
+ unsigned char CWI; //×Ö·ûµÈ´ýʱ¼äÕûÊý(Character Waiting Time Integer)
+ unsigned char Crc; //ÈßÓàУÑé(CRC=1/Longitudinal Redundancy Check=0)
+ unsigned char blknr;//¿ìµÄÐòÁкÅ
+ unsigned char *MSndBuffer; //·¢ËÍÃüÁ³åÇø
+ unsigned char *MRcvBuffer; //½ÓÊÕÃüÁ³åÇø
+
+ int ICErrorCode; //¿¨´íÎó´úÂë ICCard_error_Msg[]
+ }ICCSTRUCT;
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+ extern ICCSTRUCT *T01CurrentIccInfo; /* IC¿¨µ±Ç°×´Ì¬¶¨Òå */
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+/*
+**************************************************************************************************************
+* ´«Êä²ã½Ó¿Ú--λÓÚÓ²¼þÇý¶¯³ÌÐòÖÐ ISOUSARTDriver.C ---> (1)
+**************************************************************************************************************
+*/
+ extern unsigned short ICC_PowerOnCard( int ich ); /* ¿¨ ÉÏ µç ²¢ ¸´ λ */
+
+ extern void ICC_PowerOffCard( int ich ); /* ¿¨ Ï µç ´¥ µã ÊÍ ·Å */
+
+ extern unsigned short ICC_ResetCard( int ich ); /* ¿¨ ÈÈ ¸´ λ (À临λ) */
+
+ extern unsigned short T0_TPDU( unsigned char *scmd, unsigned char *sdata, int ctl,
+ unsigned char *rec_bytelen, int ich );
+ /* T0 Ð Òé ´« Êä Êý ¾Ý µ¥ Ôª Ó³ Éä */
+ extern unsigned short T1_TPDU( unsigned char *send_data, unsigned char send_bytelen,
+ unsigned char *rec_data, unsigned char *rec_bytelen, int ich );
+ /* T1 Ð Òé ´« Êä Êý ¾Ý µ¥ Ôª Ó³ Éä */
+
+//========>>´«Êä²ã½Ó¿Ú--λÓÚÓ²¼þÇý¶¯³ÌÐòÖÐ --> ISOUSARTDriver.C
+/*
+**************************************************************************************************************
+* ¿¨ ÉÏ µç ²¢ ¸´ λ
+* Function Name : ICC_PowerOnCard
+* Object : ¿¨Éϵç,¸´Î» Ö÷ÒªÊÇʹÓÃÒÔLTC1756оƬʱʹÓÃ
+* Input Parameters : ich =
+* Output Parameters : ·µ»ØÖµ£ºICErrorCode
+* Functions called : none
+*
+**************************************************************************************************************
+*/
+// unsigned short ICC_PowerOnCard( int ich )
+/*
+**************************************************************************************************************
+* ¿¨ Ï µç ´¥ µã ÊÍ ·Å
+* Function Name : ICC_PowerOffCard
+* Object : ¿¨Ïµç Ðè·ûºÏISO7816-2±ê×¼£¬VCC<0.4VÐèÒªÓ²¼þµÄÅäºÏʵÏÖ
+* Input Parameters : ich = CHNL_ICC/PSAM1_POWER/PSAM2_POWER_ON
+* Output Parameters : none
+* Functions called : none
+*
+**************************************************************************************************************
+*/
+// void ICC_PowerOffCard( int ich )
+/*
+**************************************************************************************************************
+* ¿¨ ÈÈ ¸´ λ (À临λ)
+* Function Name : ICC_ResetCard
+* Object : ¿¨Èȸ´Î» (À临룬Á½Õß±¾Öʶ¼Ò»Ñù£¬Ö»ÊÇÖ´ÐеÄÌõ¼þ²»Ò»Ñù)¡£¸´Î»Ó¦´ð·ûºÏISO7816 EMV2000
+* ±ê×¼.
+* Input Parameters : ich = CHNL_ICC/PSAM1_POWER/PSAM2_POWER_ON
+* Output Parameters : ·µ»ØÖµ£ºICErrorCode
+* Functions called : none
+*
+**************************************************************************************************************
+*/
+// unsigned short ICC_ResetCard( int ich )
+/*
+**************************************************************************************************************
+* T0 Ð Òé ´« Êä Êý ¾Ý µ¥ Ôª Ó³ Éä
+* Function Name : ICC_TPDU
+* Object : ÐÒé´«ÊäÊý¾Ýµ¥ÔªÓ³Éä
+* Input Parameters : scmd=5×Ö½ÚÃüÁî×Ö·û´®Ö¸Õ루CLA¡¢INS¡¢P1¡¢P2ºÍP3£©,
+* sdata=·¢ËÍ/½ÓÊÕÊý¾Ý»º³åÈ¥Ö¸Õ룬ctl=ÐÒé¿ØÖÆ×Ö·û£¨¼ûÏÂÊö£©, *rec_bytelen½ÓÊÜÊý¾ÝµÄ³¤¶È£¬ich=IC¿¨½Ó¿Ú
+* ctl=0ÎÞÊý¾ÝÖ¡scmd[4]=0, ctl=1·¢ËÍÊý¾ÝÖ¡/Ö¡³¤¶ÈÓÉscmd[4]È·¶¨, ctl=2½ÓÊÕÊý¾ÝÖ¡
+* Output Parameters : ·µ»ØICErrorCode=SW1 SW2»òÕß0-255µÄÎïÀí²ã´íÎó´úÂë
+* Functions called : none
+*
+**************************************************************************************************************
+*/
+// unsigned short T0_TPDU( unsigned char *scmd, unsigned char *sdata, int ctl, unsigned char *rec_bytelen, int ich )
+/*
+**************************************************************************************************************
+* T1 Ð Òé ´« Êä Êý ¾Ý µ¥ Ôª Ó³ Éä
+* Function Name : T1_TPDU
+* Object : T=1 ÐÒé´«ÊäÊý¾Ýµ¥ÔªÓ³Éä
+* Input Parameters :
+* Output Parameters : ·µ»ØICErrorCode=SW1 SW2»òÕß0-255µÄÎïÀí²ã´íÎó´úÂë
+* Functions called : none
+*
+**************************************************************************************************************
+*/
+// unsigned short T1_TPDU( unsigned char *send_data, unsigned char send_bytelen, unsigned char *rec_data,
+// unsigned char *rec_bytelen, int ich )
+
+
+
+/*
+**************************************************************************************************************
+* ¶ÔÍ⿪·ÅµÄµ÷Óà T0T1.C ---> (2)
+**************************************************************************************************************
+*/
+ extern void ResetIccInfo( unsigned char cid, ICCSTRUCT *info );
+ /* */
+ extern unsigned short T0PowerOnCard( int ich ); /* */
+
+ extern void T0PowerOffCard( int ich ); /* */
+
+ extern unsigned short T0ResetCard( int ich, ICCSTRUCT *Info );
+ /* */
+ extern unsigned short T0Exchange( unsigned char *snd_buf, unsigned char snd_buf_len,
+ unsigned char **rec_buf, unsigned char *rec_buf_len, int ich );
+ /* */
+ extern unsigned short T1Exchange( unsigned char cid, unsigned char nad_send,
+ unsigned char *snd_buf, unsigned char snd_buf_len,
+ unsigned char **rec_buf, unsigned char *rec_buf_len, int ich );
+ /* */
+ extern unsigned short T1IFSC( unsigned char cid, unsigned char nad_send, int ich );
+ /* */
+
+//========>>¶ÔÍ⿪·ÅµÄµ÷Óà --> T0T1.C
+
+
+
+
+
+
+
+#endif //__T0T1_H__
+
diff --git a/icc_apdu_lib/TCL.C b/icc_apdu_lib/TCL.C
new file mode 100644
index 0000000..74d6678
--- /dev/null
+++ b/icc_apdu_lib/TCL.C
@@ -0,0 +1,502 @@
+/*
+**************************************************************************************************************
+* ISO7816-1 T=CL(Á´ · ²ã) ´« Êä Ð Òé Çý ¶¯
+*
+* _____ ISO7816-2 Á´ · ²ã Çý ¶¯_____
+*
+* Ãè Êö£º Ö÷ÒªÍê³É T=CL(Êý¾ÝÁ´Â·²ã)´«ÊäÐÒé Êý¾Ý½»»» T=CL FCD
+*
+* Åä Öãº
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.05Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ: Thumb-Mode + Use Cross-Module Optimization
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ T=CL ´«ÊäÐÒé·ûºÏISO14443±ê×¼£»
+*
+* ²ã Ãû£º TCL.C
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V1.0
+*
+* ÈÕ ÆÚ£º 2008-04-07
+*
+* Copyright (c) 2008 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+
+ #include "LIB_Includes.H"
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+ const unsigned int fsdTable[9] = {16,24,32,40,48,64,96,128,256};
+
+
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+// extern unsigned char ucMemPool[]; /* ICC_APDU_MaperÖж¨Òå¹ý */
+// extern unsigned char scMemPool[]; /* ICC_APDU_MaperÖж¨Òå¹ý */
+
+ PICCSTRUCT *TclCurrentPiccInfo; /* TCL µ±Ç°IC¿¨ÐÅÏ¢ */
+// TTLSTRUCT gICCInfo[3]; /* 3¸ö²å²Û */
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+//extern void RFI_CfgSPIForRFCard(void);
+extern void SetBitMask(unsigned char reg,unsigned char mask);
+extern void ClearBitMask(unsigned char reg,unsigned char mask);
+/*
+**************************************************************************************************************
+* ¸´ λ PICC »ù ±¾ ЊϢ
+*
+* Ãè Êö£º ¸´Î»PICCµÄ»ù±¾ÐÅÏ¢,»Ö¸´ËùÓбäÁ¿µÄÖµ Sends the RATS command and parses the ATS
+*
+* ²Î Êý£º cid : ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* info : RF¿¨Í¨ÐÅÐÅÏ¢Êý¾Ý½á¹¹
+*
+* ·µ »Ø£º ÎÞ
+*
+**************************************************************************************************************
+*/
+ void ResetPiccInfo( unsigned char cid, PICCSTRUCT *info )
+ {
+ info->cid = cid;
+ info->fsci = TCLFSDSNDMAX;
+ info->fsdi = TCLFSDRECMAX;
+ info->fsc = fsdTable[info->fsci];
+ info->fsd = fsdTable[info->fsdi];
+ info->fwi = 4;
+ info->wtx = 0;
+ info->cidSupp = 1;
+ info->nadSupp = 0;
+ info->piccDiv = 0;
+ info->pcdDiv = 0;
+ info->blknr = 0;
+ info->dsi = 3; //divider PICC -> PCD
+ info->dri = 3; //divider PCD -> PICC
+ info->MSndBuffer = ucMemPool; //·¢ËÍÃüÁ³åÇø Óû§¿¨»º³åÇø Ç°Ì᣺·Ç½Ó´¥¿¨¶¼ÊÇÓû§¿¨
+ info->MRcvBuffer = ucMemPool; //½ÓÊÕÃüÁ³åÇø
+ }
+
+/*
+**************************************************************************************************************
+* »ñ È¡ ATS
+*
+* Ãè Êö£º »ñ È¡ ATS Sends the RATS command and parses the ATS
+*
+* ²Î Êý£º cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* info RF¿¨Í¨ÐÅÐÅÏ¢Êý¾Ý½á¹¹
+*
+* ·µ »Ø£º status
+* TCL_OK
+* TCL_ATSLEN ATS of invalid length
+* TCL_ATS_FORMAT_ERR Error in ATS Format.
+* MI_RECBUF_OVERFLOW ATS buffer too small.
+*
+**************************************************************************************************************
+*/
+ unsigned short TclGetAts( unsigned char cid, PICCSTRUCT *Info )
+ {
+ unsigned short status;
+ unsigned char TL,T0,i=2;
+ unsigned short ats_len=MEMORY_BUFFER_SIZE;
+
+ HW_SPI_RF_CfgInit();
+
+ TclCurrentPiccInfo = Info; // intialize pointer to Picc info structure
+ // Global pointer to the currently selected Picc
+ // for used in other routine.
+
+ TclCurrentPiccInfo->fsdi = TCLFSDRECMAX;
+ TclCurrentPiccInfo->fsd = fsdTable[TCLFSDRECMAX];
+
+ if (cid > 14)
+ return TCL_CIDINVALID;
+
+ TclCurrentPiccInfo->MSndBuffer[0]=0xE0; // RATS commands
+ //TclCurrentPiccInfo->MSndBuffer[1]=TclCurrentPiccInfo->fsdi; // FSDI & CID
+ TclCurrentPiccInfo->MSndBuffer[1]=(TclCurrentPiccInfo->fsdi<<4)|cid; // FSDI & CID
+ if((status=Mf500PiccExchangeBlock(TclCurrentPiccInfo->MSndBuffer,4,TclCurrentPiccInfo->MRcvBuffer,&ats_len,1,641))==MI_OK) // length incl CRC
+ {
+ /* ATS received */
+ TL = TclCurrentPiccInfo->MRcvBuffer[0];
+ if (TL)
+ {
+ T0 = TclCurrentPiccInfo->MRcvBuffer[1];
+ TclCurrentPiccInfo->fsci = T0&0x0f; //max PICC receive lenght
+ TclCurrentPiccInfo->fsc = fsdTable[Info->fsci];
+
+ // TA received?
+ if (T0&0x40){
+ TclCurrentPiccInfo->piccDiv = TclCurrentPiccInfo->MRcvBuffer[i++];
+ }
+ else {
+ TclCurrentPiccInfo->piccDiv = 0; // default value
+ }
+ // TB received?
+ if (T0&0x20){
+ TclCurrentPiccInfo->fwi = (TclCurrentPiccInfo->MRcvBuffer[i++]>>4)&0x0f;
+ }
+ else {
+ Info->fwi = 4; // default value
+ }
+ // TC received?
+ if (T0&0x10){
+ TclCurrentPiccInfo->cidSupp = (TclCurrentPiccInfo->MRcvBuffer[i]>>1)&0x01;
+ TclCurrentPiccInfo->nadSupp = (TclCurrentPiccInfo->MRcvBuffer[i++])&0x01;
+ }
+ else {
+ TclCurrentPiccInfo->cidSupp = 1; // default value
+ TclCurrentPiccInfo->nadSupp = 0; // default value
+ }
+ TclCurrentPiccInfo->cid = cid;
+ TclCurrentPiccInfo->blknr = 0;
+ // application specific data available?
+// if (i != TL){
+// *app_inf_len = TL - i;
+// app_inf = &MRcvBuffer[i];
+// }
+// else {
+// *app_inf_len = 0;
+// }
+// if (i != TL)
+// printf("PICC ATRC = %s\n\r",TclCurrentPiccInfo->MRcvBuffer+i);
+ }
+ else
+ status = TCL_ATSLEN;
+ }
+ else
+ if(status != MI_NOTAGERR)
+ status = TCL_2LAYER_ERR;
+
+ return status;
+ }
+
+/*
+**************************************************************************************************************
+* IC ¿¨ PPS
+*
+* Ãè Êö£º IC¿¨ PPS Sends the Protocol and Parameter selection and checks the answer.
+* If a valid PPS response is received it calls PcdSetAttrib() with dsi and dri.
+* There is no retry attempt.
+*
+* ²Î Êý£º cid ¿¨IDºÅ cid of target picc
+* dsi Divider Send Integer to switch to
+* dri Divider Receive Integer to switch to
+*
+* ·µ »Ø£º TCL.. PPS specific error code
+*
+**************************************************************************************************************
+*/
+ unsigned short TclPps( unsigned char cid, unsigned char dsi, unsigned char dri )
+ {
+ unsigned short status;
+ unsigned short bResponseLength;
+
+ HW_SPI_RF_CfgInit();
+
+ if (cid > 14)
+ return TCL_CIDINVALID;
+
+ TclCurrentPiccInfo->MSndBuffer[0]=0xD0|cid; // PPS commands & CID
+ TclCurrentPiccInfo->MSndBuffer[1]=0x11;
+ TclCurrentPiccInfo->MSndBuffer[2]=dsi<<2 | dri;
+
+ //WriteRC(RegChannelRedundancy,0x0F);
+ WriteRC(ModeReg, 0x01);
+ SetBitMask(TxModeReg, 0x80);
+ SetBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+ PcdSetTmo(32*(1<<TclCurrentPiccInfo->fwi)+1); //080512
+
+ status = (short) ExchangeByteStream(PCD_TRANSCEIVE, TclCurrentPiccInfo->MSndBuffer,
+ 3, TclCurrentPiccInfo->MRcvBuffer, &bResponseLength);
+ if( status != MI_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ if(status != MI_NOTAGERR)
+ status = TCL_2LAYER_ERR;
+ return status;
+ }
+ if(bResponseLength != 1)
+ status = TCL_PPS_FORMAT;
+ if(TclCurrentPiccInfo->MRcvBuffer[0] != 0xD0)
+ status = TCL_PPS_FORMAT;
+
+ return status;
+ }
+
+/*
+**************************************************************************************************************
+* TCL Êý ¾Ý ½» »»
+*
+* Ãè Êö£º TCL Êý ¾Ý ½» »»
+* Exchanges Data with the Picc using the dividers set either during
+* the activation sequence or with TclPps(). On transmission errors like
+* a EDC check error or a Timeout it tries to retransmit
+* data up to 'maxRetries' times specified in TclInit,
+* then it tries to deslect the picc.
+*
+* ²Î Êý£º
+* IN: unsigned char cid cid of target picc
+* IN: unsigned char nad_send Node ADdress for sending
+* IN: unsigned char *snd_buf send data buffer
+* IN: unsigned long snd_buf_len send data length
+* IN: unsigned long ExpectedResponseLength
+*
+* IN/OUT: unsigned long *rec_buf_len rec buf size & rec'd data length
+*
+* OUT: unsigned char *nad_receive Received Node ADdress
+* OUT: unsigned char *rec_buf receive data buffer
+*
+* ·µ »Ø£º TCL_OK Sucess
+* TCL_TRANSMERR_HALTED Error during transmission,
+* Picc was deselected successfully.
+* TCL_TRANSMERR_NOTAG Error during transmission,
+* Picc could not be deselected and is
+* ignoerd.
+* MI_RECBUF_OVERFLOW more than *rec_buf_len bytes rec'd
+*
+**************************************************************************************************************
+*/
+ unsigned short TclExchange( unsigned char cid, unsigned char nad_send, unsigned char *snd_buf,
+ unsigned char snd_buf_len, unsigned char ExpectedResponseLength,
+ unsigned char **rec_buf, unsigned char *rec_buf_len )
+ {
+ short wCardStatus=0, wProtocolStatus=0;
+ unsigned short bResponseLength,BufIndex;
+
+ HW_SPI_RF_CfgInit();
+
+ BufIndex = 0;
+ TclCurrentPiccInfo->MSndBuffer[BufIndex++] = 0x02 | TclCurrentPiccInfo->blknr;
+ if(TclCurrentPiccInfo->cidSupp)
+ {
+ TclCurrentPiccInfo->MSndBuffer[0] |= 0x08;
+ TclCurrentPiccInfo->MSndBuffer[BufIndex++] = cid;
+ }
+ if(TclCurrentPiccInfo->nadSupp)
+ {
+ TclCurrentPiccInfo->MSndBuffer[0] |= 0x04;
+ TclCurrentPiccInfo->MSndBuffer[BufIndex++] = nad_send;
+ }
+ memcpy(&(TclCurrentPiccInfo->MSndBuffer[BufIndex]),snd_buf,snd_buf_len);
+
+ // Communicate the prepared buffer to the card and get its response.
+ // RxCRC and TxCRC enable, parity enable
+ //WriteRC(RegChannelRedundancy,0x0F);
+ WriteRC(ModeReg, 0x01);
+ SetBitMask(TxModeReg, 0x80);
+ SetBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+// PcdSetTmo(32*(1<<TclCurrentPiccInfo->fwi)); //080215
+ PcdSetTmo(32*(1<<TclCurrentPiccInfo->fwi)+1); //080512
+
+ wProtocolStatus = (short) ExchangeByteStream(PCD_TRANSCEIVE, TclCurrentPiccInfo->MSndBuffer,
+ snd_buf_len+BufIndex, TclCurrentPiccInfo->MRcvBuffer, &bResponseLength);
+
+ if( wProtocolStatus != MI_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ if(wProtocolStatus != MI_NOTAGERR)
+ wProtocolStatus = TCL_2LAYER_ERR;
+ return (wProtocolStatus);
+ }
+
+ // Check if received block is a S-block for WTX
+ while( (TclCurrentPiccInfo->MRcvBuffer[0]&0xf0) == 0xf0 )
+ {
+ TclCurrentPiccInfo->MSndBuffer[0] = 0xfa;
+ TclCurrentPiccInfo->MSndBuffer[1] = cid;
+ TclCurrentPiccInfo->MSndBuffer[2] = TclCurrentPiccInfo->MSndBuffer[2]&0x3f;
+
+ // Communicate the prepared buffer to the card and get its response.
+ wProtocolStatus = (short)ExchangeByteStream(PCD_TRANSCEIVE, TclCurrentPiccInfo->MSndBuffer,
+ 3, TclCurrentPiccInfo->MRcvBuffer, &bResponseLength);
+ if( wProtocolStatus != MI_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ if(wProtocolStatus != MI_NOTAGERR)
+ wProtocolStatus = TCL_2LAYER_ERR;
+ return (wProtocolStatus);
+ }
+ }
+ if(TclCurrentPiccInfo->blknr == (TclCurrentPiccInfo->MRcvBuffer[0]|0x01) ) //block number equal
+ {
+ // Error: block number not equal.
+ return (TCL_FATAL_PROTOCOL);
+ }
+ TclCurrentPiccInfo->blknr ^= 1; // Toggle block number
+
+ BufIndex = 1;
+ if(TclCurrentPiccInfo->MRcvBuffer[0] & 0x08)
+ {
+ if(cid != TclCurrentPiccInfo->MSndBuffer[BufIndex++])
+ {
+ // Error: cid not equal.
+ return (TCL_CIDINVALID);
+ }
+ }
+ if(TclCurrentPiccInfo->MRcvBuffer[0] & 0x04)
+ {
+ if(nad_send != TclCurrentPiccInfo->MSndBuffer[BufIndex++])
+ {
+ // Error: nad not equal.
+ return ( TCL_NADINVALID );
+ }
+ }
+
+// if( (TclCurrentPiccInfo->MRcvBuffer[0]&0xe0) == 0xa0 )
+// {
+// printf("Chaining\r\n");
+// }
+
+ // Check the length of the response. It must be > 1 and <= sgbMAX_INFO_FRAME_SIZE in all cases.
+ // Substract 4 bytes of T=CL overhead (PCB,CID,CRC16)
+ *rec_buf_len = bResponseLength-2;
+ if( (*rec_buf_len == 0) || (*rec_buf_len > TclCurrentPiccInfo->fsc))
+ {
+ // Error: block with inappropriate number of bytes received from the card.
+ return TCL_FATAL_PROTOCOL;
+ }
+ if(*rec_buf_len >= 2)
+ {
+ *rec_buf = TclCurrentPiccInfo->MRcvBuffer+BufIndex;
+ wCardStatus = *(TclCurrentPiccInfo->MRcvBuffer+BufIndex+*rec_buf_len-2)<<8 | *(TclCurrentPiccInfo->MRcvBuffer+BufIndex+*rec_buf_len-1);
+ *rec_buf_len -= 2;
+ }
+ else
+ {
+ return (TCL_FATAL_PROTOCOL);
+ }
+
+ if(((wCardStatus & 0xf000) != 0x6000) && ((wCardStatus & 0xf000) != 0x9000))
+ { return (TCL_FATAL_PROTOCOL); } //Òþ²ØÓйش«Êä¸ñʽ¡¢Í¨ÐÅÐÒéÏà¹ØµÄ´íÎó 080512
+
+ return wCardStatus;
+ }
+
+/*
+**************************************************************************************************************
+* TCL È¡ Ïû Ñ¡ ¶¨
+*
+* Ãè Êö£º TCL È¡ Ïû Ñ¡ ¶¨
+* Deselects the specified Picc using the divider set previously
+* during the activation sequence or using TclPps().
+* On TCL_TRANSMERR_NOTAG the CID is released and so this picc
+* is ignored.
+*
+* ²Î Êý£º cid ¿¨IDºÅ
+* IN: unsigned char cid cid of the target picc
+*
+* ·µ »Ø£º TCL_OK Picc sucessfully deselected
+ TCL_TRANSMERR_NOTAG Picc couldn't be deselected.
+*
+**************************************************************************************************************
+*/
+ unsigned short TclDeselect( unsigned char cid )
+ {
+ unsigned short status;
+ unsigned short bResponseLength;
+
+ HW_SPI_RF_CfgInit();
+
+ if (cid > 14)
+ return TCL_CIDINVALID;
+
+ TclCurrentPiccInfo->MSndBuffer[0]=0xCA; // DeSelect commands
+ TclCurrentPiccInfo->MSndBuffer[1]=cid;
+
+ //WriteRC(RegChannelRedundancy,0x0F);
+ WriteRC(ModeReg, 0x01);
+ SetBitMask(TxModeReg, 0x80);
+ SetBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+ PcdSetTmo(32*(1<<TclCurrentPiccInfo->fwi)+1); //080512
+
+ status = (short) ExchangeByteStream(PCD_TRANSCEIVE, TclCurrentPiccInfo->MSndBuffer,
+ 2, TclCurrentPiccInfo->MRcvBuffer, &bResponseLength);
+ if( status != MI_OK )
+ {
+ // Error: could not exchange info blocks with the card.
+ if(status != MI_NOTAGERR)
+ status = TCL_2LAYER_ERR;
+ return status;
+ }
+ if(bResponseLength != 2)
+ status = TCL_FATAL_PROTOCOL;
+ if(TclCurrentPiccInfo->MRcvBuffer[0] != 0xCA)
+ status = TCL_FATAL_PROTOCOL;
+
+ return status;
+ }
+
+/*
+**************************************************************************************************************
+* ÔÚÉäƵ¿¨¼ÓµçÇÒ½øÈë144433-4Çé¿öϲâÊÔ¿¨Æ¬µÄ´æÔÚ
+*
+* Ãè Êö£º ÔÚÉäƵ¿¨¼ÓµçÇÒ½øÈë144433-4Çé¿öϲâÊÔ¿¨Æ¬µÄ´æÔÚ
+*
+* ²Î Êý£º ¼ì²âCPU¿¨ÊÇ·ñÀ뿪
+*
+* ·µ »Ø£º 0 ¿¨»¹´æÔÚ
+* ·Ç0 ¿¨Æ¬À뿪
+*
+**************************************************************************************************************
+*/
+ unsigned char PICC_TclCheckRFRounge( void )
+ {
+ short wProtocolStatus=0;
+ unsigned short bResponseLength;
+ unsigned char cid=0; //×¢Òâ
+
+ HW_SPI_RF_CfgInit();
+
+ TclCurrentPiccInfo->MSndBuffer[0] = 0xBA | TclCurrentPiccInfo->blknr;
+ TclCurrentPiccInfo->MSndBuffer[1] = cid;
+
+ // Communicate the prepared buffer to the card and get its response.
+ // RxCRC and TxCRC enable, parity enable
+ //WriteRC( RegChannelRedundancy, 0x0F );
+ WriteRC(ModeReg, 0x01);
+ SetBitMask(TxModeReg, 0x80);
+ SetBitMask(RxModeReg, 0x80);
+ ClearBitMask(RFU1D, 0x10);
+ PcdSetTmo( 32 * ( 1 << TclCurrentPiccInfo->fwi ) );
+
+ wProtocolStatus = ExchangeByteStream( PCD_TRANSCEIVE,
+ TclCurrentPiccInfo->MSndBuffer,
+ 2,
+ TclCurrentPiccInfo->MRcvBuffer,
+ &bResponseLength );
+ if( wProtocolStatus != 0 )
+ {
+ // Error: could not exchange info blocks with the card.
+ return ( 0xF3 );//SLOTERROR_DEACTIVATED_PROTOCOL
+ }
+ // Check if received block is a S-block for WTX
+ if( ( ( TclCurrentPiccInfo->MRcvBuffer[0] & 0xB0 ) == 0xA0 ) ||
+ ( ( TclCurrentPiccInfo->MRcvBuffer[0] & 0xC0 ) == 0x00 ) )
+ { return 0; } //Óп¨´æÔÚ
+ return 0xF3; //SLOTERROR_DEACTIVATED_PROTOCOL;
+ }
+
diff --git a/icc_apdu_lib/TCL.H b/icc_apdu_lib/TCL.H
new file mode 100644
index 0000000..69dc3a1
--- /dev/null
+++ b/icc_apdu_lib/TCL.H
@@ -0,0 +1,246 @@
+/*
+**************************************************************************************************************
+* ISO7816-1 T=CL(Á´ · ²ã) ´« Êä Ð Òé Çý ¶¯
+*
+* _____ ISO7816-2 Á´ · ²ã Çý ¶¯_____
+*
+* Ãè Êö£º Ö÷ÒªÍê³É T=CL(Êý¾ÝÁ´Â·²ã)´«ÊäÐÒé Êý¾Ý½»»» T=CL FCD
+*
+* Åä Öãº
+* CPU :
+* ÍâʱÖÓ :
+* CPUÔËÐÐʱÖÓ :
+* ÔËÐл·¾³ : Keil ARM ( RealView MDK ) v3.50Æƽâ°æ±¾
+* »·¾³ÉèÖà : 1) ģʽ:
+* 2) ÓÅ»¯: ĬÈÏ ( Level 0 (-00) ...)
+*
+* ×¢ Ò⣺ T=CL ´«ÊäÐÒé·ûºÏISO14443±ê×¼£»
+*
+* ²ã Ãû£º TCL.H
+*
+* ×÷ Õߣº Zhang_OS@163.com
+*
+* °æ ±¾£º V2.0
+*
+* ÈÕ ÆÚ£º 2009-05-21
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+*
+**************************************************************************************************************
+*/
+#ifndef __TCL_H__
+#define __TCL_H__
+
+/*
+**************************************************************************************************************
+* ³£ Á¿
+**************************************************************************************************************
+*/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* ISO14443 Support Properties
+* Some of the protokoll functions of ISO14443 needs information about
+* the capability of the reader device, which are provided by this
+* constants.
+*/
+//{
+#define TCLFSDSNDMAX 8 ///< max. frame size send
+#define TCLFSDRECMAX 8 ///< max. frame size rcv
+#define TCLDSMAX 3 ///< max. baudrate divider PICC --> PCD
+#define TCLDRMAX 3 ///< max. baudrate divider PCD --> PICC
+
+#define TCLDSDFLT 0 ///< default baudrate divider PICC --> PCD
+#define TCLDRDFLT 0 ///< default baudrate divider PCD --> PICC
+//}
+
+
+#define DEF_FIFO_LENGTH 64 //!< default FIFO size
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*
+**************************************************************************************************************
+* Àà ÐÍ
+**************************************************************************************************************
+*/
+//PICC info struct
+ typedef struct
+ {
+ unsigned char cid;
+ unsigned char fsci;
+ unsigned char fsdi;
+ unsigned int fsc;
+ unsigned int fsd;
+ unsigned char fwi;
+ unsigned char wtx;
+ unsigned char cidSupp;
+ unsigned char nadSupp;
+ unsigned char piccDiv;
+ unsigned char pcdDiv;
+ unsigned char blknr; ////¿ìµÄÐòÁкÅ
+ unsigned char dsi; //divider PICC -> PCD
+ unsigned char dri; //divider PCD -> PICC
+ unsigned char *MSndBuffer; //·¢ËÍÃüÁ³åÇø
+ unsigned char *MRcvBuffer; //½ÓÊÕÃüÁ³åÇø
+ }PICCSTRUCT;
+
+
+/*
+**************************************************************************************************************
+* ±ä Á¿
+**************************************************************************************************************
+*/
+ extern PICCSTRUCT *TclCurrentPiccInfo; // structure pointer for current selected Picc
+
+/*
+**************************************************************************************************************
+* º¯ Êý
+**************************************************************************************************************
+*/
+
+ extern void ResetPiccInfo( unsigned char cid, PICCSTRUCT *info );
+ /* */
+ extern unsigned short TclGetAts( unsigned char cid, PICCSTRUCT *Info );
+ /* */
+ extern unsigned short TclPps( unsigned char cid, unsigned char dsi, unsigned char dri );
+ /* */
+ extern unsigned short TclExchange( unsigned char cid, unsigned char nad_send, unsigned char *snd_buf,
+ unsigned char snd_buf_len, unsigned char ExpectedResponseLength,
+ unsigned char **rec_buf, unsigned char *rec_buf_len );
+ /* */
+ extern unsigned short TclDeselect( unsigned char cid );
+ /* */
+ extern unsigned char PICC_TclCheckRFRounge( void ); /* */
+
+/*
+**************************************************************************************************************
+* ¸´ λ PICC »ù ±¾ ЊϢ
+*
+* Ãè Êö£º ¸´Î»PICCµÄ»ù±¾ÐÅÏ¢,»Ö¸´ËùÓбäÁ¿µÄÖµ Sends the RATS command and parses the ATS
+*
+* ²Î Êý£º cid : ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* info : RF¿¨Í¨ÐÅÐÅÏ¢Êý¾Ý½á¹¹
+*
+* ·µ »Ø£º ÎÞ
+*
+**************************************************************************************************************
+*/
+// void ResetPiccInfo( unsigned char cid, PICCSTRUCT *info )
+/*
+**************************************************************************************************************
+* »ñ È¡ ATS
+*
+* Ãè Êö£º »ñ È¡ ATS Sends the RATS command and parses the ATS
+*
+* ²Î Êý£º cid ¿¨IDºÅ ½Ó´¥Ê½Ã»ÓÐʲô´Ë²ÎÊý£¬ ·Ç½Ó´¥Ê½Ê¹Óô˲ÎÊý
+* info RF¿¨Í¨ÐÅÐÅÏ¢Êý¾Ý½á¹¹
+*
+* ·µ »Ø£º status
+* TCL_OK
+* TCL_ATSLEN ATS of invalid length
+* TCL_ATS_FORMAT_ERR Error in ATS Format.
+* MI_RECBUF_OVERFLOW ATS buffer too small.
+*
+**************************************************************************************************************
+*/
+// unsigned short TclGetAts( unsigned char cid, PICCSTRUCT *Info )
+/*
+**************************************************************************************************************
+* IC ¿¨ PPS
+*
+* Ãè Êö£º IC¿¨ PPS Sends the Protocol and Parameter selection and checks the answer.
+* If a valid PPS response is received it calls PcdSetAttrib() with dsi and dri.
+* There is no retry attempt.
+*
+* ²Î Êý£º cid ¿¨IDºÅ cid of target picc
+* dsi Divider Send Integer to switch to
+* dri Divider Receive Integer to switch to
+*
+* ·µ »Ø£º TCL.. PPS specific error code
+*
+**************************************************************************************************************
+*/
+// unsigned short TclPps( unsigned char cid, unsigned char dsi, unsigned char dri )
+/*
+**************************************************************************************************************
+* TCL Êý ¾Ý ½» »»
+*
+* Ãè Êö£º TCL Êý ¾Ý ½» »»
+* Exchanges Data with the Picc using the dividers set either during
+* the activation sequence or with TclPps(). On transmission errors like
+* a EDC check error or a Timeout it tries to retransmit
+* data up to 'maxRetries' times specified in TclInit,
+* then it tries to deslect the picc.
+*
+* ²Î Êý£º
+* IN: unsigned char cid cid of target picc
+* IN: unsigned char nad_send Node ADdress for sending
+* IN: unsigned char *snd_buf send data buffer
+* IN: unsigned long snd_buf_len send data length
+* IN: unsigned long ExpectedResponseLength
+*
+* IN/OUT: unsigned long *rec_buf_len rec buf size & rec'd data length
+*
+* OUT: unsigned char *nad_receive Received Node ADdress
+* OUT: unsigned char *rec_buf receive data buffer
+*
+* ·µ »Ø£º TCL_OK Sucess
+* TCL_TRANSMERR_HALTED Error during transmission,
+* Picc was deselected successfully.
+* TCL_TRANSMERR_NOTAG Error during transmission,
+* Picc could not be deselected and is
+* ignoerd.
+* MI_RECBUF_OVERFLOW more than *rec_buf_len bytes rec'd
+*
+**************************************************************************************************************
+*/
+// unsigned short TclExchange( unsigned char cid, unsigned char nad_send, unsigned char *snd_buf,
+// unsigned char snd_buf_len, unsigned char ExpectedResponseLength,
+// unsigned char **rec_buf, unsigned char *rec_buf_len )
+/*
+**************************************************************************************************************
+* TCL È¡ Ïû Ñ¡ ¶¨
+*
+* Ãè Êö£º TCL È¡ Ïû Ñ¡ ¶¨
+* Deselects the specified Picc using the divider set previously
+* during the activation sequence or using TclPps().
+* On TCL_TRANSMERR_NOTAG the CID is released and so this picc
+* is ignored.
+*
+* ²Î Êý£º cid ¿¨IDºÅ
+* IN: unsigned char cid cid of the target picc
+*
+* ·µ »Ø£º TCL_OK Picc sucessfully deselected
+ TCL_TRANSMERR_NOTAG Picc couldn't be deselected.
+*
+**************************************************************************************************************
+*/
+// unsigned short TclDeselect( unsigned char cid )
+/*
+**************************************************************************************************************
+* ÔÚÉäƵ¿¨¼ÓµçÇÒ½øÈë144433-4Çé¿öϲâÊÔ¿¨Æ¬µÄ´æÔÚ
+*
+* Ãè Êö£º ÔÚÉäƵ¿¨¼ÓµçÇÒ½øÈë144433-4Çé¿öϲâÊÔ¿¨Æ¬µÄ´æÔÚ
+*
+* ²Î Êý£º ¼ì²âCPU¿¨ÊÇ·ñÀ뿪
+*
+* ·µ »Ø£º 0 ¿¨»¹´æÔÚ
+* ·Ç0 ¿¨Æ¬À뿪
+*
+**************************************************************************************************************
+*/
+// unsigned char PICC_TclCheckRFRounge( void )
+
+
+
+
+
+
+
+#endif
diff --git a/icc_apdu_lib/des.c b/icc_apdu_lib/des.c
new file mode 100644
index 0000000..640c7c1
--- /dev/null
+++ b/icc_apdu_lib/des.c
@@ -0,0 +1,493 @@
+/*
+ * FIPS-46-3 compliant 3DES implementation
+ *
+ * Copyright (C) 2001-2003 Christophe Devine
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include "des.h"
+
+/* the eight DES S-boxes */
+
+const uint32 SB1[64] =
+{
+ 0x01010400, 0x00000000, 0x00010000, 0x01010404,
+ 0x01010004, 0x00010404, 0x00000004, 0x00010000,
+ 0x00000400, 0x01010400, 0x01010404, 0x00000400,
+ 0x01000404, 0x01010004, 0x01000000, 0x00000004,
+ 0x00000404, 0x01000400, 0x01000400, 0x00010400,
+ 0x00010400, 0x01010000, 0x01010000, 0x01000404,
+ 0x00010004, 0x01000004, 0x01000004, 0x00010004,
+ 0x00000000, 0x00000404, 0x00010404, 0x01000000,
+ 0x00010000, 0x01010404, 0x00000004, 0x01010000,
+ 0x01010400, 0x01000000, 0x01000000, 0x00000400,
+ 0x01010004, 0x00010000, 0x00010400, 0x01000004,
+ 0x00000400, 0x00000004, 0x01000404, 0x00010404,
+ 0x01010404, 0x00010004, 0x01010000, 0x01000404,
+ 0x01000004, 0x00000404, 0x00010404, 0x01010400,
+ 0x00000404, 0x01000400, 0x01000400, 0x00000000,
+ 0x00010004, 0x00010400, 0x00000000, 0x01010004
+};
+
+const uint32 SB2[64] =
+{
+ 0x80108020, 0x80008000, 0x00008000, 0x00108020,
+ 0x00100000, 0x00000020, 0x80100020, 0x80008020,
+ 0x80000020, 0x80108020, 0x80108000, 0x80000000,
+ 0x80008000, 0x00100000, 0x00000020, 0x80100020,
+ 0x00108000, 0x00100020, 0x80008020, 0x00000000,
+ 0x80000000, 0x00008000, 0x00108020, 0x80100000,
+ 0x00100020, 0x80000020, 0x00000000, 0x00108000,
+ 0x00008020, 0x80108000, 0x80100000, 0x00008020,
+ 0x00000000, 0x00108020, 0x80100020, 0x00100000,
+ 0x80008020, 0x80100000, 0x80108000, 0x00008000,
+ 0x80100000, 0x80008000, 0x00000020, 0x80108020,
+ 0x00108020, 0x00000020, 0x00008000, 0x80000000,
+ 0x00008020, 0x80108000, 0x00100000, 0x80000020,
+ 0x00100020, 0x80008020, 0x80000020, 0x00100020,
+ 0x00108000, 0x00000000, 0x80008000, 0x00008020,
+ 0x80000000, 0x80100020, 0x80108020, 0x00108000
+};
+
+const uint32 SB3[64] =
+{
+ 0x00000208, 0x08020200, 0x00000000, 0x08020008,
+ 0x08000200, 0x00000000, 0x00020208, 0x08000200,
+ 0x00020008, 0x08000008, 0x08000008, 0x00020000,
+ 0x08020208, 0x00020008, 0x08020000, 0x00000208,
+ 0x08000000, 0x00000008, 0x08020200, 0x00000200,
+ 0x00020200, 0x08020000, 0x08020008, 0x00020208,
+ 0x08000208, 0x00020200, 0x00020000, 0x08000208,
+ 0x00000008, 0x08020208, 0x00000200, 0x08000000,
+ 0x08020200, 0x08000000, 0x00020008, 0x00000208,
+ 0x00020000, 0x08020200, 0x08000200, 0x00000000,
+ 0x00000200, 0x00020008, 0x08020208, 0x08000200,
+ 0x08000008, 0x00000200, 0x00000000, 0x08020008,
+ 0x08000208, 0x00020000, 0x08000000, 0x08020208,
+ 0x00000008, 0x00020208, 0x00020200, 0x08000008,
+ 0x08020000, 0x08000208, 0x00000208, 0x08020000,
+ 0x00020208, 0x00000008, 0x08020008, 0x00020200
+};
+
+const uint32 SB4[64] =
+{
+ 0x00802001, 0x00002081, 0x00002081, 0x00000080,
+ 0x00802080, 0x00800081, 0x00800001, 0x00002001,
+ 0x00000000, 0x00802000, 0x00802000, 0x00802081,
+ 0x00000081, 0x00000000, 0x00800080, 0x00800001,
+ 0x00000001, 0x00002000, 0x00800000, 0x00802001,
+ 0x00000080, 0x00800000, 0x00002001, 0x00002080,
+ 0x00800081, 0x00000001, 0x00002080, 0x00800080,
+ 0x00002000, 0x00802080, 0x00802081, 0x00000081,
+ 0x00800080, 0x00800001, 0x00802000, 0x00802081,
+ 0x00000081, 0x00000000, 0x00000000, 0x00802000,
+ 0x00002080, 0x00800080, 0x00800081, 0x00000001,
+ 0x00802001, 0x00002081, 0x00002081, 0x00000080,
+ 0x00802081, 0x00000081, 0x00000001, 0x00002000,
+ 0x00800001, 0x00002001, 0x00802080, 0x00800081,
+ 0x00002001, 0x00002080, 0x00800000, 0x00802001,
+ 0x00000080, 0x00800000, 0x00002000, 0x00802080
+};
+
+const uint32 SB5[64] =
+{
+ 0x00000100, 0x02080100, 0x02080000, 0x42000100,
+ 0x00080000, 0x00000100, 0x40000000, 0x02080000,
+ 0x40080100, 0x00080000, 0x02000100, 0x40080100,
+ 0x42000100, 0x42080000, 0x00080100, 0x40000000,
+ 0x02000000, 0x40080000, 0x40080000, 0x00000000,
+ 0x40000100, 0x42080100, 0x42080100, 0x02000100,
+ 0x42080000, 0x40000100, 0x00000000, 0x42000000,
+ 0x02080100, 0x02000000, 0x42000000, 0x00080100,
+ 0x00080000, 0x42000100, 0x00000100, 0x02000000,
+ 0x40000000, 0x02080000, 0x42000100, 0x40080100,
+ 0x02000100, 0x40000000, 0x42080000, 0x02080100,
+ 0x40080100, 0x00000100, 0x02000000, 0x42080000,
+ 0x42080100, 0x00080100, 0x42000000, 0x42080100,
+ 0x02080000, 0x00000000, 0x40080000, 0x42000000,
+ 0x00080100, 0x02000100, 0x40000100, 0x00080000,
+ 0x00000000, 0x40080000, 0x02080100, 0x40000100
+};
+
+const uint32 SB6[64] =
+{
+ 0x20000010, 0x20400000, 0x00004000, 0x20404010,
+ 0x20400000, 0x00000010, 0x20404010, 0x00400000,
+ 0x20004000, 0x00404010, 0x00400000, 0x20000010,
+ 0x00400010, 0x20004000, 0x20000000, 0x00004010,
+ 0x00000000, 0x00400010, 0x20004010, 0x00004000,
+ 0x00404000, 0x20004010, 0x00000010, 0x20400010,
+ 0x20400010, 0x00000000, 0x00404010, 0x20404000,
+ 0x00004010, 0x00404000, 0x20404000, 0x20000000,
+ 0x20004000, 0x00000010, 0x20400010, 0x00404000,
+ 0x20404010, 0x00400000, 0x00004010, 0x20000010,
+ 0x00400000, 0x20004000, 0x20000000, 0x00004010,
+ 0x20000010, 0x20404010, 0x00404000, 0x20400000,
+ 0x00404010, 0x20404000, 0x00000000, 0x20400010,
+ 0x00000010, 0x00004000, 0x20400000, 0x00404010,
+ 0x00004000, 0x00400010, 0x20004010, 0x00000000,
+ 0x20404000, 0x20000000, 0x00400010, 0x20004010
+};
+
+const uint32 SB7[64] =
+{
+ 0x00200000, 0x04200002, 0x04000802, 0x00000000,
+ 0x00000800, 0x04000802, 0x00200802, 0x04200800,
+ 0x04200802, 0x00200000, 0x00000000, 0x04000002,
+ 0x00000002, 0x04000000, 0x04200002, 0x00000802,
+ 0x04000800, 0x00200802, 0x00200002, 0x04000800,
+ 0x04000002, 0x04200000, 0x04200800, 0x00200002,
+ 0x04200000, 0x00000800, 0x00000802, 0x04200802,
+ 0x00200800, 0x00000002, 0x04000000, 0x00200800,
+ 0x04000000, 0x00200800, 0x00200000, 0x04000802,
+ 0x04000802, 0x04200002, 0x04200002, 0x00000002,
+ 0x00200002, 0x04000000, 0x04000800, 0x00200000,
+ 0x04200800, 0x00000802, 0x00200802, 0x04200800,
+ 0x00000802, 0x04000002, 0x04200802, 0x04200000,
+ 0x00200800, 0x00000000, 0x00000002, 0x04200802,
+ 0x00000000, 0x00200802, 0x04200000, 0x00000800,
+ 0x04000002, 0x04000800, 0x00000800, 0x00200002
+};
+
+const uint32 SB8[64] =
+{
+ 0x10001040, 0x00001000, 0x00040000, 0x10041040,
+ 0x10000000, 0x10001040, 0x00000040, 0x10000000,
+ 0x00040040, 0x10040000, 0x10041040, 0x00041000,
+ 0x10041000, 0x00041040, 0x00001000, 0x00000040,
+ 0x10040000, 0x10000040, 0x10001000, 0x00001040,
+ 0x00041000, 0x00040040, 0x10040040, 0x10041000,
+ 0x00001040, 0x00000000, 0x00000000, 0x10040040,
+ 0x10000040, 0x10001000, 0x00041040, 0x00040000,
+ 0x00041040, 0x00040000, 0x10041000, 0x00001000,
+ 0x00000040, 0x10040040, 0x00001000, 0x00041040,
+ 0x10001000, 0x00000040, 0x10000040, 0x10040000,
+ 0x10040040, 0x10000000, 0x00040000, 0x10001040,
+ 0x00000000, 0x10041040, 0x00040040, 0x10000040,
+ 0x10040000, 0x10001000, 0x10001040, 0x00000000,
+ 0x10041040, 0x00041000, 0x00041000, 0x00001040,
+ 0x00001040, 0x00040040, 0x10000000, 0x10041000
+};
+
+/* PC1: left and right halves bit-swap */
+
+const uint32 LHs[16] =
+{
+ 0x00000000, 0x00000001, 0x00000100, 0x00000101,
+ 0x00010000, 0x00010001, 0x00010100, 0x00010101,
+ 0x01000000, 0x01000001, 0x01000100, 0x01000101,
+ 0x01010000, 0x01010001, 0x01010100, 0x01010101
+};
+
+const uint32 RHs[16] =
+{
+ 0x00000000, 0x01000000, 0x00010000, 0x01010000,
+ 0x00000100, 0x01000100, 0x00010100, 0x01010100,
+ 0x00000001, 0x01000001, 0x00010001, 0x01010001,
+ 0x00000101, 0x01000101, 0x00010101, 0x01010101,
+};
+
+/* platform-independant 32-bit integer manipulation macros */
+
+#define GET_UINT32(n,b,i) \
+{ \
+ (n) = ( (uint32) (b)[(i) ] << 24 ) \
+ | ( (uint32) (b)[(i) + 1] << 16 ) \
+ | ( (uint32) (b)[(i) + 2] << 8 ) \
+ | ( (uint32) (b)[(i) + 3] ); \
+}
+
+#define PUT_UINT32(n,b,i) \
+{ \
+ (b)[(i) ] = (uint8) ( (n) >> 24 ); \
+ (b)[(i) + 1] = (uint8) ( (n) >> 16 ); \
+ (b)[(i) + 2] = (uint8) ( (n) >> 8 ); \
+ (b)[(i) + 3] = (uint8) ( (n) ); \
+}
+
+/* Initial Permutation macro */
+
+#define DES_IP(X,Y) \
+{ \
+ T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \
+ T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \
+ T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \
+ T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \
+ Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF; \
+ T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T; \
+ X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF; \
+}
+
+/* Final Permutation macro */
+
+#define DES_FP(X,Y) \
+{ \
+ X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF; \
+ T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T; \
+ Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF; \
+ T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \
+ T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \
+ T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \
+ T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \
+}
+
+/* DES round macro */
+
+#define DES_ROUND(X,Y) \
+{ \
+ T = *SK++ ^ X; \
+ Y ^= SB8[ (T ) & 0x3F ] ^ \
+ SB6[ (T >> 8) & 0x3F ] ^ \
+ SB4[ (T >> 16) & 0x3F ] ^ \
+ SB2[ (T >> 24) & 0x3F ]; \
+ \
+ T = *SK++ ^ ((X << 28) | (X >> 4)); \
+ Y ^= SB7[ (T ) & 0x3F ] ^ \
+ SB5[ (T >> 8) & 0x3F ] ^ \
+ SB3[ (T >> 16) & 0x3F ] ^ \
+ SB1[ (T >> 24) & 0x3F ]; \
+}
+
+/* DES key schedule */
+
+int des_main_ks( uint32 SK[32], uint8 key[8] )
+{
+ int i;
+ uint32 X, Y, T;
+
+ GET_UINT32( X, key, 0 );
+ GET_UINT32( Y, key, 4 );
+
+ /* Permuted Choice 1 */
+
+ T = ((Y >> 4) ^ X) & 0x0F0F0F0F; X ^= T; Y ^= (T << 4);
+ T = ((Y ) ^ X) & 0x10101010; X ^= T; Y ^= (T );
+
+ X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2)
+ | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] )
+ | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6)
+ | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4);
+
+ Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2)
+ | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] )
+ | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6)
+ | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4);
+
+ X &= 0x0FFFFFFF;
+ Y &= 0x0FFFFFFF;
+
+ /* calculate subkeys */
+
+ for( i = 0; i < 16; i++ )
+ {
+ if( i < 2 || i == 8 || i == 15 )
+ {
+ X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF;
+ Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF;
+ }
+ else
+ {
+ X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF;
+ Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF;
+ }
+
+ *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000)
+ | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000)
+ | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000)
+ | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000)
+ | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000)
+ | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000)
+ | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400)
+ | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100)
+ | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010)
+ | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004)
+ | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001);
+
+ *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000)
+ | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000)
+ | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000)
+ | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000)
+ | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000)
+ | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000)
+ | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000)
+ | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400)
+ | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100)
+ | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011)
+ | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002);
+ }
+
+ return( 0 );
+}
+
+int des_set_key( des_context *ctx, uint8 key[8] )
+{
+ int i;
+
+ /* setup encryption subkeys */
+
+ des_main_ks( ctx->esk, key );
+
+ /* setup decryption subkeys */
+
+ for( i = 0; i < 32; i += 2 )
+ {
+ ctx->dsk[i ] = ctx->esk[30 - i];
+ ctx->dsk[i + 1] = ctx->esk[31 - i];
+ }
+
+ return( 0 );
+}
+
+/* DES 64-bit block encryption/decryption */
+
+void des_crypt( uint32 SK[32], uint8 input[8], uint8 output[8] )
+{
+ uint32 X, Y, T;
+
+ GET_UINT32( X, input, 0 );
+ GET_UINT32( Y, input, 4 );
+
+ DES_IP( X, Y );
+
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+
+ DES_FP( Y, X );
+
+ PUT_UINT32( Y, output, 0 );
+ PUT_UINT32( X, output, 4 );
+}
+
+void des_encrypt( des_context *ctx, uint8 input[8], uint8 output[8] )
+{
+ des_crypt( ctx->esk, input, output );
+}
+
+void des_decrypt( des_context *ctx, uint8 input[8], uint8 output[8] )
+{
+ des_crypt( ctx->dsk, input, output );
+}
+
+/* Triple-DES key schedule */
+
+int des3_set_2keys( des3_context *ctx, uint8 key1[8], uint8 key2[8] )
+{
+ int i;
+
+ des_main_ks( ctx->esk , key1 );
+ des_main_ks( ctx->dsk + 32, key2 );
+
+ for( i = 0; i < 32; i += 2 )
+ {
+ ctx->dsk[i ] = ctx->esk[30 - i];
+ ctx->dsk[i + 1] = ctx->esk[31 - i];
+
+ ctx->esk[i + 32] = ctx->dsk[62 - i];
+ ctx->esk[i + 33] = ctx->dsk[63 - i];
+
+ ctx->esk[i + 64] = ctx->esk[ i];
+ ctx->esk[i + 65] = ctx->esk[ 1 + i];
+
+ ctx->dsk[i + 64] = ctx->dsk[ i];
+ ctx->dsk[i + 65] = ctx->dsk[ 1 + i];
+ }
+
+ return( 0 );
+}
+
+int des3_set_3keys( des3_context *ctx, uint8 key1[8], uint8 key2[8],
+ uint8 key3[8] )
+{
+ int i;
+
+ des_main_ks( ctx->esk , key1 );
+ des_main_ks( ctx->dsk + 32, key2 );
+ des_main_ks( ctx->esk + 64, key3 );
+
+ for( i = 0; i < 32; i += 2 )
+ {
+ ctx->dsk[i ] = ctx->esk[94 - i];
+ ctx->dsk[i + 1] = ctx->esk[95 - i];
+
+ ctx->esk[i + 32] = ctx->dsk[62 - i];
+ ctx->esk[i + 33] = ctx->dsk[63 - i];
+
+ ctx->dsk[i + 64] = ctx->esk[30 - i];
+ ctx->dsk[i + 65] = ctx->esk[31 - i];
+ }
+
+ return( 0 );
+}
+
+/* Triple-DES 64-bit block encryption/decryption */
+
+void des3_crypt( uint32 SK[96], uint8 input[8], uint8 output[8] )
+{
+ uint32 X, Y, T;
+
+ GET_UINT32( X, input, 0 );
+ GET_UINT32( Y, input, 4 );
+
+ DES_IP( X, Y );
+
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+ DES_ROUND( X, Y ); DES_ROUND( Y, X );
+
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+ DES_ROUND( Y, X ); DES_ROUND( X, Y );
+
+ DES_FP( Y, X );
+
+ PUT_UINT32( Y, output, 0 );
+ PUT_UINT32( X, output, 4 );
+}
+
+void des3_encrypt( des3_context *ctx, uint8 input[8], uint8 output[8] )
+{
+ des3_crypt( ctx->esk, input, output );
+}
+
+void des3_decrypt( des3_context *ctx, uint8 input[8], uint8 output[8] )
+{
+ des3_crypt( ctx->dsk, input, output );
+}
diff --git a/icc_apdu_lib/des.h b/icc_apdu_lib/des.h
new file mode 100644
index 0000000..0f5765e
--- /dev/null
+++ b/icc_apdu_lib/des.h
@@ -0,0 +1,37 @@
+#ifndef _DES_H
+#define _DES_H
+
+#ifndef uint8
+#define uint8 unsigned char
+#endif
+
+#ifndef uint32
+#define uint32 unsigned long
+#endif
+
+typedef struct
+{
+ uint32 esk[32]; /* DES encryption subkeys */
+ uint32 dsk[32]; /* DES decryption subkeys */
+}
+des_context;
+
+typedef struct
+{
+ uint32 esk[96]; /* Triple-DES encryption subkeys */
+ uint32 dsk[96]; /* Triple-DES decryption subkeys */
+}
+des3_context;
+
+int des_set_key( des_context *ctx, uint8 key[8] );
+void des_encrypt( des_context *ctx, uint8 input[8], uint8 output[8] );
+void des_decrypt( des_context *ctx, uint8 input[8], uint8 output[8] );
+
+int des3_set_2keys( des3_context *ctx, uint8 key1[8], uint8 key2[8] );
+int des3_set_3keys( des3_context *ctx, uint8 key1[8], uint8 key2[8],
+ uint8 key3[8] );
+
+void des3_encrypt( des3_context *ctx, uint8 input[8], uint8 output[8] );
+void des3_decrypt( des3_context *ctx, uint8 input[8], uint8 output[8] );
+
+#endif /* des.h */
diff --git a/icc_apdu_lib/erase_mf.c b/icc_apdu_lib/erase_mf.c
new file mode 100644
index 0000000..6b61e5a
--- /dev/null
+++ b/icc_apdu_lib/erase_mf.c
@@ -0,0 +1,138 @@
+#include "des.h"
+#include "string.h"
+#include "erase_mf.h"
+
+#define __recovery_key__ 0
+
+const u8 cmd_sel_mf[] = "\x00\xa4\x00\x00\x02\x3f\x00";
+const u8 cmd_sel_ec01[] = "\x00\xa4\x00\x00\x02\xEC\x01";
+const u8 cmd_get_rand[] = "\x00\x84\x00\x00\x04";
+const u8 initial_key0[] = "\x70\x66\x73\x64\x6f\x63\x66\x73\x27\xa3\x27\x27\x23\x27";
+const u8 cmd_ex_auth[] = "\x00\x82\x00\x00\x08";
+const u8 cmd_erase_mf[] = "\x80\x0E\x00\x00\x00";
+const u8 cmd_creat_key[] = "\x80\xE0\x00\x00\x07\x3F\x01\x20\x01\xFE\xFF\xFF";
+const u8 cmd_write_key[] = "\x80\xD4\x01\x00\x15\xF9\xF0\xAA\x0A\xFF";
+const u8 initial_key1[] = "\xaa\x0e\xaa\xaa\xa8\x46\xab\xeb\xfe\xc3\xc7\xcf\xe9\xe5\xf9\xaa";
+
+#if __recovery_key__
+const u8 temp_key[] = "\x57\x41\x54\x43\x48\x44\x41\x54\x41\x54\x69\x6d\x65\x43\x4f\x53";
+#endif
+
+static u8 des_ctx[768];
+
+u8 single_des_set_keys(u8 key[8])
+{
+ return des_set_key((des_context*)des_ctx, key);
+}
+
+void single_des_encrypt(u8 src[8], u8 dest[8])
+{
+ des_encrypt((des_context*)des_ctx, src, dest);
+}
+
+void single_des_decrypt(u8 src[8], u8 dest[8])
+{
+ des_decrypt((des_context*)des_ctx, src, dest);
+}
+
+u8 triple_des_set_keys(u8 key[16])
+{
+ return des3_set_2keys((des3_context*)des_ctx, key, key+8);
+}
+
+void triple_des_encrypt(u8 src[8], u8 dest[8])
+{
+ des3_encrypt((des3_context*)des_ctx, src, dest);
+}
+
+void triple_des_decrypt(u8 src[8], u8 dest[8])
+{
+ des3_decrypt((des3_context*)des_ctx, src, dest);
+}
+
+u16 erase_mf(void)
+{
+ u16 rcode;
+ u8 cmd_buff[32];
+ u8 temp_buff[16];
+ u8 rcv_len;
+ u8* prcv_buff;
+ u8 i;
+
+ //Ñ¡ÔñMF
+ memcpy(cmd_buff, cmd_sel_mf, 7);
+ rcode = Gen_Exchange(0,0,cmd_buff,7,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+
+ //Ñ¡ÔñEC01
+ //ÈôÈÔÈ»´æÔÚEC01Ŀ¼£¬ÔòÈÏΪ֮ǰδ½øÐвÁ³ý²Ù×÷
+ memcpy(cmd_buff, cmd_sel_ec01, 7);
+ rcode = Gen_Exchange(0,0,cmd_buff,7,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ {
+ return 0;
+ }
+
+ for(i=0;i<8;i++)
+ temp_buff[i] = initial_key0[i] ^ 0x27;
+
+ //Ñ¡ÔñMF
+ memcpy(cmd_buff, cmd_sel_mf, 7);
+ rcode = Gen_Exchange(0,0,cmd_buff,7,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+
+ //»ñÈ¡Ëæ»úÊý
+ memcpy(cmd_buff, cmd_get_rand, 5);
+ rcode = Gen_Exchange(0,0,cmd_buff,5,4,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+ else
+ {
+ memset(cmd_buff, 0, 8);
+ memcpy(cmd_buff, prcv_buff, 4);
+ }
+
+ for(i=0;i<8;i++)
+ temp_buff[8+i] = initial_key1[i+7] ^ 0xAA;
+
+ //¼ÓÃÜËæ»úÊý
+ #if __recovery_key__
+ memset(temp_buff, 0, 16);
+ #endif
+ triple_des_set_keys(temp_buff);
+ triple_des_encrypt(cmd_buff, temp_buff);
+
+ //Ö´ÐÐÍⲿÈÏÖ¤
+ memcpy(cmd_buff, cmd_ex_auth, 5);
+ memcpy(cmd_buff+5, temp_buff, 8);
+ rcode = Gen_Exchange(0,0,cmd_buff,13,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+
+ //²Á³ýMF
+ memcpy(cmd_buff, cmd_erase_mf, 5);
+ rcode = Gen_Exchange(0,0,cmd_buff,5,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+
+ //´´½¨keyÎļþ
+ memcpy(cmd_buff, cmd_creat_key, 12);
+ rcode = Gen_Exchange(0,0,cmd_buff,12,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+
+ //×°ÔØеÄÖ÷¿ØÃÜÔ¿
+ memset(cmd_buff, 0, 32);
+ memcpy(cmd_buff, cmd_write_key, 10);
+ #if __recovery_key__
+ memcpy(cmd_buff+10, temp_key, 16);
+ #endif
+ rcode = Gen_Exchange(0,0,cmd_buff,26,0,&prcv_buff,&rcv_len, PROTOCOL_T0_CH1);
+ if(rcode != 0x9000)
+ return rcode;
+
+ return 0x9000;
+}
+
diff --git a/icc_apdu_lib/erase_mf.h b/icc_apdu_lib/erase_mf.h
new file mode 100644
index 0000000..d803722
--- /dev/null
+++ b/icc_apdu_lib/erase_mf.h
@@ -0,0 +1,9 @@
+#ifndef __erase_mf_h__
+#define __erase_mf_h__
+
+#include "stm32f10x_lib.h"
+#include "icc_apdu_lib.h"
+
+extern u16 erase_mf(void);
+
+#endif
diff --git a/icc_apdu_lib/icc_apdu_lib_v02.h b/icc_apdu_lib/icc_apdu_lib_v02.h
new file mode 100644
index 0000000..5ec22b5
--- /dev/null
+++ b/icc_apdu_lib/icc_apdu_lib_v02.h
@@ -0,0 +1,108 @@
+#ifndef __ICC_APDU_LIB_H__
+#define __ICC_APDU_LIB_H__
+
+#define PROTOCOL_T0_CH1 1 // PSAM2
+#define PROTOCOL_TCL_PCD0 0x80 //·Ç½Ó´¥Ê½¿¨
+
+#define PICC_REQ_ALL 0x52
+#define PICC_REQ_IDLE 0x26
+//¿¨Éϵ磬ÓÃÓÚSAM¿¨À临λ
+//²ÎÊý£ºcid=0
+// ich ͨµÀºÅ
+//·µ»Ø£º0³É¹¦
+extern unsigned short Gen_PowerOnCard(unsigned char cid, int ich);
+
+//¹Ø±ÕSAM¿¨µçÔ´
+//²ÎÊý£ºich ͨµÀºÅ
+extern void Gen_PowerOffCard(int ich);
+
+//¹¦ÄÜ£º¿¨¸´Î»Ç°³õʼ»¯Ïà¹ØÊý¾Ý½á¹¹£¨ÓÃÓÚSAM»ò¿¨Æ¬£©
+//²ÎÊý£ºcid=0
+// ich ͨµÀºÅ
+void Gen_ResetInfo( unsigned char cid, int ich );
+//¹¦ÄÜ£º¿¨¸´Î»£¨¿ÉÓÃÓÚ¸´Î»SAM»ò¿¨Æ¬£©
+//²ÎÊý£ºcid=0
+// ich ͨµÀºÅ
+//·µ»Ø£º0³É¹¦
+extern unsigned short Gen_ResetCard(unsigned char cid, int ich);
+
+//¹¦ÄÜ£º¿¨Êý¾Ý½»»»
+//²ÎÊý£ºcid=0
+// nad_send=0
+// cmd_buf ÃüÁ³åÇø
+// cmd_len ÃüÁ¶È
+// ExpectedResponseLength ÆÚÍû¿¨Æ¬»Ø¸´µÄÊý¾Ý³¤¶È
+// rec_buf ÓÃÓÚ»ñÈ¡·µ»ØÊý¾ÝµÄÖ¸Õë
+// rec_buf_len ʵ¼Ê½ÓÊÕµ½µÄÊý¾Ý³¤¶È
+// ich ͨµÀºÅ
+//·µ»Ø£º0³É¹¦
+extern unsigned short Gen_Exchange(unsigned char cid,
+ unsigned char nad_send,
+ unsigned char *cmd_buf,
+ unsigned char cmd_len,
+ unsigned char ExpectedResponseLength,
+ unsigned char **rec_buf,
+ unsigned char *rec_buf_len,
+ int ich);
+
+//¹¦ÄÜ£ºActivation of a PICC in IDLE mode.
+//²ÎÊý£ºbr (IN) Baudrate for MIFARE communication 0 106 kBaud
+// atq (OUT) Answer to Request
+// sak (OUT) Select acknowledge
+// uid (OUT) up to 10 bytes UID
+// uid_len (OUT) length of the UID
+//·µ»Ø£º0 ok
+extern short Mf500PiccActivateIdle(unsigned char br,
+ unsigned char *atq,
+ unsigned char *sak,
+ unsigned char *uid,
+ unsigned char *uid_len);
+
+//¹¦ÄÜ£ºSends the PICC into the halt state.
+//²ÎÊý£ºNone
+//·µ»Ø£º0 ok
+extern short Mf500PiccHalt(void);
+
+//¹¦ÄÜ£ºÔÚÉäƵ¿¨¼ÓµçÇÒ½øÈë144433-4Çé¿öϲâÊÔ¿¨Æ¬µÄ´æÔÚ
+//²ÎÊý£ºÎÞ
+//·µ»Ø£º0 ¿¨´æÔÚ
+// ÆäËû ¿¨²»´æÔÚ
+extern unsigned char PICC_TclCheckRFRounge(void);
+
+//¹¦ÄÜ£º¸üÐÂsam¿¨¶¨Ê±µ¥ÔªtickÖµ
+// ÐèÔÚ1msÖжϺ¯ÊýÖе÷ÓÃ
+extern void update_sam_ticker(void);
+
+//¹¦ÄÜ£º³õʼ»¯SAMͨѶ½Ó¿Ú
+//²ÎÊý£ºÎÞ
+//·µ»Ø£ºÎÞ
+extern void ISO7816_USART_Init(void);
+
+
+//¹¦ÄÜ: ÉèÖÃ3DES(Ë«±¶³¤)ÃÜÔ¿
+//²ÎÊý: 16×Ö½ÚÃÜÔ¿Öµ
+//·µ»Ø: 0 ³É¹¦
+// ÆäËû ʧ°Ü
+//extern u8 des_set_keys(u8 key[16]);
+
+//¹¦ÄÜ: 3des¼ÓÃÜ
+//²ÎÊý: src[8] ÊäÈë8×Ö½ÚÃ÷ÎÄÊý¾Ý
+// dest[8] Êä³ö8×Ö½ÚÃÜÎÄÊý¾Ý
+//·µ»Ø: ÎÞ
+//extern void des_encrypt(u8 src [ 8 ], u8 dest [ 8 ]);
+
+//¹¦ÄÜ: 3des½âÃÜ
+//²ÎÊý: src[8] ÊäÈë8×Ö½ÚÃÜÎÄÊý¾Ý
+// dest[8] Êä³ö8×Ö½ÚÃ÷ÎÄÊý¾Ý
+//·µ»Ø: ÎÞ
+//extern void des_encrypt(u8 src [ 8 ], u8 dest [ 8 ]);
+
+//¹¦ÄÜ: ²Á³ýESAM¿ªÆÕ¿¨½á¹¹£¬²¢Ìæ»»³õʼÖ÷¿ØÃÜԿΪ16×Ö½ÚÈ«0
+//²ÎÊý: ÎÞ
+//·µ»Ø: 0x9000 ³É¹¦
+// 0x0000 ²»ÊÇ¿ªÆÕ³õʼESAM¿¨¿Õ¼ä£¬²»ÄܽøÐвÁ³ý²Ù×÷
+// ÆäËû ʧ°Ü
+//extern u16 erase_mf(void);
+
+#endif
+
diff --git a/lcd/Bebas_Neue18x36_Numbers.h b/lcd/Bebas_Neue18x36_Numbers.h
new file mode 100644
index 0000000..5a975b2
--- /dev/null
+++ b/lcd/Bebas_Neue18x36_Numbers.h
@@ -0,0 +1,42 @@
+/*
+ * Bebas_Neue18x36_Numberes.h
+ *
+ * Created: 30/03/2012 1:54:32 AM
+ * Author: andy
+ */
+
+
+#ifndef BEBAS_NEUE18X36_NUMBERS_H_
+#define BEBAS_NEUE18X36_NUMBERS_H_
+
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Bebas_Neue18x36
+//GLCD FontSize : 18 x 36
+
+static const char Bebas_Neue18x36_Numbers[] PROGMEM = {
+ 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char .
+ 0x12, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, // Code for char /
+ 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x3F, 0x00, 0x00, 0xC0, 0x0F, 0x1F, 0x00, 0x00, 0x80, 0x0F, 0x1F, 0x00, 0x00, 0x80, 0x0F, 0x1F, 0x00, 0x00, 0x80, 0x0F, 0x3F, 0x00, 0x00, 0xC0, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 0
+ 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 1
+ 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0xF0, 0x07, 0xF8, 0x0F, 0x00, 0xFE, 0x07, 0xFC, 0x0F, 0x00, 0xFF, 0x07, 0xFE, 0x0F, 0xC0, 0xFF, 0x07, 0xFE, 0x0F, 0xE0, 0xFF, 0x07, 0x3E, 0x00, 0xF0, 0xCF, 0x07, 0x1F, 0x00, 0xF8, 0xC3, 0x07, 0x1F, 0x00, 0xFE, 0xC1, 0x07, 0x1F, 0x00, 0x7F, 0xC0, 0x07, 0x1F, 0x80, 0x3F, 0xC0, 0x07, 0x3F, 0xF0, 0x1F, 0xC0, 0x07, 0xFE, 0xFF, 0x0F, 0xC0, 0x07, 0xFE, 0xFF, 0x03, 0xC0, 0x07, 0xFC, 0xFF, 0x01, 0xC0, 0x07, 0xF8, 0x7F, 0x00, 0xC0, 0x07, 0xE0, 0x0F, 0x00, 0x00, 0x00, // Code for char 2
+ 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x7F, 0x00, 0xF8, 0x07, 0x00, 0xFF, 0x01, 0xFC, 0x07, 0x00, 0xFF, 0x03, 0xFE, 0x07, 0x00, 0xFF, 0x07, 0xFE, 0x07, 0x00, 0xFF, 0x07, 0x3F, 0x80, 0x0F, 0xC0, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x3F, 0xC0, 0x1F, 0xC0, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0xFF, 0xF8, 0xFF, 0x01, 0xE0, 0x1F, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 3
+ 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xF8, 0x3F, 0x1F, 0x00, 0x00, 0xFF, 0x0F, 0x1F, 0x00, 0xC0, 0xFF, 0x03, 0x1F, 0x00, 0xF0, 0x7F, 0x00, 0x1F, 0x00, 0xFE, 0x1F, 0x00, 0x1F, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, // Code for char 4
+ 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x7E, 0x00, 0xFE, 0xFF, 0x1F, 0xFE, 0x01, 0xFE, 0xFF, 0x1F, 0xFE, 0x03, 0xFE, 0xFF, 0x1F, 0xFE, 0x07, 0xFE, 0xFF, 0x1F, 0xFE, 0x07, 0xFE, 0xC7, 0x03, 0xC0, 0x0F, 0x3E, 0xE0, 0x01, 0x80, 0x0F, 0x3E, 0xE0, 0x01, 0x80, 0x0F, 0x3E, 0xF0, 0x01, 0x80, 0x0F, 0x3E, 0xF0, 0x03, 0xC0, 0x0F, 0x3E, 0xF0, 0xFF, 0xFF, 0x07, 0x3E, 0xE0, 0xFF, 0xFF, 0x07, 0x3E, 0xE0, 0xFF, 0xFF, 0x03, 0x3E, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 5
+ 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x3E, 0x80, 0x07, 0xC0, 0x0F, 0x1F, 0xC0, 0x03, 0x80, 0x0F, 0x1F, 0xC0, 0x03, 0x80, 0x0F, 0x1F, 0xE0, 0x03, 0x80, 0x0F, 0x3F, 0xE0, 0x07, 0xC0, 0x0F, 0x3E, 0xE0, 0xFF, 0xFF, 0x07, 0xFE, 0xC3, 0xFF, 0xFF, 0x07, 0xFE, 0xC3, 0xFF, 0xFF, 0x03, 0xFC, 0x83, 0xFF, 0xFF, 0x01, 0xF8, 0x03, 0xFE, 0x7F, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, // Code for char 6
+ 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x06, 0x3E, 0x00, 0x00, 0xE0, 0x07, 0x3E, 0x00, 0x00, 0xFE, 0x07, 0x3E, 0x00, 0xE0, 0xFF, 0x07, 0x3E, 0x00, 0xFC, 0xFF, 0x07, 0x3E, 0xC0, 0xFF, 0xFF, 0x03, 0x3E, 0xFC, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0xFF, 0x03, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, // Code for char 7
+ 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0xC0, 0x3F, 0x00, 0xF8, 0x7F, 0xF8, 0xFF, 0x01, 0xFC, 0xFF, 0xFD, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x7E, 0xC0, 0x3F, 0xC0, 0x07, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x7E, 0xC0, 0x3F, 0xE0, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0x7F, 0xF8, 0xFF, 0x01, 0xC0, 0x1F, 0xC0, 0x3F, 0x00, // Code for char 8
+ 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0xE0, 0xFF, 0x07, 0xFC, 0x01, 0xF8, 0xFF, 0x1F, 0xFC, 0x03, 0xFC, 0xFF, 0x3F, 0xFC, 0x07, 0xFE, 0xFF, 0x3F, 0xFC, 0x07, 0xFE, 0xFF, 0x7F, 0xC0, 0x07, 0x3F, 0x00, 0x7E, 0xC0, 0x0F, 0x1F, 0x00, 0x7C, 0x80, 0x0F, 0x1F, 0x00, 0x3C, 0x80, 0x0F, 0x1F, 0x00, 0x3C, 0x80, 0x0F, 0x3F, 0x00, 0x1E, 0xC0, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // Code for char 9
+ };
+
+
+
+
+
+#endif /* BEBAS_NEUE18X36_NUMBERES_H_ */
diff --git a/lcd/Bebas_Neue20x36_Bold_Numbers.h b/lcd/Bebas_Neue20x36_Bold_Numbers.h
new file mode 100644
index 0000000..63916c5
--- /dev/null
+++ b/lcd/Bebas_Neue20x36_Bold_Numbers.h
@@ -0,0 +1,42 @@
+/*
+ * Bebas_Neue20x36_Numbers.h
+ *
+ * Created: 30/03/2012 1:51:48 AM
+ * Author: andy
+ */
+
+
+#ifndef BEBAS_NEUE20X36_BOLD_NUMBERS_H_
+#define BEBAS_NEUE20X36_BOLD_NUMBERS_H_
+
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Bebas_Neue20x36
+//GLCD FontSize : 20 x 36
+
+static const char Bebas_Neue20x36_Bold_Numbers[] PROGMEM = {
+ 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char .
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x01, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, // Code for char /
+ 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x3F, 0x00, 0x00, 0xC0, 0x0F, 0x1F, 0x00, 0x00, 0x80, 0x0F, 0x3F, 0x00, 0x00, 0xC0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 0
+ 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 1
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0xF0, 0x07, 0xF8, 0x0F, 0x00, 0xFE, 0x07, 0xFC, 0x0F, 0x00, 0xFF, 0x07, 0xFE, 0x0F, 0xC0, 0xFF, 0x07, 0xFE, 0x0F, 0xE0, 0xFF, 0x07, 0xFE, 0x0F, 0xF0, 0xFF, 0x07, 0xFF, 0x0F, 0xF8, 0xFF, 0x07, 0x3F, 0x00, 0xFE, 0xCF, 0x07, 0x1F, 0x00, 0xFF, 0xC3, 0x07, 0x1F, 0x80, 0xFF, 0xC1, 0x07, 0x3F, 0xF0, 0x7F, 0xC0, 0x07, 0xFF, 0xFF, 0x3F, 0xC0, 0x07, 0xFF, 0xFF, 0x1F, 0xC0, 0x07, 0xFE, 0xFF, 0x0F, 0xC0, 0x07, 0xFE, 0xFF, 0x03, 0xC0, 0x07, 0xFC, 0xFF, 0x01, 0xC0, 0x07, 0xF8, 0x7F, 0x00, 0xC0, 0x07, 0xE0, 0x0F, 0x00, 0x00, 0x00, // Code for char 2
+ 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x7F, 0x00, 0xF8, 0x07, 0x00, 0xFF, 0x01, 0xFC, 0x07, 0x00, 0xFF, 0x03, 0xFE, 0x07, 0x00, 0xFF, 0x07, 0xFE, 0x07, 0x00, 0xFF, 0x07, 0xFF, 0x87, 0x0F, 0xFF, 0x0F, 0xFF, 0x87, 0x0F, 0xFF, 0x0F, 0x3F, 0x80, 0x0F, 0xC0, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x3F, 0xC0, 0x1F, 0xC0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0xFF, 0xF8, 0xFF, 0x01, 0xE0, 0x1F, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 3
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xF8, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0x3F, 0x1F, 0x00, 0xF0, 0xFF, 0x0F, 0x1F, 0x00, 0xFE, 0xFF, 0x03, 0x1F, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, // Code for char 4
+ 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x7E, 0x00, 0xFE, 0xFF, 0x1F, 0xFE, 0x01, 0xFE, 0xFF, 0x1F, 0xFE, 0x03, 0xFE, 0xFF, 0x1F, 0xFE, 0x07, 0xFE, 0xFF, 0x1F, 0xFE, 0x07, 0xFE, 0xFF, 0x1F, 0xFE, 0x0F, 0xFE, 0xFF, 0x1F, 0xFE, 0x0F, 0xFE, 0xE7, 0x03, 0xC0, 0x0F, 0x3E, 0xF0, 0x01, 0x80, 0x0F, 0x3E, 0xF0, 0x03, 0xC0, 0x0F, 0x3E, 0xF0, 0xFF, 0xFF, 0x0F, 0x3E, 0xF0, 0xFF, 0xFF, 0x0F, 0x3E, 0xF0, 0xFF, 0xFF, 0x07, 0x3E, 0xE0, 0xFF, 0xFF, 0x07, 0x3E, 0xE0, 0xFF, 0xFF, 0x03, 0x3E, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 5
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x3F, 0xC0, 0x07, 0xC0, 0x0F, 0x1F, 0xE0, 0x03, 0x80, 0x0F, 0x3F, 0xE0, 0x07, 0xC0, 0x0F, 0x3F, 0xE0, 0xFF, 0xFF, 0x0F, 0xFF, 0xE3, 0xFF, 0xFF, 0x0F, 0xFE, 0xE3, 0xFF, 0xFF, 0x07, 0xFE, 0xC3, 0xFF, 0xFF, 0x07, 0xFE, 0xC3, 0xFF, 0xFF, 0x03, 0xFC, 0x83, 0xFF, 0xFF, 0x01, 0xF8, 0x03, 0xFE, 0x7F, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, // Code for char 6
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x06, 0x3E, 0x00, 0x00, 0xE0, 0x07, 0x3E, 0x00, 0x00, 0xFE, 0x07, 0x3E, 0x00, 0xE0, 0xFF, 0x07, 0x3E, 0x00, 0xFC, 0xFF, 0x07, 0x3E, 0xC0, 0xFF, 0xFF, 0x07, 0x3E, 0xFC, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0xFF, 0x03, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, // Code for char 7
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0xC0, 0x3F, 0x00, 0xF8, 0x7F, 0xF8, 0xFF, 0x01, 0xFC, 0xFF, 0xFD, 0xFF, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x7F, 0xC0, 0x3F, 0xC0, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0x7F, 0xC0, 0x3F, 0xE0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0x7F, 0xF8, 0xFF, 0x01, 0xC0, 0x1F, 0xC0, 0x3F, 0x00, // Code for char 8
+ 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0xE0, 0xFF, 0x07, 0xFC, 0x01, 0xF8, 0xFF, 0x1F, 0xFC, 0x03, 0xFC, 0xFF, 0x3F, 0xFC, 0x07, 0xFE, 0xFF, 0x3F, 0xFC, 0x07, 0xFE, 0xFF, 0x7F, 0xFC, 0x07, 0xFF, 0xFF, 0x7F, 0xFC, 0x0F, 0xFF, 0xFF, 0x7F, 0xC0, 0x0F, 0x3F, 0x00, 0x7E, 0xC0, 0x0F, 0x1F, 0x00, 0x7C, 0x80, 0x0F, 0x3F, 0x00, 0x3E, 0xC0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFE, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // Code for char 9
+ };
+
+
+
+
+
+#endif /* BEBAS_NEUE20X36_NUMBERS_H_ */
diff --git a/lcd/Earthbound_12x19_48to57.h b/lcd/Earthbound_12x19_48to57.h
new file mode 100644
index 0000000..37d1744
--- /dev/null
+++ b/lcd/Earthbound_12x19_48to57.h
@@ -0,0 +1,19 @@
+#ifndef Earthbound_12x19_48to57_H
+#define Earthbound_12x19_48to57_H
+
+// Size: 12x19
+// Chars: 48 to 57
+static const char font_Earthbound_12x19_48to57[] PROGMEM = {
+0x00, 0xe0, 0xf0, 0x38, 0x0c, 0x0c, 0x0c, 0x0c, 0x38, 0xf8, 0xc0, 0x00, 0x00, 0x1f, 0x7f, 0xe0, 0x80, 0x80, 0x80, 0x80, 0xe0, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, // Char '0'
+0x00, 0x10, 0x18, 0x18, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Char '1'
+0x00, 0x08, 0x1c, 0x0c, 0x0c, 0x0c, 0x0c, 0x8c, 0xf8, 0xf0, 0x00, 0x00, 0x00, 0xf0, 0xf8, 0x9c, 0x8c, 0x86, 0x86, 0x83, 0x83, 0x80, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, // Char '2'
+0x00, 0x08, 0x1c, 0x0c, 0x0c, 0x0c, 0x0c, 0x8c, 0xf8, 0xf0, 0x00, 0x00, 0x00, 0x80, 0xc0, 0x80, 0x81, 0x83, 0x83, 0xc7, 0xff, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, // Char '3'
+0x00, 0x00, 0x00, 0x80, 0xc0, 0x70, 0x38, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1e, 0x1b, 0x11, 0x18, 0x10, 0xff, 0xff, 0x10, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, // Char '4'
+0x00, 0x00, 0xf4, 0xfc, 0x1c, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc3, 0x83, 0x83, 0x83, 0x83, 0xc7, 0xfe, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, // Char '5'
+0x00, 0xc0, 0xf0, 0x78, 0x1c, 0x0c, 0x0c, 0x0c, 0x08, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xc3, 0x83, 0x83, 0x83, 0xc3, 0xfe, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, // Char '6'
+0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x8c, 0xcc, 0x7c, 0x3c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x80, 0xf0, 0x7c, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Char '7'
+0x00, 0xf0, 0xf8, 0x1c, 0x0c, 0x0c, 0x0c, 0x0c, 0xf8, 0xf0, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x8f, 0x07, 0x06, 0x06, 0x8f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, // Char '8'
+0x00, 0xf0, 0xf8, 0x1c, 0x0c, 0x0c, 0x0c, 0x1c, 0xf8, 0xe0, 0x00, 0x00, 0x00, 0x01, 0x87, 0x8e, 0x8c, 0x8c, 0x8c, 0xee, 0x7f, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 // Char '9'
+};
+
+#endif
diff --git a/lcd/Liberation_Sans11x14_Numbers.h b/lcd/Liberation_Sans11x14_Numbers.h
new file mode 100644
index 0000000..d2de386
--- /dev/null
+++ b/lcd/Liberation_Sans11x14_Numbers.h
@@ -0,0 +1,42 @@
+/*
+ * Liberation_Sans11x14_Numbers.h
+ *
+ * Created: 30/03/2012 1:31:10 AM
+ * Author: andy
+ */
+
+
+#ifndef LIBERATION_SANS11X14_NUMBERS_H_
+#define LIBERATION_SANS11X14_NUMBERS_H_
+
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Liberation_Sans11x14 46 to 57
+//GLCD FontSize : 11 x 14
+
+static const char Liberation_Sans11x14_Numbers[] PROGMEM = {
+ 0x04, 0x00, 0x00, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char .
+ 0x05, 0x00, 0x38, 0x80, 0x3F, 0xFC, 0x0F, 0xFF, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char /
+ 0x0A, 0x00, 0x00, 0xF0, 0x07, 0xFC, 0x1F, 0xFE, 0x3F, 0x0E, 0x38, 0x06, 0x30, 0x0E, 0x38, 0xFE, 0x3F, 0xFC, 0x1F, 0xF0, 0x07, 0x00, 0x00, // Code for char 0
+ 0x0B, 0x00, 0x00, 0x00, 0x00, 0x18, 0x30, 0x0C, 0x30, 0x0E, 0x30, 0xFE, 0x3F, 0xFE, 0x3F, 0xFE, 0x3F, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, // Code for char 1
+ 0x0A, 0x00, 0x00, 0x18, 0x38, 0x1C, 0x3C, 0x1E, 0x3E, 0x06, 0x37, 0x86, 0x33, 0xC6, 0x31, 0xFE, 0x31, 0xFC, 0x30, 0x78, 0x30, 0x00, 0x00, // Code for char 2
+ 0x0A, 0x00, 0x00, 0x18, 0x0C, 0x1C, 0x1C, 0x1E, 0x3C, 0xC6, 0x30, 0xC6, 0x30, 0xC6, 0x31, 0xFE, 0x3F, 0xBC, 0x1F, 0x3C, 0x0F, 0x00, 0x00, // Code for char 3
+ 0x0B, 0x00, 0x00, 0x00, 0x07, 0xC0, 0x07, 0xE0, 0x06, 0x38, 0x06, 0x1E, 0x06, 0xFE, 0x3F, 0xFE, 0x3F, 0xFE, 0x3F, 0x00, 0x06, 0x00, 0x06, // Code for char 4
+ 0x0A, 0x00, 0x00, 0xFE, 0x0C, 0xFE, 0x1C, 0xC6, 0x3C, 0x66, 0x38, 0x66, 0x30, 0xE6, 0x38, 0xE6, 0x3F, 0xC6, 0x1F, 0x80, 0x0F, 0x00, 0x00, // Code for char 5
+ 0x0A, 0x00, 0x00, 0xF0, 0x07, 0xFC, 0x1F, 0xFC, 0x3F, 0x8E, 0x38, 0xC6, 0x30, 0xC6, 0x30, 0xCE, 0x3F, 0x8C, 0x1F, 0x08, 0x0F, 0x00, 0x00, // Code for char 6
+ 0x0A, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x38, 0x06, 0x3F, 0xC6, 0x3F, 0xE6, 0x03, 0xFE, 0x00, 0x3E, 0x00, 0x0E, 0x00, 0x00, 0x00, // Code for char 7
+ 0x0A, 0x00, 0x00, 0x38, 0x0F, 0xFC, 0x1F, 0xFE, 0x3F, 0xC6, 0x30, 0xC6, 0x30, 0xC6, 0x30, 0xFE, 0x3F, 0xFC, 0x1F, 0x38, 0x0F, 0x00, 0x00, // Code for char 8
+ 0x0A, 0x00, 0x00, 0x78, 0x08, 0xFC, 0x18, 0xFE, 0x39, 0x86, 0x31, 0x86, 0x31, 0x86, 0x38, 0xFE, 0x1F, 0xFC, 0x1F, 0xF0, 0x07, 0x00, 0x00 // Code for char 9
+ };
+
+
+
+
+
+#endif /* LIBERATION_SANS11X14_NUMBERS_H_ */
diff --git a/lcd/Liberation_Sans15x21_Numbers.h b/lcd/Liberation_Sans15x21_Numbers.h
new file mode 100644
index 0000000..21a36f7
--- /dev/null
+++ b/lcd/Liberation_Sans15x21_Numbers.h
@@ -0,0 +1,42 @@
+/*
+ * Liberation_Sans15x21_Numbers.h
+ *
+ * Created: 30/03/2012 1:34:30 AM
+ * Author: andy
+ */
+
+
+#ifndef LIBERATION_SANS15X21_NUMBERS_H_
+#define LIBERATION_SANS15X21_NUMBERS_H_
+
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Liberation_Sans15x21 46 to 57
+//GLCD FontSize : 15 x 21
+
+static const char Liberation_Sans15x21_Numbers[] PROGMEM = {
+ 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char .
+ 0x07, 0x00, 0x00, 0x1E, 0x00, 0xE0, 0x1F, 0x00, 0xFF, 0x1F, 0xF8, 0xFF, 0x03, 0xFF, 0x1F, 0x00, 0xFF, 0x01, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char /
+ 0x0E, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0xF8, 0xFF, 0x01, 0xFC, 0xFF, 0x07, 0xFC, 0xFF, 0x07, 0x3E, 0x80, 0x0F, 0x0E, 0x00, 0x0E, 0x0E, 0x00, 0x0E, 0x0E, 0x00, 0x0E, 0x1E, 0x80, 0x0F, 0xFC, 0xFF, 0x07, 0xFC, 0xFF, 0x07, 0xF8, 0xFF, 0x01, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, // Code for char 0
+ 0x0E, 0x00, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x38, 0x00, 0x0E, 0x38, 0x00, 0x0E, 0x1C, 0x00, 0x0E, 0x0E, 0x00, 0x0E, 0xFE, 0xFF, 0x0F, 0xFE, 0xFF, 0x0F, 0xFE, 0xFF, 0x0F, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, // Code for char 1
+ 0x0E, 0x00, 0x00, 0x00, 0x60, 0x00, 0x0F, 0x78, 0x80, 0x0F, 0x7C, 0xC0, 0x0F, 0x7C, 0xE0, 0x0F, 0x1E, 0xF0, 0x0F, 0x0E, 0xF8, 0x0E, 0x0E, 0x7C, 0x0E, 0x0E, 0x3E, 0x0E, 0x1E, 0x1F, 0x0E, 0xFE, 0x0F, 0x0E, 0xFC, 0x07, 0x0E, 0xF8, 0x03, 0x0E, 0xF0, 0x01, 0x0E, 0x00, 0x00, 0x00, // Code for char 2
+ 0x0E, 0x00, 0x00, 0x00, 0x30, 0x80, 0x01, 0x38, 0x80, 0x03, 0x3C, 0x80, 0x07, 0x3C, 0x80, 0x0F, 0x1E, 0x00, 0x0F, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x1E, 0x1F, 0x0F, 0xFE, 0xFF, 0x0F, 0xFC, 0xFB, 0x07, 0xFC, 0xF9, 0x03, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0x00, // Code for char 3
+ 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x80, 0xEF, 0x00, 0xC0, 0xE7, 0x00, 0xF0, 0xE1, 0x00, 0x7C, 0xE0, 0x00, 0x3E, 0xE0, 0x00, 0xFE, 0xFF, 0x0F, 0xFE, 0xFF, 0x0F, 0xFE, 0xFF, 0x0F, 0xFE, 0xFF, 0x0F, 0x00, 0xE0, 0x00, 0x00, 0xE0, 0x00, // Code for char 4
+ 0x0E, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0xF8, 0x87, 0x03, 0xFE, 0x87, 0x07, 0xFE, 0x87, 0x0F, 0xFE, 0x07, 0x0F, 0x0E, 0x03, 0x0E, 0x8E, 0x03, 0x0E, 0x8E, 0x03, 0x0E, 0x8E, 0x07, 0x0F, 0x8E, 0xFF, 0x07, 0x0E, 0xFF, 0x07, 0x0E, 0xFE, 0x03, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, // Code for char 5
+ 0x0E, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0xF0, 0xFF, 0x01, 0xF8, 0xFF, 0x07, 0xFC, 0xFF, 0x07, 0x3E, 0x0E, 0x0F, 0x0E, 0x07, 0x0E, 0x0E, 0x07, 0x0E, 0x0E, 0x07, 0x0E, 0x1E, 0x0F, 0x0F, 0x3E, 0xFF, 0x0F, 0x3C, 0xFE, 0x07, 0x38, 0xFE, 0x03, 0x30, 0xF8, 0x01, 0x00, 0x00, 0x00, // Code for char 6
+ 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x0F, 0x0E, 0xE0, 0x0F, 0x0E, 0xF8, 0x0F, 0x0E, 0xFE, 0x0F, 0x8E, 0xFF, 0x00, 0xCE, 0x0F, 0x00, 0xFE, 0x03, 0x00, 0xFE, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 7
+ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0xF8, 0xFB, 0x03, 0xFC, 0xFB, 0x07, 0xFE, 0xFF, 0x0F, 0x1E, 0x1F, 0x0F, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x1E, 0x1F, 0x0F, 0xFE, 0xFF, 0x0F, 0xFC, 0xFB, 0x07, 0xFC, 0xFB, 0x03, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0x00, // Code for char 8
+ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x83, 0x01, 0xF8, 0x87, 0x03, 0xFC, 0x8F, 0x07, 0xFE, 0x9F, 0x0F, 0x1E, 0x1E, 0x0F, 0x0E, 0x1C, 0x0E, 0x0E, 0x1C, 0x0E, 0x0E, 0x1C, 0x0E, 0x1E, 0x8E, 0x0F, 0xFC, 0xFF, 0x07, 0xFC, 0xFF, 0x03, 0xF8, 0xFF, 0x01, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00 // Code for char 9
+ };
+
+
+
+
+
+#endif /* LIBERATION_SANS15X21_NUMBERS_H_ */
diff --git a/lcd/Liberation_Sans17x17_Alpha.h b/lcd/Liberation_Sans17x17_Alpha.h
new file mode 100644
index 0000000..83c7264
--- /dev/null
+++ b/lcd/Liberation_Sans17x17_Alpha.h
@@ -0,0 +1,54 @@
+/*
+ * Liberation_Sans17x17_Alpha.h
+ *
+ * Created: 30/03/2012 1:29:55 AM
+ * Author: andy
+ */
+
+
+#ifndef LIBERATION_SANS17X17_ALPHA_H_
+#define LIBERATION_SANS17X17_ALPHA_H_
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Liberation_Sans17x17 46 to 90
+//GLCD FontSize : 17 x 17
+
+static const char Liberation_Sans17x17_Alpha[] PROGMEM = {
+ 0x0D, 0x00, 0x10, 0x00, 0x00, 0x1E, 0x00, 0xC0, 0x1F, 0x00, 0xF8, 0x0F, 0x00, 0xFF, 0x03, 0x00, 0x1F, 0x03, 0x00, 0x03, 0x03, 0x00, 0x1F, 0x03, 0x00, 0xFF, 0x03, 0x00, 0xF8, 0x0F, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char A
+ 0x0D, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0xFF, 0x1C, 0x00, 0xFE, 0x1F, 0x00, 0xDE, 0x0F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char B
+ 0x0D, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFC, 0x07, 0x00, 0xFE, 0x0F, 0x00, 0x0F, 0x0E, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x07, 0x1C, 0x00, 0x0E, 0x0E, 0x00, 0x0E, 0x0E, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char C
+ 0x0D, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x07, 0x1C, 0x00, 0x0E, 0x0E, 0x00, 0xFE, 0x0F, 0x00, 0xFC, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char D
+ 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x63, 0x18, 0x00, 0x03, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char E
+ 0x0B, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char F
+ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xFC, 0x07, 0x00, 0xFE, 0x0F, 0x00, 0x0E, 0x0E, 0x00, 0x07, 0x1C, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0xC3, 0x18, 0x00, 0xC3, 0x18, 0x00, 0xC7, 0x1C, 0x00, 0xCE, 0x0F, 0x00, 0xCE, 0x0F, 0x00, 0xC4, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char G
+ 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char H
+ 0x04, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char I
+ 0x0A, 0x00, 0x06, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1C, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x1C, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x0F, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char J
+ 0x0E, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xE0, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xDC, 0x03, 0x00, 0x8E, 0x07, 0x00, 0x07, 0x0E, 0x00, 0x03, 0x1C, 0x00, 0x01, 0x18, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char K
+ 0x0B, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char L
+ 0x10, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x0F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x1C, 0x00, 0x80, 0x1F, 0x00, 0xF0, 0x03, 0x00, 0x7E, 0x00, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, // Code for char M
+ 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x1E, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char N
+ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xFC, 0x07, 0x00, 0xFE, 0x0F, 0x00, 0x0E, 0x0E, 0x00, 0x07, 0x1C, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x07, 0x1C, 0x00, 0x0E, 0x0E, 0x00, 0xFE, 0x0F, 0x00, 0xFC, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char O
+ 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char P
+ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0xFC, 0x07, 0x00, 0xFE, 0x0F, 0x00, 0x0E, 0x1E, 0x00, 0x07, 0x1C, 0x00, 0x03, 0x38, 0x00, 0x03, 0xF8, 0x00, 0x03, 0xF8, 0x01, 0x07, 0xDC, 0x01, 0x0E, 0x9E, 0x01, 0xFE, 0x8F, 0x01, 0xFC, 0x87, 0x01, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char Q
+ 0x0D, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0x63, 0x00, 0x00, 0xE3, 0x00, 0x00, 0xE3, 0x03, 0x00, 0xBF, 0x0F, 0x00, 0x3E, 0x1F, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char R
+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x1C, 0x0E, 0x00, 0x3E, 0x0E, 0x00, 0x7F, 0x1C, 0x00, 0x73, 0x18, 0x00, 0x63, 0x18, 0x00, 0xE3, 0x18, 0x00, 0xE7, 0x18, 0x00, 0xCF, 0x1F, 0x00, 0xCE, 0x0F, 0x00, 0x8C, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char S
+ 0x0C, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0xFF, 0x1F, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char T
+ 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0xFF, 0x0F, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x1C, 0x00, 0xFF, 0x0F, 0x00, 0xFF, 0x0F, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char U
+ 0x0D, 0x03, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xFC, 0x01, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x18, 0x00, 0x00, 0x1F, 0x00, 0xE0, 0x0F, 0x00, 0xF8, 0x01, 0x00, 0x7F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char V
+ 0x11, 0x07, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xFF, 0x07, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x1E, 0x00, 0xC0, 0x1F, 0x00, 0xFC, 0x0F, 0x00, 0xFF, 0x00, 0x00, 0x07, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x1E, 0x00, 0xF0, 0x1F, 0x00, 0xFF, 0x07, 0x00, 0x7F, 0x00, 0x00, 0x07, 0x00, 0x00, // Code for char W
+ 0x0D, 0x01, 0x10, 0x00, 0x03, 0x18, 0x00, 0x07, 0x1C, 0x00, 0x1E, 0x0F, 0x00, 0xBC, 0x07, 0x00, 0xF0, 0x01, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xBC, 0x07, 0x00, 0x1E, 0x0F, 0x00, 0x0F, 0x1E, 0x00, 0x03, 0x18, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char X
+ 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x07, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0xC0, 0x1F, 0x00, 0xF0, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x07, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char Y
+ 0x0A, 0x00, 0x00, 0x00, 0x03, 0x1C, 0x00, 0x03, 0x1E, 0x00, 0x83, 0x1F, 0x00, 0xC3, 0x1B, 0x00, 0xF3, 0x19, 0x00, 0x7B, 0x18, 0x00, 0x3F, 0x18, 0x00, 0x0F, 0x18, 0x00, 0x07, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // Code for char Z
+ };
+
+
+
+
+#endif /* LIBERATION_SANS17X17_ALPHA_H_ */
diff --git a/lcd/Liberation_Sans20x28_Numbers.h b/lcd/Liberation_Sans20x28_Numbers.h
new file mode 100644
index 0000000..1f204b8
--- /dev/null
+++ b/lcd/Liberation_Sans20x28_Numbers.h
@@ -0,0 +1,37 @@
+/*
+ * Liberation_Sans20x28_Numbers.h
+ *
+ * Created: 30/03/2012 1:41:05 AM
+ * Author: andy
+ */
+
+
+#ifndef LIBERATION_SANS20X28_NUMBERS_H_
+#define LIBERATION_SANS20X28_NUMBERS_H_
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Liberation_Sans20x28_Numbers
+//GLCD FontSize : 20 x 28
+
+static const char Liberation_Sans20x28_Numbers[] PROGMEM = {
+ 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char .
+ 0x0A, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0xF8, 0xFF, 0x0F, 0x80, 0xFF, 0xFF, 0x03, 0xFC, 0xFF, 0x3F, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char /
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0xF8, 0xFF, 0xFF, 0x03, 0xF8, 0x01, 0xF0, 0x03, 0x7C, 0x00, 0xC0, 0x07, 0x3C, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x80, 0x07, 0x7C, 0x00, 0xC0, 0x07, 0xF8, 0x01, 0xF0, 0x03, 0xF8, 0xFF, 0xFF, 0x03, 0xF0, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0x0F, 0x00, // Code for char 0
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0xE0, 0x01, 0x80, 0x07, 0xF0, 0x01, 0x80, 0x07, 0xF0, 0x00, 0x80, 0x07, 0x78, 0x00, 0x80, 0x07, 0x78, 0x00, 0x80, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x07, // Code for char 1
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80, 0x07, 0xE0, 0x03, 0xE0, 0x07, 0xF0, 0x03, 0xF0, 0x07, 0xF0, 0x03, 0xF8, 0x07, 0xF8, 0x03, 0xFC, 0x07, 0xF8, 0x00, 0xFE, 0x07, 0x7C, 0x00, 0xBE, 0x07, 0x3C, 0x00, 0x9F, 0x07, 0x3C, 0x80, 0x8F, 0x07, 0x3C, 0x80, 0x87, 0x07, 0x3C, 0xC0, 0x87, 0x07, 0x3C, 0xE0, 0x83, 0x07, 0x7C, 0xF0, 0x81, 0x07, 0x7C, 0xF8, 0x81, 0x07, 0xF8, 0xFF, 0x80, 0x07, 0xF8, 0x7F, 0x80, 0x07, 0xF0, 0x3F, 0x80, 0x07, 0xE0, 0x1F, 0x80, 0x07, 0xC0, 0x07, 0x80, 0x07, // Code for char 2
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x30, 0x00, 0xE0, 0x01, 0xF0, 0x00, 0xF0, 0x01, 0xF0, 0x01, 0xF8, 0x01, 0xF0, 0x03, 0xF8, 0x01, 0xF0, 0x03, 0xFC, 0x00, 0xE0, 0x03, 0x7C, 0x00, 0xC0, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF8, 0x80, 0x07, 0x7C, 0xF8, 0xC1, 0x07, 0xF8, 0xFF, 0xE3, 0x07, 0xF8, 0xDF, 0xFF, 0x03, 0xF0, 0x9F, 0xFF, 0x03, 0xF0, 0x8F, 0xFF, 0x01, 0xC0, 0x07, 0xFF, 0x00, 0x00, 0x00, 0x7E, 0x00, // Code for char 3
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0xF8, 0x3D, 0x00, 0x00, 0xFE, 0x3C, 0x00, 0x00, 0x3F, 0x3C, 0x00, 0xC0, 0x1F, 0x3C, 0x00, 0xE0, 0x07, 0x3C, 0x00, 0xF8, 0x03, 0x3C, 0x00, 0xFC, 0x00, 0x3C, 0x00, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x3C, 0x00, // Code for char 4
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0xFF, 0xF0, 0x00, 0xFC, 0xFF, 0xF0, 0x01, 0xFC, 0xFF, 0xF0, 0x03, 0xFC, 0xFF, 0xF0, 0x03, 0xFC, 0xFF, 0xE0, 0x07, 0x3C, 0x78, 0xC0, 0x07, 0x3C, 0x78, 0x80, 0x07, 0x3C, 0x3C, 0x80, 0x07, 0x3C, 0x3C, 0x80, 0x07, 0x3C, 0x3C, 0x80, 0x07, 0x3C, 0x3C, 0x80, 0x07, 0x3C, 0x7C, 0xC0, 0x07, 0x3C, 0xFC, 0xE0, 0x03, 0x3C, 0xF8, 0xFF, 0x03, 0x3C, 0xF8, 0xFF, 0x01, 0x3C, 0xF0, 0xFF, 0x01, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x80, 0x1F, 0x00, // Code for char 5
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0xF8, 0xFF, 0xFF, 0x03, 0xF8, 0xE1, 0xE1, 0x03, 0x78, 0xF0, 0xC0, 0x07, 0x3C, 0x70, 0x80, 0x07, 0x3C, 0x78, 0x80, 0x07, 0x3C, 0x78, 0x80, 0x07, 0x3C, 0x78, 0x80, 0x07, 0x7C, 0x78, 0x80, 0x07, 0xFC, 0xF8, 0xC0, 0x07, 0xF8, 0xF9, 0xE1, 0x07, 0xF8, 0xF1, 0xFF, 0x03, 0xF0, 0xF1, 0xFF, 0x03, 0xE0, 0xE0, 0xFF, 0x01, 0x80, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x3F, 0x00, // Code for char 6
+ 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x3C, 0x00, 0xC0, 0x07, 0x3C, 0x00, 0xF8, 0x07, 0x3C, 0x00, 0xFF, 0x07, 0x3C, 0xC0, 0xFF, 0x07, 0x3C, 0xF0, 0xFF, 0x07, 0x3C, 0xFC, 0x3F, 0x00, 0x3C, 0xFE, 0x03, 0x00, 0xBC, 0xFF, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 7
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xC0, 0x07, 0xFF, 0x00, 0xF0, 0x8F, 0xFF, 0x01, 0xF0, 0x9F, 0xFF, 0x03, 0xF8, 0xFF, 0xFF, 0x03, 0xF8, 0xFF, 0xE3, 0x07, 0x7C, 0xF8, 0xC1, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x3C, 0xF0, 0x80, 0x07, 0x7C, 0xF8, 0xC1, 0x07, 0xF8, 0xFF, 0xC1, 0x07, 0xF8, 0xFF, 0xFF, 0x03, 0xF8, 0x9F, 0xFF, 0x03, 0xF0, 0x8F, 0xFF, 0x01, 0xC0, 0x07, 0xFF, 0x00, 0x00, 0x00, 0x7E, 0x00, // Code for char 8
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x20, 0x00, 0xE0, 0x7F, 0xF0, 0x00, 0xF0, 0xFF, 0xF0, 0x01, 0xF8, 0xFF, 0xF1, 0x03, 0xF8, 0xFF, 0xF1, 0x03, 0xF8, 0xF0, 0xE3, 0x07, 0x7C, 0xE0, 0xC3, 0x07, 0x3C, 0xC0, 0x83, 0x07, 0x3C, 0xC0, 0x83, 0x07, 0x3C, 0xC0, 0x83, 0x07, 0x3C, 0xC0, 0x83, 0x07, 0x3C, 0xC0, 0xC1, 0x07, 0x7C, 0xE0, 0xC1, 0x03, 0xF8, 0xF0, 0xF0, 0x03, 0xF8, 0xFF, 0xFF, 0x01, 0xF0, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0x07, 0x00 // Code for char 9
+ };
+
+#endif /* LIBERATION_SANS20X28_NUMBERS_H_ */
diff --git a/lcd/Liberation_Sans27x36_Numbers.h b/lcd/Liberation_Sans27x36_Numbers.h
new file mode 100644
index 0000000..06cb3d8
--- /dev/null
+++ b/lcd/Liberation_Sans27x36_Numbers.h
@@ -0,0 +1,37 @@
+/*
+ * Liberation_Sans27x36_Numbers.h
+ *
+ * Created: 30/03/2012 1:43:14 AM
+ * Author: andy
+ */
+
+
+#ifndef LIBERATION_SANS27X36_NUMBERS_H_
+#define LIBERATION_SANS27X36_NUMBERS_H_
+
+//WARNING: This Font Require X-GLCD Lib.
+// You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Liberation_Sans27x36_Numbers
+//GLCD FontSize : 27 x 36
+
+static const char Liberation_Sans27x36_Numbers[] PROGMEM = {
+ 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char .
+ 0x0D, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0xC0, 0xFF, 0xFF, 0x0F, 0x00, 0xFC, 0xFF, 0xFF, 0x0F, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xFE, 0xFF, 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char /
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0x07, 0x00, 0xFC, 0x03, 0xFC, 0x00, 0x00, 0xE0, 0x07, 0x7C, 0x00, 0x00, 0xC0, 0x07, 0x7C, 0x00, 0x00, 0xC0, 0x07, 0x7C, 0x00, 0x00, 0xC0, 0x07, 0x7C, 0x00, 0x00, 0xC0, 0x07, 0x7C, 0x00, 0x00, 0xE0, 0x07, 0xFC, 0x00, 0x00, 0xF0, 0x07, 0xF8, 0x07, 0x00, 0xFC, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x01, 0xF0, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0xFF, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 0
+ 0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0xC0, 0x07, 0xC0, 0x07, 0x00, 0xC0, 0x07, 0xE0, 0x07, 0x00, 0xC0, 0x07, 0xE0, 0x03, 0x00, 0xC0, 0x07, 0xF0, 0x01, 0x00, 0xC0, 0x07, 0xF8, 0x01, 0x00, 0xC0, 0x07, 0xF8, 0x00, 0x00, 0xC0, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 1
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0xF0, 0x07, 0xE0, 0x0F, 0x00, 0xFC, 0x07, 0xF0, 0x0F, 0x00, 0xFE, 0x07, 0xF0, 0x0F, 0x00, 0xFF, 0x07, 0xF8, 0x0F, 0x80, 0xFF, 0x07, 0xF8, 0x0F, 0xC0, 0xFF, 0x07, 0xFC, 0x03, 0xE0, 0xFF, 0x07, 0xFC, 0x00, 0xF0, 0xDF, 0x07, 0x7C, 0x00, 0xF8, 0xCF, 0x07, 0x7C, 0x00, 0xFC, 0xC7, 0x07, 0x7C, 0x00, 0xFE, 0xC3, 0x07, 0x7C, 0x00, 0xFF, 0xC1, 0x07, 0xFC, 0x80, 0xFF, 0xC0, 0x07, 0xFC, 0xC1, 0x7F, 0xC0, 0x07, 0xF8, 0xFF, 0x3F, 0xC0, 0x07, 0xF8, 0xFF, 0x1F, 0xC0, 0x07, 0xF8, 0xFF, 0x0F, 0xC0, 0x07, 0xF0, 0xFF, 0x07, 0xC0, 0x07, 0xE0, 0xFF, 0x03, 0xC0, 0x07, 0xC0, 0xFF, 0x01, 0xC0, 0x07, 0x00, 0x7F, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 2
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x0E, 0x00, 0x3E, 0x00, 0x80, 0x0F, 0x00, 0x7E, 0x00, 0xE0, 0x0F, 0x00, 0xFE, 0x00, 0xE0, 0x0F, 0x00, 0xFE, 0x01, 0xF0, 0x0F, 0x00, 0xFE, 0x03, 0xF8, 0x0F, 0x00, 0xFE, 0x03, 0xF8, 0x0F, 0x00, 0xF8, 0x03, 0xFC, 0x03, 0x00, 0xE0, 0x07, 0xFC, 0x00, 0x1F, 0xE0, 0x07, 0x7C, 0x00, 0x1F, 0xC0, 0x07, 0x7C, 0x00, 0x1F, 0xC0, 0x07, 0x7C, 0x00, 0x1F, 0xC0, 0x07, 0x7C, 0x00, 0x1F, 0xC0, 0x07, 0xFC, 0x80, 0x3F, 0xC0, 0x07, 0xFC, 0xC1, 0x3F, 0xE0, 0x07, 0xF8, 0xFF, 0x7F, 0xF0, 0x07, 0xF8, 0xFF, 0xFB, 0xFF, 0x03, 0xF8, 0xFF, 0xFB, 0xFF, 0x03, 0xF0, 0xFF, 0xF9, 0xFF, 0x03, 0xE0, 0xFF, 0xF0, 0xFF, 0x01, 0xC0, 0x7F, 0xF0, 0xFF, 0x00, 0x00, 0x3F, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 3
+ 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x9F, 0x0F, 0x00, 0x00, 0xF0, 0x8F, 0x0F, 0x00, 0x00, 0xFC, 0x83, 0x0F, 0x00, 0x00, 0xFE, 0x81, 0x0F, 0x00, 0x80, 0x7F, 0x80, 0x0F, 0x00, 0xC0, 0x3F, 0x80, 0x0F, 0x00, 0xF0, 0x0F, 0x80, 0x0F, 0x00, 0xF8, 0x07, 0x80, 0x0F, 0x00, 0xFC, 0x01, 0x80, 0x0F, 0x00, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, // Code for char 4
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0xF0, 0x0F, 0x3C, 0x00, 0xFC, 0xFF, 0x0F, 0xFC, 0x00, 0xFC, 0xFF, 0x0F, 0xFC, 0x01, 0xFC, 0xFF, 0x0F, 0xFC, 0x01, 0xFC, 0xFF, 0x0F, 0xFC, 0x03, 0xFC, 0xFF, 0x0F, 0xFC, 0x03, 0xFC, 0xFF, 0x0F, 0xF8, 0x07, 0x7C, 0xC0, 0x07, 0xE0, 0x07, 0x7C, 0xC0, 0x03, 0xC0, 0x07, 0x7C, 0xE0, 0x03, 0xC0, 0x07, 0x7C, 0xE0, 0x03, 0xC0, 0x07, 0x7C, 0xE0, 0x03, 0xC0, 0x07, 0x7C, 0xE0, 0x03, 0xC0, 0x07, 0x7C, 0xE0, 0x07, 0xE0, 0x07, 0x7C, 0xE0, 0x07, 0xE0, 0x07, 0x7C, 0xE0, 0x1F, 0xF8, 0x03, 0x7C, 0xC0, 0xFF, 0xFF, 0x03, 0x7C, 0xC0, 0xFF, 0xFF, 0x03, 0x7C, 0x80, 0xFF, 0xFF, 0x01, 0x7C, 0x80, 0xFF, 0xFF, 0x00, 0x7C, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 5
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0x03, 0xF8, 0x03, 0x1F, 0xF8, 0x03, 0xFC, 0x81, 0x0F, 0xE0, 0x07, 0xFC, 0x80, 0x07, 0xE0, 0x07, 0x7C, 0xC0, 0x07, 0xC0, 0x07, 0x7C, 0xC0, 0x07, 0xC0, 0x07, 0x7C, 0xC0, 0x07, 0xC0, 0x07, 0xFC, 0xC0, 0x07, 0xC0, 0x07, 0xFC, 0xC1, 0x0F, 0xE0, 0x07, 0xFC, 0xC3, 0x3F, 0xF8, 0x07, 0xF8, 0xC3, 0xFF, 0xFF, 0x03, 0xF8, 0x83, 0xFF, 0xFF, 0x03, 0xF0, 0x83, 0xFF, 0xFF, 0x01, 0xF0, 0x01, 0xFF, 0xFF, 0x01, 0xC0, 0x01, 0xFE, 0xFF, 0x00, 0x00, 0x01, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 6
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xE0, 0x07, 0x7C, 0x00, 0x00, 0xFC, 0x07, 0x7C, 0x00, 0x80, 0xFF, 0x07, 0x7C, 0x00, 0xE0, 0xFF, 0x07, 0x7C, 0x00, 0xF8, 0xFF, 0x07, 0x7C, 0x00, 0xFE, 0xFF, 0x07, 0x7C, 0x80, 0xFF, 0xFF, 0x07, 0x7C, 0xE0, 0xFF, 0x1F, 0x00, 0x7C, 0xF0, 0xFF, 0x01, 0x00, 0x7C, 0xFC, 0x3F, 0x00, 0x00, 0x7C, 0xFE, 0x0F, 0x00, 0x00, 0x7C, 0xFF, 0x03, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 7
+ 0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x80, 0x1F, 0xE0, 0x7F, 0x00, 0xC0, 0x7F, 0xF0, 0xFF, 0x00, 0xE0, 0xFF, 0xF8, 0xFF, 0x01, 0xF0, 0xFF, 0xFD, 0xFF, 0x01, 0xF8, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0xFF, 0x3F, 0xF0, 0x07, 0xFC, 0xE1, 0x1F, 0xE0, 0x07, 0xFC, 0xC0, 0x0F, 0xC0, 0x07, 0x7C, 0x80, 0x0F, 0xC0, 0x07, 0x7C, 0x80, 0x0F, 0xC0, 0x07, 0x7C, 0x80, 0x0F, 0xC0, 0x07, 0x7C, 0x80, 0x0F, 0xC0, 0x07, 0xFC, 0xC0, 0x0F, 0xC0, 0x07, 0xFC, 0xE1, 0x1F, 0xE0, 0x07, 0xFC, 0xFF, 0x3F, 0xF0, 0x07, 0xF8, 0xFF, 0xFD, 0xFF, 0x03, 0xF8, 0xFF, 0xFD, 0xFF, 0x03, 0xF0, 0xFF, 0xFD, 0xFF, 0x01, 0xF0, 0xFF, 0xF8, 0xFF, 0x01, 0xC0, 0x7F, 0xF8, 0xFF, 0x00, 0x80, 0x1F, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char 8
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x18, 0x00, 0xE0, 0xFF, 0x0F, 0x78, 0x00, 0xF0, 0xFF, 0x1F, 0xF8, 0x00, 0xF0, 0xFF, 0x3F, 0xFC, 0x01, 0xF8, 0xFF, 0x3F, 0xFC, 0x03, 0xF8, 0xFF, 0x7F, 0xFC, 0x03, 0xFC, 0x83, 0x7F, 0xFC, 0x07, 0xFC, 0x00, 0x7E, 0xF0, 0x07, 0x7C, 0x00, 0x7C, 0xE0, 0x07, 0x7C, 0x00, 0x7C, 0xC0, 0x07, 0x7C, 0x00, 0x7C, 0xC0, 0x07, 0x7C, 0x00, 0x3C, 0xC0, 0x07, 0xFC, 0x00, 0x3C, 0xE0, 0x07, 0xFC, 0x00, 0x1E, 0xF0, 0x07, 0xF8, 0x03, 0x1F, 0xF8, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0x01, 0xF0, 0xFF, 0xFF, 0xFF, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // Code for char 9
+ };
+
+#endif /* LIBERATION_SANS27X36_NUMBERS_H_ */
diff --git a/lcd/ST7565R.c b/lcd/ST7565R.c
new file mode 100644
index 0000000..9b91610
--- /dev/null
+++ b/lcd/ST7565R.c
@@ -0,0 +1,213 @@
+/**
+ * \file ST7565R.c
+ * \brief Functions relating to ST7565R.
+ * \author Andy Gock
+ * \see glcd.h
+ */
+
+#include "ST7565R.h"
+#include "glcd_spi.h"
+
+void glcd_command(uint8_t c)
+{
+ GLCD_A0_LOW();
+ glcd_spi_write(c);
+}
+
+void glcd_data(uint8_t c)
+{
+ GLCD_A0_HIGH();
+ glcd_spi_write(c);
+}
+
+void glcd_set_contrast(uint8_t val) {
+ /* Can set a 6-bit value (0 to 63) */
+
+ /* Must send this command byte before setting the contrast */
+ glcd_command(0x81);
+
+ /* Set the contrat value ("electronic volumne register") */
+ if (val > 63) {
+ glcd_command(63);
+ } else {
+ glcd_command(val);
+ }
+ return;
+}
+
+void glcd_power_down(void)
+{
+ /* Command sequence as in ST7565 datasheet */
+ glcd_command(0xac); // Static indicator off
+ glcd_command(0x00); // Static indicator register, not blinking
+ glcd_command(0xae); // Display OFF
+ glcd_command(0xa5); // Display all points ON
+
+ /* Display is now in sleep mode */
+}
+
+void glcd_power_up(void)
+{
+ glcd_command(0xa4); // Display all points OFF
+ glcd_command(0xad); // Static indicator ON
+ glcd_command(0x00); // Static indicator register, not Blinking
+ glcd_command(0xaf);
+
+ return;
+}
+
+void glcd_set_y_address(uint8_t y)
+{
+ glcd_command(ST7565R_PAGE_ADDRESS_SET | (0x0F & y)); /* 0x0F = 0b00001111 */
+}
+
+void glcd_set_x_address(uint8_t x)
+{
+ glcd_set_column_upper(x);
+ glcd_set_column_lower(x);
+}
+
+void glcd_all_on(void)
+{
+ glcd_command(ST7565R_DISPLAY_ALL_ON);
+}
+
+void glcd_normal(void)
+{
+ glcd_command(ST7565R_DISPLAY_NORMAL);
+}
+
+void glcd_set_column_upper(uint8_t addr)
+{
+ glcd_command(ST7565R_COLUMN_ADDRESS_SET_UPPER | (addr >> 4));
+}
+
+void glcd_set_column_lower(uint8_t addr)
+{
+ glcd_command(ST7565R_COLUMN_ADDRESS_SET_LOWER | (0x0f & addr));
+}
+
+void glcd_set_start_line(uint8_t addr)
+{
+ glcd_command( ST7565R_SET_START_LINE | (0x3F & addr)); /* 0x3F == 0b00111111 */
+}
+
+/** Clear the display immediately, does not buffer */
+void glcd_clear_now(void)
+{
+ uint8_t page;
+ for (page = 0; page < GLCD_NUMBER_OF_BANKS1; page++) {
+ uint8_t col;
+ glcd_set_y_address(page);
+ glcd_set_x_address(0);
+ for (col = 0; col < GLCD_NUMBER_OF_COLS1; col++) {
+ glcd_data(0);
+ }
+ }
+}
+
+void glcd_pattern(void)
+{
+ uint8_t page;
+ for (page = 0; page < GLCD_NUMBER_OF_BANKS1; page++) {
+ uint8_t col;
+ glcd_set_y_address(page);
+ glcd_set_x_address(0);
+ for (col = 0; col < GLCD_NUMBER_OF_COLS1; col++) {
+ glcd_data( (col / 8 + 2) % 2 == 1 ? 0xff : 0x00 );
+ }
+ }
+}
+
+
+#define GLCD_INIT_NHD_C12864WC_FSW_FBW_3V3_M
+uint8_t contrast = 37;
+void glcd_ST7565R_init(void) {
+
+#if defined(GLCD_INIT_NHD_C12832A1Z_FSW_FBW_3V3)
+
+ /* Init sequence based on datasheet example code for NHD-C12832A1Z-FSW-FBW-3V3 */
+ /* Datasheet says max SCK frequency 20MHz for this LCD */
+ /* We use "reverse direction" for common output mode, as opposed to datasheet specifying "normal direction" */
+
+ glcd_command(0xa0); /* ADC select in normal mode */
+ glcd_command(0xae); /* Display OFF */
+ glcd_command(0xc8); /* Common output mode select: reverse direction (last 3 bits are ignored) */
+ glcd_command(0xa2); /* LCD bias set at 1/9 */
+ glcd_command(0x2f); /* Power control set to operating mode: 7 */
+ glcd_command(0x21); /* Internal resistor ratio, set to: 1 */
+ glcd_set_contrast(40); /* Set contrast, value experimentally determined, can set to 6-bit value, 0 to 63 */
+ glcd_command(0xaf); /* Display on */
+
+#elif defined(GLCD_INIT_NHD_C12864A1Z_FSW_FBW_HTT)
+
+ /* Init sequence based on datasheet example code for NHD-C12864A1Z-FSW-FBW-HTT */
+ /* Datasheet says max SCK frequency 2.5MHz for this LCD */
+ /* We use "reverse direction" for common output mode, as opposed to datasheet specifying "normal direction" */
+
+ glcd_command(0xa0); /* ADC select in normal mode */
+ glcd_command(0xae); /* Display OFF */
+ glcd_command(0xc8); /* Common output mode select: reverse direction (last 3 bits are ignored) */
+ glcd_command(0xa2); /* LCD bias set at 1/9 */
+ glcd_command(0x2f); /* Power control set to operating mode: 7 */
+ glcd_command(0x26); /* Internal resistor ratio, set to: 6 */
+ glcd_set_contrast(30); /* Set contrast, value experimentally determined */
+ glcd_command(0xaf); /* Display on */
+
+#elif defined(GLCD_INIT_NHD_C12864WC_FSW_FBW_3V3_M)
+
+ /* Init sequence for NHD-C12864WC-FSW-FBW-3V3-M */
+
+ glcd_command(ST7565R_RESET); /* Internal reset */
+ glcd_command(0xa2); /* 1/9 bias */
+ glcd_command(0xa0); /* ADC select, normal */
+ glcd_command(0xc8); /* Com output reverse */
+ glcd_command(0xa4); /* Display all points normal */
+ glcd_command(0x40); /* Display start line set */
+ glcd_command(0x25); /* Internal resistor ratio */
+ glcd_set_contrast(contrast); /* Set contrast value, experimentally determined, value 0 to 63 */
+ glcd_command(0x2f); /* Power controller set */
+ glcd_command(0xaf); /* Display on */
+
+#elif defined(GLCD_INIT_ZOLEN_12864_FFSSWE_NAA)
+ /* Init sequence for Zolen 128x64 module with
+ * size 40x35mm. Chip ST7567 */
+
+ glcd_command(0xa0); /* ADC select in normal mode */
+ glcd_command(0xae); /* Display OFF */
+ glcd_command(0xc8); /* Common output mode select: reverse direction (last 3 bits are ignored) */
+ glcd_command(0xa3); /* LCD bias set at 1/9 */
+ glcd_command(0x2f); /* Power control set to operating mode: 7 */
+ glcd_command(0x24); /* Internal resistor ratio, set to: 6 */
+ glcd_set_contrast(45); /* Set contrast, value experimentally determined, value 0 to 63 */
+ glcd_command(0xaf); /* Display on */
+
+#elif defined(GLCD_MY)
+
+ glcd_command(0xa2); /* 1/9 bias */
+ glcd_command(0xa0); /* Select SEG Normal Direction */
+ glcd_command(0xc0); /* Select COM Normal Direction */
+ glcd_command(0x24); /* Select Regulation Ration=5.0 */
+ glcd_command(0x81); /* Set EV Command */
+ glcd_command(0x20); /* Set EV Command */
+ glcd_command(0x2c); /* Power controller set */
+ glcd_command(0x2e); /* Power controller set */
+ glcd_command(0x2f); /* Power controller set */
+ glcd_command(0xaf); /* Display on */
+#else
+
+ /* Default init sequence */
+ /* Currently just set the same as GLCD_INIT_NHD_C12864A1Z_FSW_FBW_HTT */
+
+ glcd_command(0xa0); /* ADC select in normal mode */
+ glcd_command(0xae); /* Display OFF */
+ glcd_command(0xc8); /* Common output mode select: reverse direction (last 3 bits are ignored) */
+ glcd_command(0xa2); /* LCD bias set at 1/9 */
+ glcd_command(0x2f); /* Power control set to operating mode: 7 */
+ glcd_command(0x26); /* Internal resistor ratio, set to: 6 */
+ glcd_set_contrast(20); /* Set contrast, value experimentally determined, value 0 to 63 */
+ glcd_command(0xaf); /* Display on */
+
+#endif
+
+}
diff --git a/lcd/ST7565R.h b/lcd/ST7565R.h
new file mode 100644
index 0000000..1c2b06a
--- /dev/null
+++ b/lcd/ST7565R.h
@@ -0,0 +1,108 @@
+/**
+ * \file ST7565R.h
+ * \brief Constants relating to ST7565R LCD controller.
+ * \author Andy Gock
+ *
+ * Constants and functions specific to ST7565R.
+ * Tested with Newhaven Display model NHD-C12864WC-FSW-FBW-3V3-M
+ *
+ * \todo Need to move functions to be controller independent
+ *
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef ST7565R_H_
+#define ST7565R_H_
+
+#include "stdint.h"
+
+/* Commands */
+#define ST7565R_DISPLAY_ON 0xAF /* 0b10101111 */
+#define ST7565R_DISPLAY_OFF 0xAE /* 0b10101110 */
+#define ST7565R_PAGE_ADDRESS_SET 0xB0 /* 0b10110000 */
+#define ST7565R_COLUMN_ADDRESS_SET_LOWER 0x00
+#define ST7565R_COLUMN_ADDRESS_SET_UPPER 0x10
+#define ST7565R_DISPLAY_NORMAL 0xA4 /* 0b10100100 */
+#define ST7565R_DISPLAY_ALL_ON 0xA5 /* 0b10100101 */
+#define ST7565R_NORMAL 0xA0 /* 0b10100000 */
+#define ST7565R_REVERSE 0xA1 /* 0b10100001 */
+#define ST7565R_RESET 0xE2 /* 0b11100010 */
+#define ST7565R_SET_START_LINE (1<<6)
+
+ /**
+ * User specified GLCD width in pixels
+ * Set to 0 for automatic assignment based on controller.
+ */
+#define GLCD_LCD_WIDTH1 128
+
+ /**
+ * User specified GLCD height in pixels
+ * Set to 0 for automatic assignment based on controller.
+ */
+
+#define GLCD_LCD_HEIGHT1 64
+
+
+#define GLCD_NUMBER_OF_BANKS1 (GLCD_LCD_WIDTH1 / 8)
+#define GLCD_NUMBER_OF_COLS1 GLCD_LCD_WIDTH1
+
+/* These functions only available on ST7565 implementation (for now) */
+
+/* Private functions */
+void glcd_set_column_upper(uint8_t addr);
+void glcd_set_column_lower(uint8_t addr);
+
+/** All display points on (native) */
+void glcd_all_on(void);
+
+/** Set to normal mode */
+void glcd_normal(void);
+
+/** Set start line/page */
+void glcd_set_start_line(uint8_t addr);
+
+/** Clear the display immediately, does not buffer */
+void glcd_clear_now(void);
+
+/** Show a black and white line pattern on the display */
+void glcd_pattern(void);
+
+/** Init ST7565R controller / display */
+void glcd_ST7565R_init(void);
+
+void glcd_write(void);
+
+void glcd_set_y_address(uint8_t y);
+
+void glcd_set_x_address(uint8_t x);
+
+void glcd_data(uint8_t c);
+
+#endif /* ST7565R_H_ */
diff --git a/lcd/font5x7.h b/lcd/font5x7.h
new file mode 100644
index 0000000..b800fbf
--- /dev/null
+++ b/lcd/font5x7.h
@@ -0,0 +1,118 @@
+/*
+ * font5x7.h
+ *
+ * Created: 28/03/2012 1:52:20 AM
+ * Author: andy
+ */
+
+// Title : Graphic LCD Font (Ascii Charaters)
+// Author : Pascal Stang
+
+#ifndef FONT5X7_H_
+#define FONT5X7_H_
+
+// standard ascii 5x7 font
+// defines ascii characters 0x20-0x7F (32-127)
+static const char Font5x7[] PROGMEM = {
+ 0x00, 0x00, 0x00, 0x00, 0x00,// (space)
+ 0x00, 0x00, 0x5F, 0x00, 0x00,// !
+ 0x00, 0x07, 0x00, 0x07, 0x00,// "
+ 0x14, 0x7F, 0x14, 0x7F, 0x14,// #
+ 0x24, 0x2A, 0x7F, 0x2A, 0x12,// $
+ 0x23, 0x13, 0x08, 0x64, 0x62,// %
+ 0x36, 0x49, 0x55, 0x22, 0x50,// &
+ 0x00, 0x05, 0x03, 0x00, 0x00,// '
+ 0x00, 0x1C, 0x22, 0x41, 0x00,// (
+ 0x00, 0x41, 0x22, 0x1C, 0x00,// )
+ 0x08, 0x2A, 0x1C, 0x2A, 0x08,// *
+ 0x08, 0x08, 0x3E, 0x08, 0x08,// +
+ 0x00, 0x50, 0x30, 0x00, 0x00,// ,
+ 0x08, 0x08, 0x08, 0x08, 0x08,// -
+ 0x00, 0x60, 0x60, 0x00, 0x00,// .
+ 0x20, 0x10, 0x08, 0x04, 0x02,// /
+ 0x3E, 0x51, 0x49, 0x45, 0x3E,// 0
+ 0x00, 0x42, 0x7F, 0x40, 0x00,// 1
+ 0x42, 0x61, 0x51, 0x49, 0x46,// 2
+ 0x21, 0x41, 0x45, 0x4B, 0x31,// 3
+ 0x18, 0x14, 0x12, 0x7F, 0x10,// 4
+ 0x27, 0x45, 0x45, 0x45, 0x39,// 5
+ 0x3C, 0x4A, 0x49, 0x49, 0x30,// 6
+ 0x01, 0x71, 0x09, 0x05, 0x03,// 7
+ 0x36, 0x49, 0x49, 0x49, 0x36,// 8
+ 0x06, 0x49, 0x49, 0x29, 0x1E,// 9
+ 0x00, 0x36, 0x36, 0x00, 0x00,// :
+ 0x00, 0x56, 0x36, 0x00, 0x00,// ;
+ 0x00, 0x08, 0x14, 0x22, 0x41,// <
+ 0x14, 0x14, 0x14, 0x14, 0x14,// =
+ 0x41, 0x22, 0x14, 0x08, 0x00,// >
+ 0x02, 0x01, 0x51, 0x09, 0x06,// ?
+ 0x32, 0x49, 0x79, 0x41, 0x3E,// @
+ 0x7E, 0x11, 0x11, 0x11, 0x7E,// A
+ 0x7F, 0x49, 0x49, 0x49, 0x36,// B
+ 0x3E, 0x41, 0x41, 0x41, 0x22,// C
+ 0x7F, 0x41, 0x41, 0x22, 0x1C,// D
+ 0x7F, 0x49, 0x49, 0x49, 0x41,// E
+ 0x7F, 0x09, 0x09, 0x01, 0x01,// F
+ 0x3E, 0x41, 0x41, 0x51, 0x32,// G
+ 0x7F, 0x08, 0x08, 0x08, 0x7F,// H
+ 0x00, 0x41, 0x7F, 0x41, 0x00,// I
+ 0x20, 0x40, 0x41, 0x3F, 0x01,// J
+ 0x7F, 0x08, 0x14, 0x22, 0x41,// K
+ 0x7F, 0x40, 0x40, 0x40, 0x40,// L
+ 0x7F, 0x02, 0x04, 0x02, 0x7F,// M
+ 0x7F, 0x04, 0x08, 0x10, 0x7F,// N
+ 0x3E, 0x41, 0x41, 0x41, 0x3E,// O
+ 0x7F, 0x09, 0x09, 0x09, 0x06,// P
+ 0x3E, 0x41, 0x51, 0x21, 0x5E,// Q
+ 0x7F, 0x09, 0x19, 0x29, 0x46,// R
+ 0x46, 0x49, 0x49, 0x49, 0x31,// S
+ 0x01, 0x01, 0x7F, 0x01, 0x01,// T
+ 0x3F, 0x40, 0x40, 0x40, 0x3F,// U
+ 0x1F, 0x20, 0x40, 0x20, 0x1F,// V
+ 0x7F, 0x20, 0x18, 0x20, 0x7F,// W
+ 0x63, 0x14, 0x08, 0x14, 0x63,// X
+ 0x03, 0x04, 0x78, 0x04, 0x03,// Y
+ 0x61, 0x51, 0x49, 0x45, 0x43,// Z
+ 0x00, 0x00, 0x7F, 0x41, 0x41,// [
+ 0x02, 0x04, 0x08, 0x10, 0x20,// "\"
+ 0x41, 0x41, 0x7F, 0x00, 0x00,// ]
+ 0x04, 0x02, 0x01, 0x02, 0x04,// ^
+ 0x40, 0x40, 0x40, 0x40, 0x40,// _
+ 0x00, 0x01, 0x02, 0x04, 0x00,// `
+ 0x20, 0x54, 0x54, 0x54, 0x78,// a
+ 0x7F, 0x48, 0x44, 0x44, 0x38,// b
+ 0x38, 0x44, 0x44, 0x44, 0x20,// c
+ 0x38, 0x44, 0x44, 0x48, 0x7F,// d
+ 0x38, 0x54, 0x54, 0x54, 0x18,// e
+ 0x08, 0x7E, 0x09, 0x01, 0x02,// f
+ 0x08, 0x14, 0x54, 0x54, 0x3C,// g
+ 0x7F, 0x08, 0x04, 0x04, 0x78,// h
+ 0x00, 0x44, 0x7D, 0x40, 0x00,// i
+ 0x20, 0x40, 0x44, 0x3D, 0x00,// j
+ 0x00, 0x7F, 0x10, 0x28, 0x44,// k
+ 0x00, 0x41, 0x7F, 0x40, 0x00,// l
+ 0x7C, 0x04, 0x18, 0x04, 0x78,// m
+ 0x7C, 0x08, 0x04, 0x04, 0x78,// n
+ 0x38, 0x44, 0x44, 0x44, 0x38,// o
+ 0x7C, 0x14, 0x14, 0x14, 0x08,// p
+ 0x08, 0x14, 0x14, 0x18, 0x7C,// q
+ 0x7C, 0x08, 0x04, 0x04, 0x08,// r
+ 0x48, 0x54, 0x54, 0x54, 0x20,// s
+ 0x04, 0x3F, 0x44, 0x40, 0x20,// t
+ 0x3C, 0x40, 0x40, 0x20, 0x7C,// u
+ 0x1C, 0x20, 0x40, 0x20, 0x1C,// v
+ 0x3C, 0x40, 0x30, 0x40, 0x3C,// w
+ 0x44, 0x28, 0x10, 0x28, 0x44,// x
+ 0x0C, 0x50, 0x50, 0x50, 0x3C,// y
+ 0x44, 0x64, 0x54, 0x4C, 0x44,// z
+ 0x00, 0x08, 0x36, 0x41, 0x00,// {
+ 0x00, 0x00, 0x7F, 0x00, 0x00,// |
+ 0x00, 0x41, 0x36, 0x08, 0x00,// }
+ 0x08, 0x08, 0x2A, 0x1C, 0x08,// ->
+ 0x08, 0x1C, 0x2A, 0x08, 0x08 // <-
+};
+
+
+
+
+#endif /* FONT5X7_H_ */
diff --git a/lcd/glcd.c b/lcd/glcd.c
new file mode 100644
index 0000000..a0f1461
--- /dev/null
+++ b/lcd/glcd.c
@@ -0,0 +1,242 @@
+/**
+ \file glcd.c
+ \author Andy Gock
+ \brief Basic GLCD functions affecting bounding box manipulation,
+ clearing of screen and buffers, and basic scroll functions.
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <string.h>
+#include <stdio.h>
+#include "glcd.h"
+
+/** \addtogroup GlobalVars Global Variables
+ * @{
+ */
+
+/**
+ * Screen buffer
+ *
+ * Requires at least one bit for every pixel (e.g 504 bytes for 48x84 LCD)
+ */
+uint8_t glcd_buffer[GLCD_LCD_WIDTH * GLCD_LCD_HEIGHT / 8];
+
+/**
+ * Keeps track of bounding box of area on LCD which need to be
+ * updated next reresh cycle
+ */
+glcd_BoundingBox_t glcd_bbox;
+
+/**
+ * Pointer to screen buffer currently in use.
+ */
+uint8_t* glcd_buffer_selected;
+
+uint8_t glcd_disp_reverse_en = 0;
+
+/**
+ * Pointer to bounding box currently in use.
+ */
+glcd_BoundingBox_t* glcd_bbox_selected;
+
+/** @} */
+
+void glcd_set_reverse_sta(uint8_t sta)
+{
+ if(!sta)
+ glcd_disp_reverse_en = 0;
+ else
+ glcd_disp_reverse_en = 1;
+}
+
+uint8_t glcd_get_reverse_sta(void)
+{
+ return glcd_disp_reverse_en;
+}
+
+void glcd_update_bbox(uint8_t xmin, uint8_t ymin, uint8_t xmax, uint8_t ymax)
+{
+ /* Keep and check bounding box within limits of LCD screen dimensions */
+ if(xmin > (GLCD_LCD_WIDTH-1))
+ {
+ xmin = GLCD_LCD_WIDTH-1;
+ }
+ if(xmax > (GLCD_LCD_WIDTH-1))
+ {
+ xmax = GLCD_LCD_WIDTH-1;
+ }
+
+ if(ymin > (GLCD_LCD_HEIGHT-1))
+ {
+ ymin = GLCD_LCD_HEIGHT-1;
+ }
+ if(ymax > (GLCD_LCD_HEIGHT-1))
+ {
+ ymax = GLCD_LCD_HEIGHT-1;
+ }
+
+ /* Update the bounding box size */
+ if(xmin < glcd_bbox_selected->x_min)
+ {
+ glcd_bbox_selected->x_min = xmin;
+ }
+ if(xmax > glcd_bbox_selected->x_max)
+ {
+ glcd_bbox_selected->x_max = xmax;
+ }
+ if(ymin < glcd_bbox_selected->y_min)
+ {
+ glcd_bbox_selected->y_min = ymin;
+ }
+ if(ymax > glcd_bbox_selected->y_max)
+ {
+ glcd_bbox_selected->y_max = ymax;
+ }
+}
+
+void glcd_reset_bbox()
+{
+ /* Used after physically writing to the LCD */
+ glcd_bbox_selected->x_min = GLCD_LCD_WIDTH - 1;
+ glcd_bbox_selected->x_max = 0;
+ glcd_bbox_selected->y_min = GLCD_LCD_HEIGHT -1;
+ glcd_bbox_selected->y_max = 0;
+}
+
+void glcd_bbox_reset()
+{
+ glcd_reset_bbox();
+}
+
+void glcd_bbox_refresh()
+{
+ /* Marks bounding box as entire screen, so on next glcd_write(), it writes the entire buffer to the LCD */
+ glcd_bbox_selected->x_min = 0;
+ glcd_bbox_selected->x_max = GLCD_LCD_WIDTH - 1;
+ glcd_bbox_selected->y_min = 0;
+ glcd_bbox_selected->y_max = GLCD_LCD_HEIGHT -1;
+}
+
+void glcd_clear(void)
+{
+ memset(glcd_buffer_selected, 0x00, GLCD_LCD_WIDTH * GLCD_LCD_HEIGHT / 8);
+ glcd_update_bbox(0,0,GLCD_LCD_WIDTH - 1,GLCD_LCD_HEIGHT - 1);
+ glcd_write();
+}
+
+void glcd_clear_buffer(void)
+{
+ memset(glcd_buffer_selected, 0x00, GLCD_LCD_WIDTH * GLCD_LCD_HEIGHT / 8);
+ glcd_update_bbox(0,0,GLCD_LCD_WIDTH - 1,GLCD_LCD_HEIGHT - 1);
+}
+
+void glcd_select_screen(uint8_t* buffer, glcd_BoundingBox_t* bbox)
+{
+ glcd_buffer_selected = buffer;
+ glcd_bbox_selected = bbox;
+}
+
+void glcd_scroll(int8_t x, int8_t y)
+{
+ /** \todo Skeleton */
+
+ uint8_t row;
+
+ for(row=0; row<(GLCD_LCD_HEIGHT / 8); row++)
+ {
+ uint8_t x;
+ for(x=0; x<GLCD_LCD_WIDTH; x++)
+ {
+
+ }
+ }
+}
+
+void glcd_scroll_line(void)
+{
+ uint8_t y;
+ uint8_t number_of_rows = GLCD_LCD_HEIGHT / 8;
+ for(y=0; y<number_of_rows; y++)
+ {
+ if(y < (number_of_rows - 1))
+ {
+ /* All lines except the last */
+ memcpy(glcd_buffer_selected + y*GLCD_LCD_WIDTH,
+ glcd_buffer_selected + y*GLCD_LCD_WIDTH + GLCD_LCD_WIDTH, GLCD_LCD_WIDTH);
+ }
+ else
+ {
+ /* Last line, clear it */
+ memset(glcd_buffer_selected + (number_of_rows - 1)*GLCD_LCD_WIDTH, 0x00, GLCD_LCD_WIDTH);
+ }
+ }
+ glcd_update_bbox(0,0,GLCD_LCD_WIDTH - 1,GLCD_LCD_HEIGHT - 1);
+}
+
+void glcd_init(void)
+{
+ glcd_HW_init();
+
+ glcd_select_screen(glcd_buffer,&glcd_bbox);
+ glcd_clear();
+}
+void glcd_write()
+{
+
+ uint8_t bank;
+
+ for(bank = 0; bank < GLCD_NUMBER_OF_BANKS; bank++)
+ {
+ /* Each bank is a single row 8 bits tall */
+ uint8_t column;
+
+ if(glcd_bbox_selected->y_min >= (bank+1)*8)
+ {
+ continue; /* Skip the entire bank */
+ }
+
+ if(glcd_bbox_selected->y_max < bank*8)
+ {
+ break; /* No more banks need updating */
+ }
+
+ glcd_set_y_address(bank);
+ glcd_set_x_address(glcd_bbox_selected->x_min);
+
+ for(column = glcd_bbox_selected->x_min; column <= glcd_bbox_selected->x_max; column++)
+ {
+ glcd_data(glcd_buffer_selected[GLCD_NUMBER_OF_COLS * bank + column]);
+ }
+ }
+
+ glcd_reset_bbox();
+
+}
+
diff --git a/lcd/glcd.h b/lcd/glcd.h
new file mode 100644
index 0000000..1577878
--- /dev/null
+++ b/lcd/glcd.h
@@ -0,0 +1,251 @@
+/**
+ \file glcd.h
+ \brief GLCD Library main header file. This file must be included into project.
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _GLCD_H
+#define _GLCD_H
+
+#include "stm32f10x.h"
+#include "glcd_spi.h"
+#include "ST7565R.h"
+
+
+extern void delay_ms(uint32_t ms);
+#define PROGMEM
+
+
+/* Macros */
+
+#define swap(a, b) { uint8_t t = a; a = b; b = t; }
+
+/* Defining new types */
+
+/**
+ * Font table type
+ */
+typedef enum {
+ STANG,
+ MIKRO,
+ GLCD_UTILS
+} font_table_type_t;
+
+/**
+ * Bounding box for pixels that need to be updated
+ */
+typedef struct {
+ uint8_t x_min;
+ uint8_t y_min;
+ uint8_t x_max;
+ uint8_t y_max;
+} glcd_BoundingBox_t;
+
+#include <stdint.h>
+#include "glcd_graphics.h"
+#include "glcd_graphs.h"
+#include "glcd_text_tiny.h"
+#include "glcd_text.h"
+#include "unit_tests.h"
+#include "font5x7.h"
+#include "Earthbound_12x19_48to57.h"
+#include "Liberation_Sans15x21_Numbers.h"
+
+/**
+ * \name Colour Constants
+ * @{
+ */
+#define BLACK 1
+#define WHITE 0
+/**@}*/
+
+/**
+ * \name LCD Dimensions
+ * @{
+ */
+#if !defined(GLCD_LCD_WIDTH) || !defined(GLCD_LCD_HEIGHT)
+
+ /**
+ * User specified GLCD width in pixels
+ * Set to 0 for automatic assignment based on controller.
+ */
+ #define GLCD_LCD_WIDTH 128
+
+ /**
+ * User specified GLCD height in pixels
+ * Set to 0 for automatic assignment based on controller.
+ */
+
+ #define GLCD_LCD_HEIGHT 64
+
+ /* Automatic assignment of width and height, if required. */
+ #if !GLCD_LCD_WIDTH && !GLCD_LCD_HEIGHT
+ #undef GLCD_LCD_WIDTH
+ #undef GLCD_LCD_HEIGHT
+ #if defined(GLCD_CONTROLLER_PCD8544)
+ /* 84x48 is standard for the popular Nokia LCD */
+ #define GLCD_LCD_WIDTH 84
+ #define GLCD_LCD_HEIGHT 48
+ #elif defined(GLCD_CONTROLLER_ST7565R) || defined(GLCD_CONTROLLER_NT75451)
+ /* 128x64 is the most popular for this, so we'll use that as default */
+ #define GLCD_LCD_WIDTH 128
+ #define GLCD_LCD_HEIGHT 64
+ #else
+ #define GLCD_LCD_WIDTH 128
+ #define GLCD_LCD_HEIGHT 64
+ #endif
+ #endif
+
+#endif /* !defined(GLCD_LCD_WIDTH) || !defined(GLCD_LCD_HEIGHT) */
+
+/*
+ * GLCD_NUMBER_OF_BANKS is typically GLCD_LCD_HEIGHT/8
+ * Don't adjust these below unless required.
+ */
+#define GLCD_NUMBER_OF_BANKS (GLCD_LCD_WIDTH / 8)
+#define GLCD_NUMBER_OF_COLS GLCD_LCD_WIDTH
+
+/**@}*/
+
+#if !defined(GLCD_RESET_TIME)
+ /** Reset duration by glcd_reset(), in milliseconds */
+ #define GLCD_RESET_TIME 2
+#endif
+/*
+ * Set to custom value, or leave at 0 for automatic assignment.
+ * For custom dimensions, users can define this in their compiler options.
+ */
+
+/* Global variables used for GLCD library */
+extern uint8_t glcd_buffer[GLCD_LCD_WIDTH * GLCD_LCD_HEIGHT / 8];
+extern glcd_BoundingBox_t glcd_bbox;
+extern uint8_t *glcd_buffer_selected;
+extern glcd_BoundingBox_t *glcd_bbox_selected;
+
+/** \name Base Functions
+ * @{
+ */
+
+/**
+ * Update bounding box.
+ *
+ * The bounding box defines a rectangle in which needs to be refreshed next time
+ * glcd_write() is called. glcd_write() only writes to those pixels inside the bounding box plus any
+ * surrounding pixels which are required according to the bank/column write method of the controller.
+ *
+ * Define a rectangle here, and it will be <em>added</em> to the existing bounding box.
+ *
+ * \param xmin Minimum x value of rectangle
+ * \param ymin Minimum y value of rectangle
+ * \param xmax Maximum x value of rectangle
+ * \param ymax Maximum y value of rectangle
+ * \see glcd_bbox
+ * \see glcd_bbox_selected
+ */
+void glcd_update_bbox(uint8_t xmin, uint8_t ymin, uint8_t xmax, uint8_t ymax);
+
+/**
+ * Reset the bounding box.
+ * After resetting the bounding box, no pixels are marked as needing refreshing.
+ */
+void glcd_reset_bbox(void);
+
+/**
+ * Same as glcd_reset_bbox()
+ */
+void glcd_bbox_reset(void);
+
+/**
+ * Marks the entire display for re-writing.
+ */
+void glcd_bbox_refresh(void);
+
+/**
+ * Clear the display. This will clear the buffer and physically write and commit it to the LCD
+ */
+void glcd_clear(void);
+
+/**
+ * Clear the display buffer only. This does not physically write the changes to the LCD
+ */
+void glcd_clear_buffer(void);
+
+/**
+ * Select screen buffer and bounding box structure.
+ * This should be selected at initialisation. There are future plans to support multiple screen buffers
+ * but this not yet available.
+ * \param buffer Pointer to screen buffer
+ * \param bbox Pointer to bounding box object.
+ * \see glcd_BoundingBox_t
+ */
+void glcd_select_screen(uint8_t *buffer, glcd_BoundingBox_t *bbox);
+
+/**
+ * Scroll entire screne buffer by x and y pixels. (not implemented yet)
+ * \note Items scrolled off the extents of the display dimensions will be lost.
+ *
+ * \param x X distance to scroll
+ * \param y Y distance to scroll
+ */
+void glcd_scroll(int8_t x, int8_t y);
+
+/**
+ * Scroll screen buffer up by 8 pixels.
+ * This is designed to be used in conjunciton with tiny text functions which are 8 bits high.
+ * \see Tiny Text
+ */
+void glcd_scroll_line(void);
+
+void glcd_set_reverse_sta(uint8_t sta);
+uint8_t glcd_get_reverse_sta(void);
+
+void glcd_HW_init(void);
+
+void glcd_write(void);
+
+/** @}*/
+
+typedef struct {
+ const char *font_table;
+ uint8_t width;
+ uint8_t height;
+ char start_char;
+ char end_char;
+ font_table_type_t table_type;
+} glcd_FontConfig_t;
+
+
+
+extern uint8_t *glcd_buffer_selected;
+extern glcd_BoundingBox_t *glcd_bbox_selected;
+extern glcd_FontConfig_t font_current;
+
+#endif
diff --git a/lcd/glcd_graphics.h b/lcd/glcd_graphics.h
new file mode 100644
index 0000000..376565f
--- /dev/null
+++ b/lcd/glcd_graphics.h
@@ -0,0 +1,169 @@
+/**
+ \file glcd_graphics.h
+ \brief Graphics routines
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef GLCD_GRAPHICS_H_
+#define GLCD_GRAPHICS_H_
+
+/** \addtogroup Graphics Graphics
+ * Graphics specific functions such as drawing lines, circles, rectangles etc.
+ * @{
+ */
+
+/**
+ * Set pixel to specified colour
+ * \param x X-coordinate
+ * \param y Y-coordinate
+ * \param color Colour to set pixel
+ * \see ColourConstants
+ */
+void glcd_set_pixel(uint8_t x, uint8_t y, uint8_t color);
+
+/**
+ * Get state of pixel from specified location
+ * \param x X-coordinate
+ * \param y Y-coordinate
+ * \return Colour
+ */
+uint8_t glcd_get_pixel(uint8_t x, uint8_t y);
+
+/**
+ * Invert state of pixel of specified location
+ * \param x X-coordinate
+ * \param y Y-coordinate
+ */
+void glcd_invert_pixel(uint8_t x, uint8_t y);
+
+/**
+ * Draw line
+ * \param x0 Start x-coordinate
+ * \param y0 Start y-coordinate
+ * \param x1 End x-coordinate
+ * \param y1 End y-coordinate
+ * \param color Colour to set pixels
+ * \see ColourConstants
+ */
+void glcd_draw_line(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1, uint8_t color);
+
+/**
+ * Draw rectangle and fill with colour.
+ * The border of the rectangle is the same as fill colour
+ * \param x Start x-coordinate (left-most)
+ * \param y Start y-coordinate (top-most)
+ * \param w Width
+ * \param h Height
+ * \param color Colour to fill with
+ * \see ColourConstants
+ */
+void glcd_fill_rect(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t color);
+
+/**
+ * Draw rectangle but do not fill.
+ * The border of the rectangle is the same as fill colour
+ * \param x Start x-coordinate (left-most)
+ * \param y Start y-coordinate (top-most)
+ * \param w Width
+ * \param h Height
+ * \param color Colour of border
+ * \see ColourConstants
+ */
+void glcd_draw_rect(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t color);
+
+/**
+ * Draw rectangle but do not fill. User specified thickness.
+ * The border of the rectangle is the same as fill colour
+ * \param x Start x-coordinate (left-most)
+ * \param y Start y-coordinate (top-most)
+ * \param w Width (outermost pixels)
+ * \param h Height
+ * \param tx Thickness of horizontal border along X axis
+ * \param ty Thickness of vertical border along Y axis
+ * \param color Colour of border
+ * \see ColourConstants
+ */
+void glcd_draw_rect_thick(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t tx, uint8_t ty, uint8_t color);
+
+/**
+ * Draw rectangle but do not fill. Place a shadow line on the bottom-right of the window.
+ * The border of the rectangle is the same as fill colour
+ * \param x Start x-coordinate (left-most)
+ * \param y Start y-coordinate (top-most)
+ * \param w Width
+ * \param h Height
+ * \param color Colour of border
+ * \see ColourConstants
+ */
+void glcd_draw_rect_shadow(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t color);
+
+/**
+ * Draw circle but do not fill.
+ * The border of the rectangle is the same as fill colour
+ * \param x0 Centre x-coordinate (left-most)
+ * \param y0 Centre y-coordinate (top-most)
+ * \param r Radius
+ * \param color Colour of border
+ * \see ColourConstants
+ */
+void glcd_draw_circle(uint8_t x0, uint8_t y0, uint8_t r, uint8_t color);
+
+/**
+ * Draw circle and fill.
+ * The border of the rectangle is the same as fill colour
+ * \param x0 Centre x-coordinate (left-most)
+ * \param y0 Centre y-coordinate (top-most)
+ * \param r Radius
+ * \param color Colour of border
+ * \see ColourConstants
+ */
+void glcd_fill_circle(uint8_t x0, uint8_t y0, uint8_t r, uint8_t color);
+
+/**
+ * Invert pixels in a retangular area.
+ * \param x Start x-coordinate (left-most)
+ * \param y Start y-coordinate (top-most)
+ * \param w Width
+ * \param h Height
+ */
+void glcd_invert_area(uint8_t x, uint8_t y, uint8_t w, uint8_t h);
+
+/**
+ * Draw bitmap to screen buffer.
+ * Note this will draw to the entire buffer, its not yet possible to draw partially to the LCD.
+ * Not yet supported with AVR pgmspace.
+ * \param data Pointer to bitmap data.
+ */
+void glcd_draw_bitmap(const unsigned char *data);
+
+/** @}*/
+
+#endif /* GLCD_GRAPHICS_H_ */
diff --git a/lcd/glcd_graphs.h b/lcd/glcd_graphs.h
new file mode 100644
index 0000000..a1aa987
--- /dev/null
+++ b/lcd/glcd_graphs.h
@@ -0,0 +1,88 @@
+/**
+ \file glcd_graphs.h
+ \brief GLCD Library - Graph drawing functions.
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef GLCD_GRAPHS_H
+#define GLCD_GRAPHS_H
+
+/** \addtogroup Graphing
+ * Functions for graphing, e.g drawing bar graphs etc.
+ * @{
+ */
+
+/** Draw horizontal bar graph with 1 px wide border.
+ * The bar graph draws from left to right as val increases.
+ * \param x x location for top-left of border
+ * \param y y location for top-left of border
+ * \param width width of the border
+ * \param height height of the border (must be over 2)
+ * \param val value to display in graph (0-255 8 bit value).
+ */
+void glcd_bar_graph_horizontal(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val);
+
+/** Draw horizontal bar graph with no border.
+ * The bar graph draws from left to right as val increases.
+ * \param x x location for top-left of bar
+ * \param y y location for top-left of bar
+ * \param width width of the bar at full val
+ * \param height height of the bar
+ * \param val value to display in graph (0-255 8 bit value).
+ */
+void glcd_bar_graph_horizontal_no_border(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val);
+
+/** Draw vertical bar graph with 1px wide border.
+ * The bar graph draws from bottom to top as val increases.
+ * \param x x location for top-left of border
+ * \param y y location for top-left of border
+ * \param width width of the border
+ * \param height height of the border
+ * \param val value to display in graph (0-255 8 bit value).
+ */
+void glcd_bar_graph_vertical(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val);
+
+/** Draw vertical bar graph with no border.
+ * The bar graph draws from bottom to top as val increases.
+ * \param x x location for top-left of bar
+ * \param y y location for top-left of bar
+ * \param width width of the bar
+ * \param height height of the bar
+ * \param val value to display in graph (0-255 8 bit value).
+ */
+void glcd_bar_graph_vertical_no_border(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val);
+
+/** \todo write doc */
+void glcd_scrolling_bar_graph(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val);
+
+/** @}*/
+
+#endif
diff --git a/lcd/glcd_spi.c b/lcd/glcd_spi.c
new file mode 100644
index 0000000..1e65708
--- /dev/null
+++ b/lcd/glcd_spi.c
@@ -0,0 +1,115 @@
+/**
+ * \file STM32F10x.c
+ * \brief Device implementation for ST STM32F10x ARM Cortex-M3 MCUs
+ * Requires the use of ST's Standard Peripheral Library
+ * \author Andy Gock
+ * \todo Code is untested!
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Includes from CMSIS and Peripheral Library */
+#include "stm32f10x.h"
+#include "../sys_hw/timer.h"
+#include "glcd_spi.h"
+#include "ST7565R.h"
+
+void glcd_HW_init(void)
+{
+ /* Initialisation of GPIO and SPI */
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Set up GPIO pins */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
+
+ /* DC pin */
+ GPIO_InitStructure.GPIO_Pin = CONTROLLER_SPI_DC_PIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(CONTROLLER_SPI_DC_PORT, &GPIO_InitStructure);
+
+ /* RESET pin */
+ GPIO_InitStructure.GPIO_Pin = CONTROLLER_SPI_RST_PIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(CONTROLLER_SPI_RST_PORT, &GPIO_InitStructure);
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ GLCD_BKL_ON();
+
+ /* Make sure chip is de-selected by default */
+ GLCD_DESELECT();
+
+ /* Initialise SPI */
+ spi_init();
+
+ /* Send reset pulse to LCD */
+ glcd_reset();
+ delay_ms(1);
+
+ glcd_ST7565R_init();
+
+ /* Set all dots black and hold for 0.5s, then clear it, we do this so we can visually check init sequence is working */
+// glcd_all_on();
+// delay_ms(50);
+ glcd_normal();
+
+ glcd_set_start_line(0);
+ glcd_clear_now();
+}
+
+void glcd_spi_write(uint8_t c)
+{
+ GLCD_SELECT();
+ spi_transive(c, 1000);
+ GLCD_DESELECT();
+}
+
+void glcd_reset(void)
+{
+ GLCD_SELECT();
+ GLCD_RESET_LOW();
+ delay_ms(2);
+ GLCD_RESET_HIGH();
+ GLCD_DESELECT();
+}
+/*void GLCD_BKL_ON(void)
+{
+ GPIO_SetBits(GPIOA, GPIO_Pin_15);
+}
+void GLCD_BKL_OFF(void)
+{
+ GPIO_ResetBits(GPIOA, GPIO_Pin_15);
+}*/
diff --git a/lcd/glcd_spi.h b/lcd/glcd_spi.h
new file mode 100644
index 0000000..64a6249
--- /dev/null
+++ b/lcd/glcd_spi.h
@@ -0,0 +1,100 @@
+/**
+ * \file STM32F10x.h
+ * \brief Device implementation for ST STM32F10x ARM Cortex-M3 MCUs
+ * Requires the use of ST's Standard Peripheral Library
+ * \author Andy Gock
+ *
+ * \todo Code is untested!
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef __glcd_spi_h__
+#define __glcd_spi_h__
+
+#include "spi.h"
+
+/** SPI port number e.g SPI1, SPI2 (not to be confused with GPIOA, GPIOB, etc) */
+#define CONTROLLER_SPI_NUMBER
+#define CONTROLLER_SPI_PORT
+#define CONTROLLER_SPI_SCK_PIN
+#define CONTROLLER_SPI_SCK_PINSRC
+#define CONTROLLER_SPI_MISO_PIN
+#define CONTROLLER_SPI_MISO_PINSRC
+#define CONTROLLER_SPI_MOSI_PIN
+#define CONTROLLER_SPI_MOSI_PINSRC
+
+#define CONTROLLER_SPI_SS_PORT
+#define CONTROLLER_SPI_SS_PIN
+#define CONTROLLER_SPI_DC_PORT GPIOC
+#define CONTROLLER_SPI_DC_PIN GPIO_Pin_10
+#define CONTROLLER_SPI_RST_PORT GPIOC
+#define CONTROLLER_SPI_RST_PIN GPIO_Pin_11
+
+#define GLCD_SELECT() SPI_SELECT_CH2()
+#define GLCD_DESELECT() SPI_DESELECT_CH2()
+#define GLCD_DC_LOW() GPIO_ResetBits(CONTROLLER_SPI_DC_PORT,CONTROLLER_SPI_DC_PIN)
+#define GLCD_DC_HIGH() GPIO_SetBits(CONTROLLER_SPI_DC_PORT,CONTROLLER_SPI_DC_PIN)
+#define GLCD_A0_LOW() GPIO_ResetBits(CONTROLLER_SPI_DC_PORT,CONTROLLER_SPI_DC_PIN)
+#define GLCD_A0_HIGH() GPIO_SetBits(CONTROLLER_SPI_DC_PORT,CONTROLLER_SPI_DC_PIN)
+#define GLCD_RESET_LOW() GPIO_ResetBits(CONTROLLER_SPI_RST_PORT,CONTROLLER_SPI_RST_PIN)
+#define GLCD_RESET_HIGH() GPIO_SetBits(CONTROLLER_SPI_RST_PORT,CONTROLLER_SPI_RST_PIN)
+/*#ifdef HW_V01
+#define GLCD_BKL_ON() GPIO_SetBits(GPIOD, GPIO_Pin_2)
+#define GLCD_BKL_OFF() GPIO_ResetBits(GPIOD, GPIO_Pin_2)
+#endif
+#ifdef HW_V02*/
+#define GLCD_BKL_ON() GPIO_SetBits(GPIOA, GPIO_Pin_15)
+#define GLCD_BKL_OFF() GPIO_ResetBits(GPIOA, GPIO_Pin_15)
+//#endif
+
+/**
+ * Initialise the LCD. This function is platform and controller specific.
+ */
+void glcd_HW_init(void);
+
+/**
+ * Write a byte to the connected SPI slave.
+ * \param c Byte to be written
+ * \return Returned value from SPI (often not used)
+ */
+void glcd_spi_write(uint8_t c);
+
+
+/**
+ * Reset the LCD.
+ * \note Not all LCD controllers support reset.
+ */
+void glcd_reset(void);
+
+void glcd_bkl_on(void);
+
+void glcd_bkl_off(void);
+
+#endif
+/* __glcd_spi_h__ */
diff --git a/lcd/glcd_text.h b/lcd/glcd_text.h
new file mode 100644
index 0000000..85b4e61
--- /dev/null
+++ b/lcd/glcd_text.h
@@ -0,0 +1,109 @@
+/**
+ \file glcd_text.h
+ \brief GLCD Library - Text functions
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef GLCD_TEXT_H
+#define GLCD_TEXT_H
+
+/** \addtogroup Text
+ * Functions relating to using text fonts.
+ * @{
+ */
+
+/** \addtogroup StandardText Standard Text
+ * Functions relating to using text fonts of all sizes.
+ * @{
+ */
+
+/** Set GLCD font to predefined font table. Only suitable for MikroElektronika font storage format.
+ *
+ * \param font_table pointer to font table to be used
+ * \param width width of each character
+ * \param height height of each character
+ * \param start_char first character of font table
+ * \param end_char last character of font table
+ * \note Only suitable for MikroElektronika font storage format. For Stang format, use
+ * glcd_tiny_set_font()
+ * \see glcd_tiny_set_font()
+ */
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_set_font(PGM_P font_table, uint8_t width, uint8_t height, char start_char, char end_char);
+#else
+void glcd_set_font(const char * font_table, uint8_t width, uint8_t height, char start_char, char end_char);
+#endif
+
+/** Set GLCD font to predefined font table. Suitable for different different types of font tables.
+ *
+ * \param font_table pointer to font table to be used
+ * \param width width of each character
+ * \param height height of each character
+ * \param start_char first character of font table
+ * \param end_char last character of font table
+ * \param type font table type
+ * \note Only suitable for MikroElektronika font storage format. For Stang format, use
+ * glcd_tiny_set_font()
+ * \see glcd_tiny_set_font()
+ */
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_font(PGM_P font_table, uint8_t width, uint8_t height, char start_char, char end_char, font_table_type_t type);
+#else
+void glcd_font(const char * font_table, uint8_t width, uint8_t height, char start_char, char end_char, font_table_type_t type);
+#endif
+
+/** Draw a char at specified location.
+ * \param x x location to place top-left of character frame
+ * \param y y location to place top-left of character frame
+ * \param c character to be drawn
+ * \return width of character, 0 on error (e.g could not read font table)
+ */
+uint8_t glcd_draw_char_xy(uint8_t x, uint8_t y, char c);
+
+/** Draw a string at specified location.
+ * \param x x location to place top-left of character frame
+ * \param y y location to place top-left of character frame
+ * \param c pointer to string to be drawn
+ */
+void glcd_draw_string_xy(uint8_t x, uint8_t y, char *c);
+
+/** Draw a string from program memory at specified location.
+ * \param x x location to place top-left of character frame
+ * \param y y location to place top-left of character frame
+ * \param str pointer to string in program memory to be drawn
+ */
+void glcd_draw_string_xy_P(uint8_t x, uint8_t y, const char *str);
+
+/** @}*/
+
+/** @}*/
+
+#endif
diff --git a/lcd/glcd_text_tiny.h b/lcd/glcd_text_tiny.h
new file mode 100644
index 0000000..e8dc4d7
--- /dev/null
+++ b/lcd/glcd_text_tiny.h
@@ -0,0 +1,138 @@
+/**
+ \file glcd_text_tiny.h
+ \brief GLCD Library - Tiny Text functions.
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef GLCD_TEXT_TINY_H
+#define GLCD_TEXT_TINY_H
+
+#include "stdint.h"
+
+/** \addtogroup TinyText Tiny Text
+ * Functions relating to using tiny 5x7 text fonts.
+ *
+ * Tiny text functions are usually used on a line by line basis. Each line being 8 bits high.
+ * Characters start on the top most bit and are 7 bits high, leaving a one bit space underneath.
+ *
+ * @{
+ */
+
+/** Set font to be used from now on. This is the tiny 5x7 monospace font.
+ * \param font_table flash pointer to start from font table
+ * \param width width of each character
+ * \param height height of each character
+ * \param start_char start character
+ * \param end_char end character
+ * \note Only suitable for Stang font storage format. For MikroElektronika format, use
+ * glcd_set_font()
+ * \see glcd_set_font()
+ */
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_tiny_set_font(PGM_P font_table, uint8_t width, uint8_t height, char start_char, char end_char);
+#else
+void glcd_tiny_set_font(const char *font_table, uint8_t width, uint8_t height, char start_char, char end_char);
+#endif
+
+/** Write character to LCD in tiny 5x7 font.
+ * \param x column position to start
+ * \param line line number to be written (each line is 8 pixels high)
+ * \param c char to be written
+ */
+void glcd_tiny_draw_char(uint8_t x, uint8_t line, char c);
+
+/** Write string to display buffer in tiny 5x7 font.
+ * Will wrap to next line if needed. Screen is not updated. Use glcd_write() to physically update display.
+ * \param x column position to start
+ * \param line line number to be written (each line is 8 pixels high)
+ * \param str string to be written
+ */
+void glcd_tiny_draw_string(uint8_t x, uint8_t line, char *str);
+
+/** Write flash string to display buffer in tiny 5x7 font.
+ * Will wrap to next line if needed. Screen is not updated. Use glcd_write() to physically update display.
+ * \param x column position to start
+ * \param line line to be written (each line is 8 pixels high)
+ * \param str string stored in flash memory to be written
+ */
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_tiny_draw_string_P(uint8_t x, uint8_t line, PGM_P str);
+#else
+void glcd_tiny_draw_string_P(uint8_t x, uint8_t line, const char *str);
+#endif
+
+/** Write string to bottom row of display.
+ * Screen buffer is scrolled up by one line. Screen is then physically updated.
+ * \param str string to be written
+ */
+void glcd_tiny_draw_string_ammend(char *str);
+
+/** Write string from flash memory to bottom row of display.
+ * Screen buffer is scrolled up by one line. Screen is then physically updated.
+ * \param str string to be written
+ */
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_tiny_draw_string_ammend_P(PGM_P str);
+#else
+void glcd_tiny_draw_string_ammend_P(const char *str);
+#endif
+
+/**
+ * Invert all contents of line number. Line 0 is the top most line.
+ * \param line Line number (0 is top most line)
+ */
+void glcd_tiny_invert_line(uint8_t line);
+
+/** Write character to LCD in tiny 5x7 font to specified X, Y location.
+ * If position is aligned with 8 bit line heights, use glcd_tiny_draw_char() instead
+ * as it will be faster.
+ *
+ * \param x column position to start
+ * \param y row position to start (pixel based, not 8 bit high rows)
+ * \param c char to be written
+ * \see glcd_tiny_draw_char()
+ * \note This does the same thing as glcd_tiny_draw_char_xy() but is limited to Stang format
+ * font tables.
+ */
+void glcd_tiny_draw_char_xy(uint8_t x, uint8_t y, char c);
+
+/** Initialise 5x7 text */
+#define GLCD_TEXT_INIT() glcd_tiny_set_font(Font5x7,5,7,32,127);
+
+/** Write string to bottom-most line after scrolling everything else up */
+#define GLCD_WRITE(str) glcd_tiny_draw_string_ammend(str)
+
+/** Write string from program memory to bottom-most line after scrolling everything else up */
+#define GLCD_WRITE_P(str) glcd_tiny_draw_string_ammend_P(str)
+
+/** @}*/
+
+#endif
diff --git a/lcd/graphics.c b/lcd/graphics.c
new file mode 100644
index 0000000..dec75c0
--- /dev/null
+++ b/lcd/graphics.c
@@ -0,0 +1,309 @@
+/**
+ \file graphics.c
+ \brief Functions relating to graphics. e.g drawing lines, rectangles, circles etc.
+ \author Andy Gock
+
+ Some functions based on Limor Fried's PCD8544 Arduino library.
+
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ Copyright (c) 2012, Adafruit Industries
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "glcd.h"
+
+/* Based on PCD8544 library by Limor Fried */
+void glcd_set_pixel(uint8_t x, uint8_t y, uint8_t color) {
+ if (x > (GLCD_LCD_WIDTH-1) || y > (GLCD_LCD_HEIGHT-1)) {
+ /* don't do anything if x/y is outside bounds of display size */
+ return;
+ }
+
+ if (color) {
+ /* Set black */
+ glcd_buffer[x+ (y/8)*GLCD_LCD_WIDTH] |= ( 1 << (y%8));
+ } else {
+ /* Set white */
+ glcd_buffer[x+ (y/8)*GLCD_LCD_WIDTH] &= ~ (1 << (y%8));
+ }
+
+ glcd_update_bbox(x,y,x,y);
+}
+
+/* Based on PCD8544 library by Limor Fried */
+uint8_t glcd_get_pixel(uint8_t x, uint8_t y) {
+ if ((x >= GLCD_LCD_WIDTH) || (y >= GLCD_LCD_HEIGHT)) {
+ return 0;
+ }
+
+ if ( glcd_buffer[x+ (y/8)*GLCD_LCD_WIDTH] & ( 1 << (y%8)) ) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+void glcd_invert_pixel(uint8_t x, uint8_t y) {
+ if ((x >= GLCD_LCD_WIDTH) || (y >= GLCD_LCD_HEIGHT)) {
+ return;
+ }
+ glcd_update_bbox(x,y,x,y);
+ glcd_buffer[x+ (y/8)*GLCD_LCD_WIDTH] ^= ( 1 << (y%8));
+}
+
+/* Bresenham's algorithm - based on PCD8544 library Limor Fried */
+void glcd_draw_line(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1, uint8_t color) {
+ uint8_t steep = abs(y1 - y0) > abs(x1 - x0);
+ uint8_t dx, dy;
+ int8_t err;
+ int8_t ystep;
+
+ if (steep) {
+ swap(x0, y0);
+ swap(x1, y1);
+ }
+
+ if (x0 > x1) {
+ swap(x0, x1);
+ swap(y0, y1);
+ }
+
+ glcd_update_bbox( x0, y0, x1, y1 );
+
+ dx = x1 - x0;
+ dy = abs(y1 - y0);
+
+ err = dx / 2;
+
+ if (y0 < y1) {
+ ystep = 1;
+ } else {
+ ystep = -1;
+ }
+
+ for (; x0<=x1; x0++) {
+ if (steep) {
+ glcd_set_pixel(y0, x0, color);
+ } else {
+ glcd_set_pixel(x0, y0, color);
+ }
+ err -= dy;
+ if (err < 0) {
+ y0 += ystep;
+ err += dx;
+ }
+ }
+}
+
+void glcd_fill_rect(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t color)
+{
+ int16_t i;
+ for (i=x; i<x+w; i++) {
+ int16_t j;
+ for (j=y; j<y+h; j++) {
+ glcd_set_pixel(i, j, color);
+ }
+ }
+ glcd_update_bbox(x, y, x+w-1, y+h-1);
+}
+
+void glcd_draw_rect(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t color)
+{
+ int16_t i;
+ for (i=x; i<x+w; i++) {
+ glcd_set_pixel(i, y, color);
+ glcd_set_pixel(i, y+h-1, color);
+ }
+ for (i=y; i<y+h; i++) {
+ glcd_set_pixel(x, i, color);
+ glcd_set_pixel(x+w-1, i, color);
+ }
+ glcd_update_bbox(x, y, x+w-1, y+h-1);
+}
+
+void glcd_draw_rect_thick(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t tx, uint8_t ty, uint8_t color)
+{
+ int16_t i, t;
+
+ if (tx == 0) {
+ tx = 1;
+ }
+
+ if (ty == 0) {
+ ty = 1;
+ }
+
+ for (i=x; i<x+w; i++) {
+ /* Top and bottom sides */
+ for (t=0; t<(ty); t++) {
+ glcd_set_pixel(i, y+t, color);
+ glcd_set_pixel(i, y+h-1-t, color);
+ }
+ }
+ for (i=y; i<y+h; i++) {
+ /* Left and right sides */
+ for (t=0; t<(tx); t++) {
+ glcd_set_pixel(x+t, i, color);
+ glcd_set_pixel(x+w-1-t, i, color);
+ }
+ }
+ glcd_update_bbox(x, y, x+w-1, y+h-1);
+}
+
+void glcd_draw_rect_shadow(uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t color)
+{
+ glcd_draw_rect(x, y, w, h, color);
+ glcd_draw_line(x+1, y+h, x+w, y+h, color);
+ glcd_draw_line(x+w, y+1, x+w, y+h, color);
+}
+
+void glcd_draw_circle(uint8_t x0, uint8_t y0, uint8_t r, uint8_t color)
+{
+
+ int8_t f = 1 - r;
+ int8_t ddF_x = 1;
+ int8_t ddF_y = -2 * r;
+ int8_t x = 0;
+ int8_t y = r;
+
+ glcd_update_bbox(x0-r, y0-r, x0+r, y0+r);
+
+ glcd_set_pixel(x0, y0+r, color);
+ glcd_set_pixel(x0, y0-r, color);
+ glcd_set_pixel(x0+r, y0, color);
+ glcd_set_pixel(x0-r, y0, color);
+
+ while (x<y) {
+ if (f >= 0) {
+ y--;
+ ddF_y += 2;
+ f += ddF_y;
+ }
+ x++;
+ ddF_x += 2;
+ f += ddF_x;
+
+ glcd_set_pixel(x0 + x, y0 + y, color);
+ glcd_set_pixel(x0 - x, y0 + y, color);
+ glcd_set_pixel(x0 + x, y0 - y, color);
+ glcd_set_pixel(x0 - x, y0 - y, color);
+
+ glcd_set_pixel(x0 + y, y0 + x, color);
+ glcd_set_pixel(x0 - y, y0 + x, color);
+ glcd_set_pixel(x0 + y, y0 - x, color);
+ glcd_set_pixel(x0 - y, y0 - x, color);
+
+ }
+}
+
+void glcd_fill_circle(uint8_t x0, uint8_t y0, uint8_t r, uint8_t color)
+{
+
+ int8_t f = 1 - r;
+ int8_t ddF_x = 1;
+ int8_t ddF_y = -2 * r;
+ int8_t x = 0;
+ int8_t y = r;
+
+ int16_t i;
+
+ glcd_update_bbox(x0-r, y0-r, x0+r, y0+r);
+
+ for (i=y0-r; i<=y0+r; i++) {
+ glcd_set_pixel(x0, i, color);
+ }
+
+ while (x < y) {
+ if (f >= 0) {
+ y--;
+ ddF_y += 2;
+ f += ddF_y;
+ }
+ x++;
+ ddF_x += 2;
+ f += ddF_x;
+
+ for (i=y0-y; i<=y0+y; i++) {
+ glcd_set_pixel(x0+x, i, color);
+ glcd_set_pixel(x0-x, i, color);
+ }
+ for (i=y0-x; i<=y0+x; i++) {
+ glcd_set_pixel(x0+y, i, color);
+ glcd_set_pixel(x0-y, i, color);
+ }
+ }
+}
+
+void glcd_invert_area(uint8_t x, uint8_t y, uint8_t w, uint8_t h)
+{
+ uint8_t xx, yy;
+ for (xx = x; xx < (x+w); xx++) {
+ /* Loop through each partial column */
+ for (yy = y; yy < (y+h); yy++) {
+ /* Go down and invert every pixel */
+ glcd_invert_pixel(xx,yy);
+ }
+ }
+}
+
+void glcd_draw_bitmap(const unsigned char *data)
+{
+
+#if 0
+ /* Testing purposes only: Writing to the LCD right away (not for AVR) */
+ /* Normally, we do not do this, we just write to the screen buffer */
+ uint8_t *original_buffer;
+
+ /* Save the location of original screen buffer */
+ original_buffer = glcd_buffer_selected;
+
+ /* Use bitmap location as screen buffer (this won't work when using AVR8 PGM_P) */
+ glcd_select_screen((uint8_t *)data, glcd_bbox_selected);
+
+ /* Make sure we write the entre display */
+ glcd_bbox_refresh();
+ glcd_write();
+
+ /* Restore the screen buffer back to original */
+ glcd_select_screen(original_buffer, glcd_bbox_selected);
+#endif
+
+ /* Copy bitmap data to the screen buffer */
+#if defined(GLCD_DEVICE_AVR8)
+ memcpy_P(glcd_buffer_selected, data, (GLCD_LCD_WIDTH * GLCD_LCD_HEIGHT / 8));
+#else
+ memcpy(glcd_buffer_selected, data, (GLCD_LCD_WIDTH * GLCD_LCD_HEIGHT / 8));
+#endif
+
+ glcd_bbox_refresh();
+}
diff --git a/lcd/graphs.c b/lcd/graphs.c
new file mode 100644
index 0000000..fb1f034
--- /dev/null
+++ b/lcd/graphs.c
@@ -0,0 +1,120 @@
+/**
+ \file graphs.c
+ \brief Functions relating to graphs. e.g bar graphs etc.
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "glcd.h"
+
+static uint8_t glcd_map(uint8_t x1, uint8_t x2, uint8_t x);
+
+void glcd_bar_graph_horizontal(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val)
+{
+ if (height < 3) {
+ return;
+ }
+ glcd_draw_rect(x, y, width, height, BLACK);
+ glcd_fill_rect(x+1, y+1, glcd_map(0,width-2,val), height-2 , BLACK);
+}
+
+void glcd_bar_graph_horizontal_no_border(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val)
+{
+ if (height < 3) {
+ return;
+ }
+ glcd_fill_rect(x, y, glcd_map(0,width,val), height , BLACK);
+}
+
+void glcd_bar_graph_vertical(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val)
+{
+ glcd_draw_rect(x, y, width, height, BLACK);
+ glcd_fill_rect(x+1, y+1+glcd_map(0,height-2,255-val), width-2, height-2-glcd_map(0,height-2,255-val), BLACK);
+}
+
+void glcd_bar_graph_vertical_no_border(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val)
+{
+ glcd_fill_rect(x, y+glcd_map(0,height-2,255-val), width, height-2-glcd_map(0,height-2,255-val), BLACK);
+}
+
+void glcd_scrolling_bar_graph(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val)
+{
+ uint8_t nx, ny;
+ uint8_t color;
+
+ /* Draw border of graph */
+ glcd_draw_rect(x,y,width,height,BLACK);
+
+ /* Scroll inner contents left by one pixel width */
+ for (ny = 1; ny <= (height-2); ny++) {
+ /* Redraw each horizontal line */
+ for (nx = 1; nx <= (width-2); nx += 1) {
+ color = glcd_get_pixel(x+nx+1,y+ny);
+ glcd_set_pixel(x+nx,y+ny,color);
+ }
+ }
+
+ val = val * (height-3) / 255;
+
+ /* Make sure we're not exceeding the size of box interior */
+ if (val > (height-3)) {
+ val = height - 3;
+ }
+
+ /* Draw new bar - both black and white portions*/
+ glcd_draw_line(x+width-2,y+height-2,x+width-2,y+height-2-val,BLACK);
+ glcd_draw_line(x+width-2,y+height-3-val,x+width-2,y+1,WHITE);
+
+ /* Write to display */
+ glcd_write();
+}
+
+void glcd_scrolling_bar_graph_timing(uint8_t x, uint8_t y, uint8_t width, uint8_t height, uint8_t val, uint8_t line_width, uint16_t delay)
+{
+ uint8_t n;
+ if (line_width == 0) {
+ line_width = 1;
+ }
+
+ /* Adjust graph line's width by just running glcd_scrolling_bar_graph() x number of times */
+ /* \todo This should be done differently! */
+ for (n=0; n<line_width; n++) {
+ glcd_scrolling_bar_graph(x,y,width,height,val);
+ }
+
+ if (delay) {
+ delay_ms(delay);
+ }
+}
+
+static uint8_t glcd_map(uint8_t x1, uint8_t x2, uint8_t x)
+{
+ return x1+(x2-x1)*x/255;
+}
diff --git a/lcd/spi.c b/lcd/spi.c
new file mode 100644
index 0000000..23bb27a
--- /dev/null
+++ b/lcd/spi.c
@@ -0,0 +1,79 @@
+#include "spi.h"
+
+static void spi_gpio_init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB|RCC_APB2Periph_AFIO, ENABLE);
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15|GPIO_Pin_13;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+}
+
+static void spi_cs_init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC|RCC_APB2Periph_GPIOA, ENABLE);
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ GPIO_SetBits(GPIOB, GPIO_Pin_12);
+ GPIO_SetBits(GPIOC, GPIO_Pin_7);
+ GPIO_SetBits(GPIOA, GPIO_Pin_8);
+}
+
+void spi_init(void)
+{
+ SPI_InitTypeDef SPI_InitStructure;
+
+ spi_cs_init();
+ spi_gpio_init();
+
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
+ SPI_Init(SPI2, &SPI_InitStructure);
+
+ SPI_Cmd(SPI2, ENABLE);
+}
+
+//transmit/receive
+uint8_t spi_transive(uint8_t byte, uint32_t timeout)
+{
+ uint32_t timer;
+
+ timer = timeout;
+ while((SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET)&&timer)
+ {
+ timer --;
+ }
+ SPI_I2S_SendData(SPI2, byte);
+
+ timer = timeout;
+ while((SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)&&timer)
+ {
+ timer --;
+ }
+ return SPI_I2S_ReceiveData(SPI2);
+}
diff --git a/lcd/spi.h b/lcd/spi.h
new file mode 100644
index 0000000..89a3c5b
--- /dev/null
+++ b/lcd/spi.h
@@ -0,0 +1,19 @@
+#ifndef __spi_h__
+#define __spi_h__
+
+#include "stm32f10x.h"
+
+#define SPI_SELECT_CH1() GPIO_ResetBits(GPIOB, GPIO_Pin_12)
+#define SPI_DESELECT_CH1() GPIO_SetBits(GPIOB, GPIO_Pin_12)
+
+#define SPI_SELECT_CH2() GPIO_ResetBits(GPIOA, GPIO_Pin_8)
+#define SPI_DESELECT_CH2() GPIO_SetBits(GPIOA, GPIO_Pin_8)
+
+
+#define SPI_SELECT_CH3() GPIO_ResetBits(GPIOC, GPIO_Pin_7)
+#define SPI_DESELECT_CH3() GPIO_SetBits(GPIOC, GPIO_Pin_7)
+
+extern void spi_init(void);
+extern uint8_t spi_transive(uint8_t byte, uint32_t timeout);
+
+#endif
diff --git a/lcd/text.c b/lcd/text.c
new file mode 100644
index 0000000..23bfa5d
--- /dev/null
+++ b/lcd/text.c
@@ -0,0 +1,321 @@
+
+/**
+ \file text.c
+ \brief Functions relating to using text fonts of all sizes.
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "glcd.h"
+
+extern uint8_t *glcd_buffer_selected;
+extern glcd_BoundingBox_t *glcd_bbox_selected;
+
+glcd_FontConfig_t font_current;
+
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_set_font(PGM_P font_table, uint8_t width, uint8_t height, char start_char, char end_char)
+#else
+void glcd_set_font(const char * font_table, uint8_t width, uint8_t height, char start_char, char end_char)
+#endif
+{
+ /* Supports variable width fonts */
+ font_current.font_table = font_table;
+ font_current.width = width;
+ font_current.height = height;
+ font_current.start_char = start_char;
+ font_current.end_char = end_char;
+ font_current.table_type = MIKRO; /* Only supports MikroElektronika generated format at the moment */
+}
+
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_font(PGM_P font_table, uint8_t width, uint8_t height, char start_char, char end_char, font_table_type_t type)
+#else
+void glcd_font(const char * font_table, uint8_t width, uint8_t height, char start_char, char end_char, font_table_type_t type)
+#endif
+{
+ /* Supports variable width fonts */
+ font_current.font_table = font_table;
+ font_current.width = width;
+ font_current.height = height;
+ font_current.start_char = start_char;
+ font_current.end_char = end_char;
+ font_current.table_type = type; /* Only supports MikroElektronika generated format at the moment */
+}
+
+uint8_t glcd_draw_char_xy(uint8_t x, uint8_t y, char c)
+{
+ if (c < font_current.start_char || c > font_current.end_char) {
+ c = '.';
+ }
+
+ if (font_current.table_type == STANG) {
+ /* Font table in Pascal Stang format (single byte height with with no width specifier) */
+ /* Maximum height of 8 bits only */
+
+ uint8_t i;
+ for ( i = 0; i < font_current.width; i++ ) {
+#if defined(GLCD_DEVICE_AVR8)
+ uint8_t dat = pgm_read_byte( font_current.font_table + ((c - font_current.start_char) * (font_current.width)) + i );
+#else
+ uint8_t dat = *( font_current.font_table + ((c - font_current.start_char) * (font_current.width)) + i );
+#endif
+ uint8_t j;
+
+ if(glcd_get_reverse_sta())
+ dat = ~dat;
+ for (j = 0; j < 8; j++) {
+ /* Set pixel color for each bit of the column (8-bits) */
+ if (x+i >= GLCD_LCD_WIDTH || y+j >= GLCD_LCD_HEIGHT) {
+ /* Don't try and write past the dimensions of the LCD */
+ return 0;
+ }
+ if (dat & (1<<j)) {
+ glcd_set_pixel(x+i,y+j,BLACK);
+ } else {
+ glcd_set_pixel(x+i,y+j,WHITE);
+ }
+ }
+ }
+
+ /* always return how many pixels of width were written */
+ /* here for "stang" format fonts, it is always fixed */
+ return font_current.width;
+
+ } else if (font_current.table_type == MIKRO) {
+ /* Font table in MikroElecktronica format
+ - multi row fonts allowed (more than 8 pixels high)
+ - variable width fonts allowed
+ a complete column is written before moving to the next */
+
+ uint8_t i;
+ uint8_t var_width;
+ uint8_t bytes_high;
+ uint8_t bytes_per_char;
+ const char *p;
+
+ if ((font_current.height % 8) > 0){
+ bytes_high = (font_current.height / 8) + 1;
+ }
+ else{
+ bytes_high = (font_current.height / 8);
+ }
+ bytes_per_char = font_current.width * bytes_high + 1; /* The +1 is the width byte at the start */
+
+ p = font_current.font_table + (c - font_current.start_char) * bytes_per_char;
+
+ /* The first byte per character is always the width of the character */
+#if defined(GLCD_DEVICE_AVR8)
+ var_width = pgm_read_byte(p);
+#else
+ var_width = *p;
+#endif
+ p++; /* Step over the variable width field */
+
+ /*
+ if (x+var_width >= GLCD_LCD_WIDTH || y+font_current.height >= GLCD_LCD_HEIGHT) {
+ return;
+ }
+ */
+
+ for ( i = 0; i < var_width; i++ ) {
+ uint8_t j;
+ for ( j = 0; j < bytes_high; j++ ) {
+#if defined(GLCD_DEVICE_AVR8)
+ uint8_t dat = pgm_read_byte( p + i*bytes_high + j );
+#else
+ uint8_t dat = *( p + i*bytes_high + j );
+#endif
+ uint8_t bit;
+
+ if(glcd_get_reverse_sta())
+ dat = ~dat;
+ for (bit = 0; bit < 8; bit++) {
+
+ if (x+i >= GLCD_LCD_WIDTH || y+j*8+bit >= GLCD_LCD_HEIGHT) {
+ /* Don't write past the dimensions of the LCD, skip the entire char */
+ return 0;
+ }
+
+ /* We should not write if the y bit exceeds font height */
+ if ((j*8 + bit) >= font_current.height) {
+ /* Skip the bit */
+ continue;
+ }
+
+ if (dat & (1<<bit)) {
+ glcd_set_pixel(x+i,y+j*8+bit,BLACK);
+ } else {
+ glcd_set_pixel(x+i,y+j*8+bit,WHITE);
+ }
+ }
+ }
+ }
+ return var_width;
+
+ } else if (font_current.table_type == GLCD_UTILS) {
+ /* Font table format of glcd-utils
+ - A complete row is written first (not completed columns)
+ - Width not stored, but we can search and determine it
+ - Not yet supported */
+
+ uint8_t var_width, n;
+ uint8_t bytes_high, bytes_per_char;
+ const char *p;
+ uint8_t j;
+
+ bytes_high = font_current.height / 8 + 1;
+ bytes_per_char = font_current.width * bytes_high;
+
+ /* Point to chars first byte */
+ p = font_current.font_table + (c - font_current.start_char) * bytes_per_char;
+
+ /* Determine the width of the character */
+ var_width = font_current.width;
+
+ n = 0; /* How many columns back from the end */
+
+ while (1) {
+ uint8_t max_byte = 0;
+ uint8_t row = 0;
+
+ for (row = 0; row < bytes_high; row++) {
+ uint8_t offset;
+ offset = (font_current.width - 1 - n) * row;
+ max_byte = *(p + offset);
+ }
+ if (max_byte == 0) {
+ /* column is empty for all rows, go left and test again */
+ /* reduce variable width by 1 */
+ var_width--;
+ if (var_width == 0) {
+ break;
+ }
+ } else {
+ break; /* Part of a character was found */
+ }
+ n++;
+ }
+
+ /* Uncomment line below, to force fixed width, for debugging only */
+ //var_width = font_current.width; // bypass auto width detection, treat as fixed width
+
+ /* For glcd-utils format, we write one complete row at a time */
+ /* loop as rows, 1st row, j=0 */
+ for ( j = 0; j < bytes_high; j++ ) {
+ /* Loop one row at a time */
+
+ uint8_t i;
+ for ( i = 0; i < var_width; i++ ) {
+ /* Loop one column at a time */
+
+ uint8_t dat, bit;
+
+#if defined(GLCD_DEVICE_AVR8)
+ dat = pgm_read_byte( p + j*font_current.width + i );
+#else
+ dat = *( p + j*font_current.width + i );
+#endif
+
+ if(glcd_get_reverse_sta())
+ dat = ~dat;
+
+ for (bit = 0; bit < 8; bit++) {
+
+ if ((x+i) >= GLCD_LCD_WIDTH || (y+j*8+bit) >= GLCD_LCD_HEIGHT) {
+ /* Don't write past the dimensions of the LCD, skip the entire char */
+ return 0;
+ }
+
+ /* We should not write if the y bit exceeds font height */
+ if ((j*8 + bit) >= font_current.height) {
+ /* Skip the bit */
+ continue;
+ }
+
+ if (dat & (1<<bit)) {
+ glcd_set_pixel(x+i,y+j*8+bit,BLACK);
+ } else {
+ glcd_set_pixel(x+i,y+j*8+bit,WHITE);
+ }
+ }
+ } /* i */
+ } /* j */
+
+ return var_width; /* Number of columns written to display */
+
+ } else {
+ /* Don't recognise the font table */
+ return 0;
+
+ }
+
+}
+
+void glcd_draw_string_xy(uint8_t x, uint8_t y, char *c)
+{
+ uint8_t width;
+
+ if (y > (GLCD_LCD_HEIGHT - font_current.height - 1)) {
+ /* Character won't fit */
+ return;
+ }
+
+ while (*c) {
+ width = glcd_draw_char_xy(x,y,*c);
+ x += (width + 1);
+ c++;
+ }
+}
+
+void glcd_draw_string_xy_P(uint8_t x, uint8_t y, const char *str)
+{
+ uint8_t width;
+
+ if (y > (GLCD_LCD_HEIGHT - font_current.height - 1)) {
+ /* Character won't fit */
+ return;
+ }
+
+ while (1) {
+#if defined(GLCD_DEVICE_AVR8)
+ char c = pgm_read_byte(str++);
+#else
+ char c = *(str++);
+#endif
+ if (!c)
+ return;
+
+ width = glcd_draw_char_xy(x,y,c);
+ x += (width + 1);
+ c++;
+ }
+}
+
diff --git a/lcd/text_tiny.c b/lcd/text_tiny.c
new file mode 100644
index 0000000..ade6d4e
--- /dev/null
+++ b/lcd/text_tiny.c
@@ -0,0 +1,177 @@
+/**
+ \file text_tiny.c
+ \brief Functions relating to using tiny 5x7 text fonts.
+ \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "glcd.h"
+
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_tiny_set_font(PGM_P font_table, uint8_t width, uint8_t height, char start_char, char end_char)
+#else
+void glcd_tiny_set_font(const char * font_table, uint8_t width, uint8_t height, char start_char, char end_char)
+#endif
+{
+ font_current.font_table = font_table;
+ font_current.width = width;
+ font_current.height = height;
+ font_current.start_char = start_char;
+ font_current.end_char = end_char;
+ font_current.table_type = STANG;
+}
+
+void glcd_tiny_draw_char(uint8_t x, uint8_t line, char c)
+{
+ uint8_t i;
+
+ /* Only works for fonts < 8 bits in height */
+ if (font_current.height >= 8) {
+ return;
+ }
+ if (c < font_current.start_char || c > font_current.end_char) {
+ c = '.';
+ }
+ if ( line >= GLCD_LCD_HEIGHT / (font_current.height + 1) ) {
+ return;
+ }
+ if ( (x+font_current.width) >= GLCD_LCD_WIDTH ) {
+ return;
+ }
+
+ glcd_update_bbox(x, line*(font_current.height + 1), x+font_current.width, line*(font_current.height + 1) + (font_current.height + 1));
+
+ for ( i = 0; i < font_current.width; i++ ) {
+#if defined(GLCD_DEVICE_AVR8)
+ glcd_buffer_selected[x + (line * GLCD_LCD_WIDTH)] = pgm_read_byte( font_current.font_table + ((c - font_current.start_char) * (font_current.width)) + i );
+#else
+ glcd_buffer_selected[x + (line * GLCD_LCD_WIDTH)] = *( font_current.font_table + ((c - font_current.start_char) * (font_current.width)) + i );
+#endif
+ x++;
+ }
+}
+
+void glcd_tiny_draw_string(uint8_t x, uint8_t line, char *str)
+{
+ if (font_current.height >= 8) {
+ return;
+ }
+ while (*str) {
+ glcd_tiny_draw_char(x, line, *str++);
+ x += (font_current.width + 1);
+ if ((x + font_current.width + 1) > GLCD_LCD_WIDTH) {
+ x = 0; /* Ran out of this line */
+ line++;
+ }
+ if (line >= (GLCD_LCD_HEIGHT/(font_current.height + 1)))
+ return; /* Ran out of space :( */
+ }
+}
+
+#if defined(GLCD_DEVICE_AVR8)
+void glcd_tiny_draw_string_P(uint8_t x, uint8_t line, PGM_P str)
+#else
+void glcd_tiny_draw_string_P(uint8_t x, uint8_t line, const char *str)
+#endif
+{
+ if (font_current.height >= 8) {
+ return;
+ }
+ while (1) {
+#if defined(GLCD_DEVICE_AVR8)
+ char c = pgm_read_byte(str++);
+#else
+ char c = *(str++);
+#endif
+ if (!c)
+ return;
+
+ glcd_tiny_draw_char(x, line, c);
+
+ x += (font_current.width + 1);
+ if ((x + font_current.width + 1) > GLCD_LCD_WIDTH) {
+ x = 0; /* Ran out of this line */
+ line++;
+ }
+ if (line >= (GLCD_LCD_HEIGHT/(font_current.height + 1)))
+ return; /* Ran out of space :( */
+ }
+}
+
+void glcd_tiny_draw_string_ammend(char *str) {
+ glcd_scroll_line();
+ glcd_tiny_draw_string(0, (GLCD_LCD_HEIGHT/8-1), str);
+ glcd_write();
+}
+
+void glcd_tiny_draw_string_ammend_P(const char *str) {
+ glcd_scroll_line();
+ glcd_tiny_draw_string_P(0, (GLCD_LCD_HEIGHT/8-1), str);
+ glcd_write();
+}
+
+void glcd_tiny_invert_line(uint8_t line)
+{
+ glcd_invert_area(0,line*8,GLCD_LCD_WIDTH-1,8);
+}
+
+void glcd_tiny_draw_char_xy(uint8_t x, uint8_t y, char c)
+{
+ uint8_t i;
+ uint8_t xvar, yvar;
+ uint8_t dat;
+
+ /* Only works for fonts < 8 bits in height */
+
+ /* Check all important bounds requirements are okay */
+ if ( (y >= GLCD_LCD_HEIGHT) || ((x+font_current.width) >= GLCD_LCD_WIDTH) || (font_current.height >= 8) || font_current.table_type != STANG) {
+ return;
+ }
+ if (c < font_current.start_char || c > font_current.end_char) {
+ c = '.';
+ }
+
+ xvar = x;
+
+ for ( i = 0; i < font_current.width; i++ ) {
+#if defined(GLCD_DEVICE_AVR8)
+ dat = pgm_read_byte( font_current.font_table + ((c - font_current.start_char) * (font_current.width)) + i );
+#else
+ dat = *( font_current.font_table + ((c - font_current.start_char) * (font_current.width)) + i );
+#endif
+ for (yvar = 0; yvar < font_current.height; yvar++) {
+ glcd_set_pixel(xvar,y+yvar, (dat & (1<<yvar) ? 1 : 0) );
+ }
+ xvar++;
+ }
+
+ glcd_update_bbox(x, y, x+font_current.width,y+font_current.height);
+
+}
diff --git a/lcd/unit_tests.c b/lcd/unit_tests.c
new file mode 100644
index 0000000..75f8bf1
--- /dev/null
+++ b/lcd/unit_tests.c
@@ -0,0 +1,334 @@
+/**
+ * \file unit_tests.c
+ * \brief Various test functions to demonstrate features of the library
+ * \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "glcd.h"
+#include "unit_tests.h"
+
+/** Fonts */
+#include "font5x7.h"
+#include "Liberation_Sans11x14_Numbers.h"
+#include "Liberation_Sans15x21_Numbers.h"
+#include "Liberation_Sans17x17_Alpha.h"
+#include "Liberation_Sans27x36_Numbers.h"
+#include "Bebas_Neue20x36_Bold_Numbers.h"
+
+volatile uint8_t unit_test_return = 0;
+
+/**
+ * Return from test procedure. Global var \p unit_test_return is set to 1 elsewhere,
+ * to signal function to return.
+ */
+#define DEMO_RETURN() if (unit_test_return) { unit_test_return = 0; return; }
+
+#if defined(GLCD_UNIT_TEST_BITMAP_ENABLE)
+ /* Open Source logo -- Size: 128x64 */
+ #if defined(GLCD_DEVICE_AVR8)
+ const unsigned char bmp_oslogo[] PROGMEM = {
+ #else
+ const unsigned char bmp_oslogo[] = {
+ #endif /* GLCD_DEVICE_AVR8 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xc0, 0xc0, 0xc0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xc0, 0xc0, 0xc0, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfc, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xf0, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xfe, 0xfc, 0xf0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x07, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xf0, 0xe0, 0xc0, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xc0, 0xf0, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x07, 0x1f, 0x7f,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0f, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x3f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0f, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00
+, 0x00 //
+ };
+#endif /* GLCD_UNIT_TEST_BITMAP_ENABLE */
+
+void glcd_test_circles(void)
+{
+ uint8_t x,y,radius;
+
+ unit_test_return = 0;
+ while (1) {
+ uint8_t i;
+
+ glcd_clear();
+
+ // generate random(ish) position on display
+ x = rand() % GLCD_LCD_WIDTH;
+ y = rand() % GLCD_LCD_HEIGHT;
+ radius = rand() % 50;
+
+ //x = 70; y=25; radius=50; // for debugging
+
+ // fill circle with black
+
+ for (i=0; i<=radius; i++) {
+ glcd_fill_circle(x,y,i,BLACK);
+ glcd_write();
+ delay_ms(2);
+ }
+
+ // fill the same circle above but with white
+ for (i=0; i<=radius; i++) {
+ glcd_fill_circle(x,y,i,WHITE);
+ glcd_write();
+ delay_ms(1);
+ }
+ DEMO_RETURN();
+ }
+}
+
+void glcd_test_counter_and_graph(void)
+{
+ uint8_t count = 0;
+ char string[8] = "";
+
+ unit_test_return = 0;
+ while(1) {
+ glcd_clear_buffer();
+
+ //glcd_tiny_set_font(Font5x7,5,7,32,127);
+ //glcd_draw_string_xy(0,40,(char *)utoa(count,string,10));
+
+ glcd_set_font(Liberation_Sans15x21_Numbers,15,21,46,57);
+ //glcd_set_font(Liberation_Sans27x36_Numbers,27,36,46,57);
+ //glcd_set_font(Bebas_Neue20x36_Bold_Numbers,20,36,46,57);
+ //glcd_set_font(Bebas_Neue18x36_Numbers,18,36,46,57);
+ //glcd_set_font(HelveticaNeueLT_Com_57_Cn23x35_Numbers,23,35,46,57); // commercial font - not for public distribution
+
+ sprintf(string,"%d",count);
+ glcd_draw_string_xy(0,0,string);
+ glcd_bar_graph_horizontal(10,38,30,6,count*4);
+ glcd_bar_graph_vertical(70,0,8,30,count*2);
+
+ glcd_write();
+ count += 1;
+
+ DEMO_RETURN();
+ }
+
+}
+
+/* Test glcd-utils font table type, increments and display a 16-bit number over and over */
+#include "Earthbound_12x19_48to57.h"
+void glcd_test_glcdutils(void)
+{
+ uint16_t count = 0;
+ char string[8] = "";
+
+ unit_test_return = 0;
+ while(1) {
+ glcd_clear_buffer();
+
+ /* Set the font */
+ glcd_font(font_Earthbound_12x19_48to57,12,19,48,57,GLCD_UTILS);
+
+ sprintf(string,"%d",count);
+ glcd_draw_string_xy(0,0,string);
+ glcd_write();
+
+ count += 1;
+
+ DEMO_RETURN();
+ }
+}
+
+void glcd_test_text_up_down(void)
+{
+ // moves some text up and down the display
+
+ uint8_t y;
+ uint8_t max_y;
+
+ //glcd_set_font(Liberation_Sans11x14_Numbers,11,14,46,57);
+ glcd_set_font(Liberation_Sans15x21_Numbers,15,21,46,57);
+ //glcd_set_font(Liberation_Sans27x36_Numbers,27,36,46,57);
+ //glcd_set_font(Liberation_Sans17x17_Alpha,17,17,46,90);
+
+ max_y = GLCD_LCD_HEIGHT - font_current.height - 2; // max y start position for draw_string
+
+ unit_test_return = 0;
+ while(1) {
+ // move top to bottom
+ for (y=0; y<max_y; y++) {
+ DEMO_RETURN();
+ glcd_clear_buffer();
+ glcd_draw_string_xy(0,y,"123");
+ glcd_write();
+ delay_ms(80);
+ }
+
+ // move bottom to top
+ for (y=(max_y); y>0; y--) {
+ DEMO_RETURN();
+ glcd_clear_buffer();
+ glcd_draw_string_xy(0,y,"456");
+ glcd_write();
+ delay_ms(80);
+ }
+
+ }
+
+}
+
+void glcd_test_tiny_text(void)
+{
+ /* Write tiny text on display, all chars, scrolling up every second */
+
+ char string[GLCD_LCD_WIDTH / 6 + 1];
+
+ uint8_t c = 32;
+ uint8_t len = GLCD_LCD_WIDTH / 6;
+
+ GLCD_TEXT_INIT();
+
+ unit_test_return = 0;
+ while(1) {
+ // write chars to string from 32 to 127 ASCII
+ uint8_t i;
+ for (i=0; i<len; i++) {
+ string[i] = c;
+ c++;
+ if (c > 127) {
+ c = 32;
+ }
+ }
+
+ // write null terminator
+ string[len] = '\0';
+
+ GLCD_WRITE(string);
+
+ DEMO_RETURN();
+
+ delay_ms(1000);
+ }
+
+}
+
+void glcd_test_hello_world(void)
+{
+ glcd_tiny_set_font(Font5x7,5,7,32,127);
+ glcd_clear_buffer();
+ glcd_tiny_draw_string(0,0,"Hello World!");
+ glcd_write();
+
+ unit_test_return = 0;
+ while(1) {
+ DEMO_RETURN();
+ }
+}
+
+void glcd_test_rectangles(void)
+{
+ glcd_tiny_set_font(Font5x7,5,7,32,127);
+ glcd_clear_buffer();
+ glcd_tiny_draw_string(0,0,"RECTANGLE DEMO");
+ glcd_write();
+ delay_ms(200);
+
+ unit_test_return = 0;
+ while(1) {
+
+ //glcd_clear();
+ glcd_draw_rect(0,0,100,50,BLACK);
+ glcd_tiny_draw_string(0,GLCD_NUMBER_OF_BANKS-1,"glcd_draw_rect");
+ glcd_write();
+ delay_ms(500);
+ DEMO_RETURN();
+
+ glcd_clear();
+ glcd_tiny_draw_string(0,GLCD_NUMBER_OF_BANKS-1,"glcd_draw_rect_thick");
+ glcd_write();
+
+ glcd_draw_rect_thick(5,5,80,30,3,6,BLACK);
+ glcd_write();
+ delay_ms(500);
+ DEMO_RETURN();
+
+ glcd_draw_rect_thick(0,0,20,20,2,2,BLACK);
+ glcd_write();
+ delay_ms(500);
+ DEMO_RETURN();
+
+ glcd_draw_rect_thick(100,10,20,20,5,5,BLACK);
+ glcd_write();
+ delay_ms(500);
+ DEMO_RETURN();
+
+ glcd_clear();
+ glcd_tiny_draw_string(0,GLCD_NUMBER_OF_BANKS-1,"glcd_draw_rect_shadow");
+ glcd_draw_rect_shadow(0,0,45,30,BLACK);
+ glcd_write();
+ delay_ms(500);
+ DEMO_RETURN();
+
+ glcd_draw_rect_shadow(95,5,30,30,BLACK);
+ glcd_write();
+ delay_ms(500);
+ DEMO_RETURN();
+
+ }
+
+}
+
+void glcd_test_scrolling_graph(void)
+{
+ glcd_clear();
+ glcd_write();
+
+ unit_test_return = 0;
+ while(1) {
+ uint16_t n;
+ for (n=0; n<=255; n += 20) {
+ glcd_scrolling_bar_graph(0,0,50,50,n);
+ glcd_scrolling_bar_graph(60,0,50,30,n);
+ glcd_scrolling_bar_graph(60,35,60,20,n);
+ DEMO_RETURN();
+ }
+ for (n=0; n<=255; n += 20) {
+ glcd_scrolling_bar_graph(0,0,50,50,255-n);
+ glcd_scrolling_bar_graph(60,0,50,30,n);
+ glcd_scrolling_bar_graph(60,35,60,20,n);
+ DEMO_RETURN();
+ }
+ }
+}
+
+#if defined (GLCD_UNIT_TEST_BITMAP_ENABLE)
+void glcd_test_bitmap_128x64(void)
+{
+ glcd_draw_bitmap(bmp_oslogo);
+
+ unit_test_return = 0;
+ glcd_write();
+ while (1) {
+ DEMO_RETURN();
+ }
+}
+#endif
diff --git a/lcd/unit_tests.h b/lcd/unit_tests.h
new file mode 100644
index 0000000..f3540ba
--- /dev/null
+++ b/lcd/unit_tests.h
@@ -0,0 +1,71 @@
+/**
+ * \file unit_tests.h
+ * \brief Various test functions to demonstrate features of the library
+ * \author Andy Gock
+ */
+
+/*
+ Copyright (c) 2012, Andy Gock
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Andy Gock nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL ANDY GOCK BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _UNIT_TESTS_H
+#define _UNIT_TESTS_H
+
+#include "stdint.h"
+
+#define GLCD_UNIT_TEST_BITMAP_ENABLE
+
+extern volatile uint8_t unit_test_return;
+
+/** Make random "exploding circles" */
+void glcd_test_circles(void);
+
+/* Shows a 8-bit counter incorementing, with a verticla and horizontal bar graph */
+void glcd_test_counter_and_graph(void);
+
+/* Shows a 16-bit counter incrementing, using glcdutils font format */
+void glcd_test_glcdutils(void);
+
+/** Scroll some text up and down the screen */
+void glcd_test_text_up_down(void);
+
+/** Display all chars of tiny 5x7 font, scrolling previous lines one by one every second */
+void glcd_test_tiny_text(void);
+
+/** Print hello world to display */
+void glcd_test_hello_world(void);
+
+/** Demonstrating rectangle drawing */
+void glcd_test_rectangles(void);
+
+/** Demonstrate scrolling bar graph */
+void glcd_test_scrolling_graph(void);
+
+/** Demonstrate bitmap display */
+void glcd_test_bitmap_128x64(void);
+
+#endif
diff --git a/libqr/qrencode.c b/libqr/qrencode.c
new file mode 100644
index 0000000..f083724
--- /dev/null
+++ b/libqr/qrencode.c
@@ -0,0 +1,1474 @@
+#include <string.h>
+
+#include "qrencode.h"
+
+typedef enum
+{
+ FALSE = 0,
+ TRUE = !FALSE
+} bool;
+
+typedef unsigned char BYTE;
+typedef unsigned int WORD;
+
+#define QR_LEVEL_L 0
+#define QR_LEVEL_M 1
+#define QR_LEVEL_Q 2
+#define QR_LEVEL_H 3
+
+#define QR_MODE_NUMERAL 0
+#define QR_MODE_ALPHABET 1
+#define QR_MODE_8BIT 2
+
+#define QR_VRESION_S 0
+#define QR_VRESION_M 1
+#define QR_VRESION_L 2
+
+#define MAX_ALLCODEWORD 172 //733ÊÇ°æ±¾16ÐèÒªµÄ×î´ó¿Õ¼ä
+#define MAX_DATACODEWORD 136 //589ÊÇ°æ±¾16ÐèÒªµÄ×î´ó¿Õ¼ä
+#define MAX_CODEBLOCK 153
+
+/////////////////////////////////////////////////////////////////////////////
+
+struct RS_BLOCKINFO
+{
+ int ncRSBlock;
+ int ncAllCodeWord;
+ int ncDataCodeWord;
+};
+
+struct QR_VERSIONINFO
+{
+ int nVersionNo;
+ int ncAllCodeWord;
+
+ int ncDataCodeWord[4];
+ int ncAlignPoint;
+ int nAlignPoint[6];
+
+ struct RS_BLOCKINFO RS_BlockInfo1[4];
+ struct RS_BLOCKINFO RS_BlockInfo2[4];
+};
+
+static const struct QR_VERSIONINFO QR_VersonInfo[] = {{0}, // Ver.0
+ {
+ 1, // Ver.1
+ 26, 19, 16, 13, 9,
+ 0, 0, 0, 0, 0, 0, 0,
+ 1, 26, 19,
+ 1, 26, 16,
+ 1, 26, 13,
+ 1, 26, 9,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ 2, // Ver.2
+ 44, 34, 28, 22, 16,
+ 1, 18, 0, 0, 0, 0, 0,
+ 1, 44, 34,
+ 1, 44, 28,
+ 1, 44, 22,
+ 1, 44, 16,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ 3, // Ver.3
+ 70, 55, 44, 34, 26,
+ 1, 22, 0, 0, 0, 0, 0,
+ 1, 70, 55,
+ 1, 70, 44,
+ 2, 35, 17,
+ 2, 35, 13,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ 4, // Ver.4
+ 100, 80, 64, 48, 36,
+ 1, 26, 0, 0, 0, 0, 0,
+ 1, 100, 80,
+ 2, 50, 32,
+ 2, 50, 24,
+ 4, 25, 9,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0
+ },
+ {
+ 5, // Ver.5
+ 134, 108, 86, 62, 46,
+ 1, 30, 0, 0, 0, 0, 0,
+ 1, 134, 108,
+ 2, 67, 43,
+ 2, 33, 15,
+ 2, 33, 11,
+ 0, 0, 0,
+ 0, 0, 0,
+ 2, 34, 16,
+ 2, 34, 12
+ },
+ {
+ 6, // Ver.6
+ 172, 136, 108, 76, 60,
+ 1, 34, 0, 0, 0, 0, 0,
+ 2, 86, 68,
+ 4, 43, 27,
+ 4, 43, 19,
+ 4, 43, 15,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0,
+ 0, 0, 0
+ },
+};
+
+
+/////////////////////////////////////////////////////////////////////////////
+static const BYTE byExpToInt[] = { 1, 2, 4, 8, 16, 32, 64, 128, 29, 58, 116, 232, 205, 135, 19, 38,
+ 76, 152, 45, 90, 180, 117, 234, 201, 143, 3, 6, 12, 24, 48, 96, 192,
+ 157, 39, 78, 156, 37, 74, 148, 53, 106, 212, 181, 119, 238, 193, 159, 35,
+ 70, 140, 5, 10, 20, 40, 80, 160, 93, 186, 105, 210, 185, 111, 222, 161,
+ 95, 190, 97, 194, 153, 47, 94, 188, 101, 202, 137, 15, 30, 60, 120, 240,
+ 253, 231, 211, 187, 107, 214, 177, 127, 254, 225, 223, 163, 91, 182, 113, 226,
+ 217, 175, 67, 134, 17, 34, 68, 136, 13, 26, 52, 104, 208, 189, 103, 206,
+ 129, 31, 62, 124, 248, 237, 199, 147, 59, 118, 236, 197, 151, 51, 102, 204,
+ 133, 23, 46, 92, 184, 109, 218, 169, 79, 158, 33, 66, 132, 21, 42, 84,
+ 168, 77, 154, 41, 82, 164, 85, 170, 73, 146, 57, 114, 228, 213, 183, 115,
+ 230, 209, 191, 99, 198, 145, 63, 126, 252, 229, 215, 179, 123, 246, 241, 255,
+ 227, 219, 171, 75, 150, 49, 98, 196, 149, 55, 110, 220, 165, 87, 174, 65,
+ 130, 25, 50, 100, 200, 141, 7, 14, 28, 56, 112, 224, 221, 167, 83, 166,
+ 81, 162, 89, 178, 121, 242, 249, 239, 195, 155, 43, 86, 172, 69, 138, 9,
+ 18, 36, 72, 144, 61, 122, 244, 245, 247, 243, 251, 235, 203, 139, 11, 22,
+ 44, 88, 176, 125, 250, 233, 207, 131, 27, 54, 108, 216, 173, 71, 142, 1
+ };
+
+
+/////////////////////////////////////////////////////////////////////////////
+static const BYTE byIntToExp[] = { 0, 0, 1, 25, 2, 50, 26, 198, 3, 223, 51, 238, 27, 104, 199, 75,
+ 4, 100, 224, 14, 52, 141, 239, 129, 28, 193, 105, 248, 200, 8, 76, 113,
+ 5, 138, 101, 47, 225, 36, 15, 33, 53, 147, 142, 218, 240, 18, 130, 69,
+ 29, 181, 194, 125, 106, 39, 249, 185, 201, 154, 9, 120, 77, 228, 114, 166,
+ 6, 191, 139, 98, 102, 221, 48, 253, 226, 152, 37, 179, 16, 145, 34, 136,
+ 54, 208, 148, 206, 143, 150, 219, 189, 241, 210, 19, 92, 131, 56, 70, 64,
+ 30, 66, 182, 163, 195, 72, 126, 110, 107, 58, 40, 84, 250, 133, 186, 61,
+ 202, 94, 155, 159, 10, 21, 121, 43, 78, 212, 229, 172, 115, 243, 167, 87,
+ 7, 112, 192, 247, 140, 128, 99, 13, 103, 74, 222, 237, 49, 197, 254, 24,
+ 227, 165, 153, 119, 38, 184, 180, 124, 17, 68, 146, 217, 35, 32, 137, 46,
+ 55, 63, 209, 91, 149, 188, 207, 205, 144, 135, 151, 178, 220, 252, 190, 97,
+ 242, 86, 211, 171, 20, 42, 93, 158, 132, 60, 57, 83, 71, 109, 65, 162,
+ 31, 45, 67, 216, 183, 123, 164, 118, 196, 23, 73, 236, 127, 12, 111, 246,
+ 108, 161, 59, 82, 41, 157, 85, 170, 251, 96, 134, 177, 187, 204, 62, 90,
+ 203, 89, 95, 176, 156, 169, 160, 81, 11, 245, 22, 235, 122, 117, 44, 215,
+ 79, 174, 213, 233, 230, 231, 173, 232, 116, 214, 244, 234, 168, 80, 88, 175
+ };
+
+
+/////////////////////////////////////////////////////////////////////////////
+static const BYTE byRSExp7[] = {87, 229, 146, 149, 238, 102, 21};
+static const BYTE byRSExp10[] = {251, 67, 46, 61, 118, 70, 64, 94, 32, 45};
+static const BYTE byRSExp13[] = { 74, 152, 176, 100, 86, 100, 106, 104, 130, 218, 206, 140, 78};
+static const BYTE byRSExp15[] = { 8, 183, 61, 91, 202, 37, 51, 58, 58, 237, 140, 124, 5, 99, 105};
+static const BYTE byRSExp16[] = {120, 104, 107, 109, 102, 161, 76, 3, 91, 191, 147, 169, 182, 194, 225, 120};
+static const BYTE byRSExp17[] = { 43, 139, 206, 78, 43, 239, 123, 206, 214, 147, 24, 99, 150, 39, 243, 163, 136};
+static const BYTE byRSExp18[] = {215, 234, 158, 94, 184, 97, 118, 170, 79, 187, 152, 148, 252, 179, 5, 98, 96, 153};
+static const BYTE byRSExp20[] = { 17, 60, 79, 50, 61, 163, 26, 187, 202, 180, 221, 225, 83, 239, 156, 164, 212, 212, 188, 190};
+static const BYTE byRSExp22[] = {210, 171, 247, 242, 93, 230, 14, 109, 221, 53, 200, 74, 8, 172, 98, 80, 219, 134, 160, 105,
+ 165, 231
+ };
+static const BYTE byRSExp24[] = {229, 121, 135, 48, 211, 117, 251, 126, 159, 180, 169, 152, 192, 226, 228, 218, 111, 0, 117, 232,
+ 87, 96, 227, 21
+ };
+static const BYTE byRSExp26[] = {173, 125, 158, 2, 103, 182, 118, 17, 145, 201, 111, 28, 165, 53, 161, 21, 245, 142, 13, 102,
+ 48, 227, 153, 145, 218, 70
+ };
+static const BYTE byRSExp28[] = {168, 223, 200, 104, 224, 234, 108, 180, 110, 190, 195, 147, 205, 27, 232, 201, 21, 43, 245, 87,
+ 42, 195, 212, 119, 242, 37, 9, 123
+ };
+static const BYTE byRSExp30[] = { 41, 173, 145, 152, 216, 31, 179, 182, 50, 48, 110, 86, 239, 96, 222, 125, 42, 173, 226, 193,
+ 224, 130, 156, 37, 251, 216, 238, 40, 192, 180
+ };
+static const BYTE byRSExp32[] = { 10, 6, 106, 190, 249, 167, 4, 67, 209, 138, 138, 32, 242, 123, 89, 27, 120, 185, 80, 156,
+ 38, 69, 171, 60, 28, 222, 80, 52, 254, 185, 220, 241
+ };
+static const BYTE byRSExp34[] = {111, 77, 146, 94, 26, 21, 108, 19, 105, 94, 113, 193, 86, 140, 163, 125, 58, 158, 229, 239,
+ 218, 103, 56, 70, 114, 61, 183, 129, 167, 13, 98, 62, 129, 51
+ };
+static const BYTE byRSExp36[] = {200, 183, 98, 16, 172, 31, 246, 234, 60, 152, 115, 0, 167, 152, 113, 248, 238, 107, 18, 63,
+ 218, 37, 87, 210, 105, 177, 120, 74, 121, 196, 117, 251, 113, 233, 30, 120
+ };
+static const BYTE byRSExp38[] = {159, 34, 38, 228, 230, 59, 243, 95, 49, 218, 176, 164, 20, 65, 45, 111, 39, 81, 49, 118,
+ 113, 222, 193, 250, 242, 168, 217, 41, 164, 247, 177, 30, 238, 18, 120, 153, 60, 193
+ };
+static const BYTE byRSExp40[] = { 59, 116, 79, 161, 252, 98, 128, 205, 128, 161, 247, 57, 163, 56, 235, 106, 53, 26, 187, 174,
+ 226, 104, 170, 7, 175, 35, 181, 114, 88, 41, 47, 163, 125, 134, 72, 20, 232, 53, 35, 15
+ };
+static const BYTE byRSExp42[] = {250, 103, 221, 230, 25, 18, 137, 231, 0, 3, 58, 242, 221, 191, 110, 84, 230, 8, 188, 106,
+ 96, 147, 15, 131, 139, 34, 101, 223, 39, 101, 213, 199, 237, 254, 201, 123, 171, 162, 194, 117,
+ 50, 96
+ };
+static const BYTE byRSExp44[] = {190, 7, 61, 121, 71, 246, 69, 55, 168, 188, 89, 243, 191, 25, 72, 123, 9, 145, 14, 247,
+ 1, 238, 44, 78, 143, 62, 224, 126, 118, 114, 68, 163, 52, 194, 217, 147, 204, 169, 37, 130,
+ 113, 102, 73, 181
+ };
+static const BYTE byRSExp46[] = {112, 94, 88, 112, 253, 224, 202, 115, 187, 99, 89, 5, 54, 113, 129, 44, 58, 16, 135, 216,
+ 169, 211, 36, 1, 4, 96, 60, 241, 73, 104, 234, 8, 249, 245, 119, 174, 52, 25, 157, 224,
+ 43, 202, 223, 19, 82, 15
+ };
+static const BYTE byRSExp48[] = {228, 25, 196, 130, 211, 146, 60, 24, 251, 90, 39, 102, 240, 61, 178, 63, 46, 123, 115, 18,
+ 221, 111, 135, 160, 182, 205, 107, 206, 95, 150, 120, 184, 91, 21, 247, 156, 140, 238, 191, 11,
+ 94, 227, 84, 50, 163, 39, 34, 108
+ };
+static const BYTE byRSExp50[] = {232, 125, 157, 161, 164, 9, 118, 46, 209, 99, 203, 193, 35, 3, 209, 111, 195, 242, 203, 225,
+ 46, 13, 32, 160, 126, 209, 130, 160, 242, 215, 242, 75, 77, 42, 189, 32, 113, 65, 124, 69,
+ 228, 114, 235, 175, 124, 170, 215, 232, 133, 205
+ };
+static const BYTE byRSExp52[] = {116, 50, 86, 186, 50, 220, 251, 89, 192, 46, 86, 127, 124, 19, 184, 233, 151, 215, 22, 14,
+ 59, 145, 37, 242, 203, 134, 254, 89, 190, 94, 59, 65, 124, 113, 100, 233, 235, 121, 22, 76,
+ 86, 97, 39, 242, 200, 220, 101, 33, 239, 254, 116, 51
+ };
+static const BYTE byRSExp54[] = {183, 26, 201, 87, 210, 221, 113, 21, 46, 65, 45, 50, 238, 184, 249, 225, 102, 58, 209, 218,
+ 109, 165, 26, 95, 184, 192, 52, 245, 35, 254, 238, 175, 172, 79, 123, 25, 122, 43, 120, 108,
+ 215, 80, 128, 201, 235, 8, 153, 59, 101, 31, 198, 76, 31, 156
+ };
+static const BYTE byRSExp56[] = {106, 120, 107, 157, 164, 216, 112, 116, 2, 91, 248, 163, 36, 201, 202, 229, 6, 144, 254, 155,
+ 135, 208, 170, 209, 12, 139, 127, 142, 182, 249, 177, 174, 190, 28, 10, 85, 239, 184, 101, 124,
+ 152, 206, 96, 23, 163, 61, 27, 196, 247, 151, 154, 202, 207, 20, 61, 10
+ };
+static const BYTE byRSExp58[] = { 82, 116, 26, 247, 66, 27, 62, 107, 252, 182, 200, 185, 235, 55, 251, 242, 210, 144, 154, 237,
+ 176, 141, 192, 248, 152, 249, 206, 85, 253, 142, 65, 165, 125, 23, 24, 30, 122, 240, 214, 6,
+ 129, 218, 29, 145, 127, 134, 206, 245, 117, 29, 41, 63, 159, 142, 233, 125, 148, 123
+ };
+static const BYTE byRSExp60[] = {107, 140, 26, 12, 9, 141, 243, 197, 226, 197, 219, 45, 211, 101, 219, 120, 28, 181, 127, 6,
+ 100, 247, 2, 205, 198, 57, 115, 219, 101, 109, 160, 82, 37, 38, 238, 49, 160, 209, 121, 86,
+ 11, 124, 30, 181, 84, 25, 194, 87, 65, 102, 190, 220, 70, 27, 209, 16, 89, 7, 33, 240
+ };
+static const BYTE byRSExp62[] = { 65, 202, 113, 98, 71, 223, 248, 118, 214, 94, 0, 122, 37, 23, 2, 228, 58, 121, 7, 105,
+ 135, 78, 243, 118, 70, 76, 223, 89, 72, 50, 70, 111, 194, 17, 212, 126, 181, 35, 221, 117,
+ 235, 11, 229, 149, 147, 123, 213, 40, 115, 6, 200, 100, 26, 246, 182, 218, 127, 215, 36, 186,
+ 110, 106
+ };
+static const BYTE byRSExp64[] = { 45, 51, 175, 9, 7, 158, 159, 49, 68, 119, 92, 123, 177, 204, 187, 254, 200, 78, 141, 149,
+ 119, 26, 127, 53, 160, 93, 199, 212, 29, 24, 145, 156, 208, 150, 218, 209, 4, 216, 91, 47,
+ 184, 146, 47, 140, 195, 195, 125, 242, 238, 63, 99, 108, 140, 230, 242, 31, 204, 11, 178, 243,
+ 217, 156, 213, 231
+ };
+static const BYTE byRSExp66[] = { 5, 118, 222, 180, 136, 136, 162, 51, 46, 117, 13, 215, 81, 17, 139, 247, 197, 171, 95, 173,
+ 65, 137, 178, 68, 111, 95, 101, 41, 72, 214, 169, 197, 95, 7, 44, 154, 77, 111, 236, 40,
+ 121, 143, 63, 87, 80, 253, 240, 126, 217, 77, 34, 232, 106, 50, 168, 82, 76, 146, 67, 106,
+ 171, 25, 132, 93, 45, 105
+ };
+static const BYTE byRSExp68[] = {247, 159, 223, 33, 224, 93, 77, 70, 90, 160, 32, 254, 43, 150, 84, 101, 190, 205, 133, 52,
+ 60, 202, 165, 220, 203, 151, 93, 84, 15, 84, 253, 173, 160, 89, 227, 52, 199, 97, 95, 231,
+ 52, 177, 41, 125, 137, 241, 166, 225, 118, 2, 54, 32, 82, 215, 175, 198, 43, 238, 235, 27,
+ 101, 184, 127, 3, 5, 8, 163, 238
+ };
+
+static const BYTE* byRSExp[] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, byRSExp7, NULL, NULL,
+ byRSExp10, NULL, NULL, byRSExp13, NULL, byRSExp15, byRSExp16, byRSExp17, byRSExp18, NULL,
+ byRSExp20, NULL, byRSExp22, NULL, byRSExp24, NULL, byRSExp26, NULL, byRSExp28, NULL,
+ byRSExp30, NULL, byRSExp32, NULL, byRSExp34, NULL, byRSExp36, NULL, byRSExp38, NULL,
+ byRSExp40, NULL, byRSExp42, NULL, byRSExp44, NULL, byRSExp46, NULL, byRSExp48, NULL,
+ byRSExp50, NULL, byRSExp52, NULL, byRSExp54, NULL, byRSExp56, NULL, byRSExp58, NULL,
+ byRSExp60, NULL, byRSExp62, NULL, byRSExp64, NULL, byRSExp66, NULL, byRSExp68
+ };
+
+static const int nIndicatorLenNumeral[] = {10, 12, 14};
+static const int nIndicatorLenAlphabet[] = { 9, 11, 13};
+static const int nIndicatorLen8Bit[] = { 8, 16, 16};
+
+static int m_ncDataCodeWordBit;
+static BYTE m_byDataCodeWord[MAX_DATACODEWORD];
+
+static int m_ncDataBlock;
+static BYTE m_byBlockMode[MAX_DATACODEWORD];
+static int m_nBlockLength[MAX_DATACODEWORD];
+
+static int m_ncAllCodeWord;
+static BYTE m_byAllCodeWord[MAX_ALLCODEWORD];
+static BYTE m_byRSWork[MAX_CODEBLOCK];
+
+static int m_nLevel;
+static int m_nVersion;
+static int m_nMaskingNo;
+
+int m_nSymbleSize;
+BYTE m_byModuleData[MAX_MODULESIZE][MAX_MODULESIZE];
+
+#define min(a,b) (((a) < (b)) ? (a) : (b))
+
+static bool IsNumeralData(unsigned char c)
+{
+ if(c >= '0' && c <= '9')
+ return TRUE;
+
+ return FALSE;
+}
+
+static bool IsAlphabetData(unsigned char c)
+{
+ if(c >= '0' && c <= '9')
+ return TRUE;
+
+ if(c >= 'A' && c <= 'Z')
+ return TRUE;
+
+ if(c == ' ' || c == '$' || c == '%' || c == '*' || c == '+' || c == '-' || c == '.'
+ || c == '/' || c == ':')
+ return TRUE;
+
+ return FALSE;
+}
+
+static BYTE AlphabetToBinaly(BYTE c)
+{
+ if(c >= '0' && c <= '9') return (BYTE)(c - '0');
+
+ if(c >= 'A' && c <= 'Z') return (BYTE)(c - 'A' + 10);
+
+ if(c == ' ') return 36;
+
+ if(c == '$') return 37;
+
+ if(c == '%') return 38;
+
+ if(c == '*') return 39;
+
+ if(c == '+') return 40;
+
+ if(c == '-') return 41;
+
+ if(c == '.') return 42;
+
+ if(c == '/') return 43;
+
+ return 44;
+}
+static int GetBitLength(BYTE nMode, int ncData, int nVerGroup)
+{
+ int ncBits = 0;
+
+ switch(nMode)
+ {
+ case QR_MODE_NUMERAL:
+ ncBits = 4 + nIndicatorLenNumeral[nVerGroup] + (10 * (ncData / 3));
+ switch(ncData % 3)
+ {
+ case 1:
+ ncBits += 4;
+ break;
+ case 2:
+ ncBits += 7;
+ break;
+ default:
+ break;
+ }
+
+ break;
+
+ case QR_MODE_ALPHABET:
+ ncBits = 4 + nIndicatorLenAlphabet[nVerGroup] + (11 * (ncData / 2)) + (6 * (ncData % 2));
+ break;
+
+ case QR_MODE_8BIT:
+ ncBits = 4 + nIndicatorLen8Bit[nVerGroup] + (8 * ncData);
+ break;
+
+ default:
+ break;
+ }
+
+ return ncBits;
+}
+
+static int SetBitStream(int nIndex, WORD wData, int ncData)
+{
+ int i;
+
+ if(nIndex == -1 || nIndex + ncData > MAX_DATACODEWORD * 8)
+ return -1;
+
+ for(i = 0; i < ncData; ++i)
+ {
+ if(wData & (1 << (ncData - i - 1)))
+ {
+ m_byDataCodeWord[(nIndex + i) / 8] |= 1 << (7 - ((nIndex + i) % 8));
+ }
+ }
+
+ return nIndex + ncData;
+}
+
+static void GetRSCodeWord(BYTE* lpbyRSWork, int ncDataCodeWord, int ncRSCodeWord)
+{
+ int i, j;
+
+ for(i = 0; i < ncDataCodeWord ; ++i)
+ {
+ if(lpbyRSWork[0] != 0)
+ {
+ BYTE nExpFirst = byIntToExp[lpbyRSWork[0]];
+
+ for(j = 0; j < ncRSCodeWord; ++j)
+ {
+ BYTE nExpElement = (BYTE)(((int)(byRSExp[ncRSCodeWord][j] + nExpFirst)) % 255);
+
+ lpbyRSWork[j] = (BYTE)(lpbyRSWork[j + 1] ^ byExpToInt[nExpElement]);
+ }
+
+ for(j = ncRSCodeWord; j < ncDataCodeWord + ncRSCodeWord - 1; ++j)
+ lpbyRSWork[j] = lpbyRSWork[j + 1];
+ }
+ else
+ {
+ for(j = 0; j < ncDataCodeWord + ncRSCodeWord - 1; ++j)
+ lpbyRSWork[j] = lpbyRSWork[j + 1];
+ }
+ }
+}
+
+static void SetAlignmentPattern(int x, int y)
+{
+ static BYTE byPattern[] = {0x1f,
+ 0x11,
+ 0x15,
+ 0x11,
+ 0x1f
+ };
+ int i, j;
+
+ if(m_byModuleData[x][y] & 0x20)
+ return;
+
+ x -= 2; y -= 2;
+
+ for(i = 0; i < 5; ++i)
+ {
+ for(j = 0; j < 5; ++j)
+ {
+ m_byModuleData[x + j][y + i] = (byPattern[i] & (1 << (4 - j))) ? '\x30' : '\x20';
+ }
+ }
+}
+static void SetFinderPattern(int x, int y)
+{
+ static BYTE byPattern[] = {0x7f,
+ 0x41,
+ 0x5d,
+ 0x5d,
+ 0x5d,
+ 0x41,
+ 0x7f
+ };
+ int i, j;
+
+ for(i = 0; i < 7; ++i)
+ {
+ for(j = 0; j < 7; ++j)
+ {
+ m_byModuleData[x + j][y + i] = (byPattern[i] & (1 << (6 - j))) ? '\x30' : '\x20';
+ }
+ }
+}
+
+static void SetVersionPattern(void)
+{
+ int i, j;
+ int nVerData;
+
+ if(m_nVersion <= 6)
+ return;
+
+ nVerData = m_nVersion << 12;
+
+ for(i = 0; i < 6; ++i)
+ {
+ if(nVerData & (1 << (17 - i)))
+ {
+ nVerData ^= (0x1f25 << (5 - i));
+ }
+ }
+
+ nVerData += m_nVersion << 12;
+
+ for(i = 0; i < 6; ++i)
+ {
+ for(j = 0; j < 3; ++j)
+ {
+ m_byModuleData[m_nSymbleSize - 11 + j][i] = m_byModuleData[i][m_nSymbleSize - 11 + j] =
+ (nVerData & (1 << (i * 3 + j))) ? '\x30' : '\x20';
+ }
+ }
+}
+
+static void SetCodeWordPattern(void)
+{
+ int x = m_nSymbleSize;
+ int y = m_nSymbleSize - 1;
+
+ int nCoef_x = 1;
+ int nCoef_y = 1;
+
+ int i, j;
+
+ for(i = 0; i < m_ncAllCodeWord; ++i)
+ {
+ for(j = 0; j < 8; ++j)
+ {
+ do
+ {
+ x += nCoef_x;
+ nCoef_x *= -1;
+
+ if(nCoef_x < 0)
+ {
+ y += nCoef_y;
+
+ if(y < 0 || y == m_nSymbleSize)
+ {
+ y = (y < 0) ? 0 : m_nSymbleSize - 1;
+ nCoef_y *= -1;
+
+ x -= 2;
+
+ if(x == 6)
+ --x;
+ }
+ }
+ }
+ while(m_byModuleData[x][y] & 0x20);
+
+ m_byModuleData[x][y] = (m_byAllCodeWord[i] & (1 << (7 - j))) ? '\x02' : '\x00';
+ }
+ }
+}
+
+static void SetMaskingPattern(int nPatternNo)
+{
+ int i, j;
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize; ++j)
+ {
+ if(!(m_byModuleData[j][i] & 0x20))
+ {
+ bool bMask;
+
+ switch(nPatternNo)
+ {
+ case 0:
+ bMask = (bool)((i + j) % 2 == 0);
+ break;
+
+ case 1:
+ bMask = (bool)(i % 2 == 0);
+ break;
+
+ case 2:
+ bMask = (bool)(j % 3 == 0);
+ break;
+
+ case 3:
+ bMask = (bool)((i + j) % 3 == 0);
+ break;
+
+ case 4:
+ bMask = (bool)(((i / 2) + (j / 3)) % 2 == 0);
+ break;
+
+ case 5:
+ bMask = (bool)(((i * j) % 2) + ((i * j) % 3) == 0);
+ break;
+
+ case 6:
+ bMask = (bool)((((i * j) % 2) + ((i * j) % 3)) % 2 == 0);
+ break;
+
+ default:
+ bMask = (bool)((((i * j) % 3) + ((i + j) % 2)) % 2 == 0);
+ break;
+ }
+
+ m_byModuleData[j][i] = (BYTE)((m_byModuleData[j][i] & 0xfe) | (((
+ m_byModuleData[j][i] & 0x02) > 1) ^ bMask));
+ }
+ }
+ }
+}
+
+static void SetFormatInfoPattern(int nPatternNo)
+{
+ int nFormatInfo;
+ int i;
+ int nFormatData;
+
+ switch(m_nLevel)
+ {
+ case QR_LEVEL_M:
+ nFormatInfo = 0x00;
+ break;
+
+ case QR_LEVEL_L:
+ nFormatInfo = 0x08;
+ break;
+
+ case QR_LEVEL_Q:
+ nFormatInfo = 0x18;
+ break;
+
+ default:
+ nFormatInfo = 0x10;
+ break;
+ }
+
+ nFormatInfo += nPatternNo;
+
+ nFormatData = nFormatInfo << 10;
+
+ for(i = 0; i < 5; ++i)
+ {
+ if(nFormatData & (1 << (14 - i)))
+ {
+ nFormatData ^= (0x0537 << (4 - i));
+ }
+ }
+
+ nFormatData += nFormatInfo << 10;
+
+ nFormatData ^= 0x5412;
+
+ for(i = 0; i <= 5; ++i)
+ m_byModuleData[8][i] = (nFormatData & (1 << i)) ? '\x30' : '\x20';
+
+ m_byModuleData[8][7] = (nFormatData & (1 << 6)) ? '\x30' : '\x20';
+ m_byModuleData[8][8] = (nFormatData & (1 << 7)) ? '\x30' : '\x20';
+ m_byModuleData[7][8] = (nFormatData & (1 << 8)) ? '\x30' : '\x20';
+
+ for(i = 9; i <= 14; ++i)
+ m_byModuleData[14 - i][8] = (nFormatData & (1 << i)) ? '\x30' : '\x20';
+
+ for(i = 0; i <= 7; ++i)
+ m_byModuleData[m_nSymbleSize - 1 - i][8] = (nFormatData & (1 << i)) ? '\x30' : '\x20';
+
+ m_byModuleData[8][m_nSymbleSize - 8] = '\x30';
+
+ for(i = 8; i <= 14; ++i)
+ m_byModuleData[8][m_nSymbleSize - 15 + i] = (nFormatData & (1 << i)) ? '\x30' : '\x20';
+}
+
+static int CountPenalty(void)
+{
+ int nPenalty = 0;
+ int i, j, k;
+ int nCount = 0, s_nCount;
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize - 4; ++j)
+ {
+ int nCount = 1;
+
+ for(k = j + 1; k < m_nSymbleSize; k++)
+ {
+ if(((m_byModuleData[i][j] & 0x11) == 0) == ((m_byModuleData[i][k] & 0x11) == 0))
+ ++nCount;
+ else
+ break;
+ }
+
+ if(nCount >= 5)
+ {
+ nPenalty += 3 + (nCount - 5);
+ }
+
+ j = k - 1;
+ }
+ }
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize - 4; ++j)
+ {
+ int nCount = 1;
+
+ for(k = j + 1; k < m_nSymbleSize; k++)
+ {
+ if(((m_byModuleData[j][i] & 0x11) == 0) == ((m_byModuleData[k][i] & 0x11) == 0))
+ ++nCount;
+ else
+ break;
+ }
+
+ if(nCount >= 5)
+ {
+ nPenalty += 3 + (nCount - 5);
+ }
+
+ j = k - 1;
+ }
+ }
+
+ for(i = 0; i < m_nSymbleSize - 1; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize - 1; ++j)
+ {
+ if((((m_byModuleData[i][j] & 0x11) == 0) == ((m_byModuleData[i + 1][j] & 0x11) == 0)) &&
+ (((m_byModuleData[i][j] & 0x11) == 0) == ((m_byModuleData[i] [j + 1] & 0x11) == 0)) &&
+ (((m_byModuleData[i][j] & 0x11) == 0) == ((m_byModuleData[i + 1][j + 1] & 0x11) == 0)))
+ {
+ nPenalty += 3;
+ }
+ }
+ }
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize - 6; ++j)
+ {
+ if(((j == 0) || (!(m_byModuleData[i][j - 1] & 0x11))) && // Ã÷»ò·ûºÅÍâ
+ (m_byModuleData[i][j] & 0x11) && // °µ - 1
+ (!(m_byModuleData[i][j + 1] & 0x11)) && // Ã÷ - 1
+ (m_byModuleData[i][j + 2] & 0x11) && // °µ ©´
+ (m_byModuleData[i][j + 3] & 0x11) && // °µ ©¦3
+ (m_byModuleData[i][j + 4] & 0x11) && // °µ ©¼
+ (!(m_byModuleData[i][j + 5] & 0x11)) && // Ã÷ - 1
+ (m_byModuleData[i][j + 6] & 0x11) && // °µ - 1
+ ((j == m_nSymbleSize - 7) || (!(m_byModuleData[i][j + 7] & 0x11)))) // Ã÷»ò·ûºÅÍâ
+ {
+ if(((j < 2 || !(m_byModuleData[i][j - 2] & 0x11)) &&
+ (j < 3 || !(m_byModuleData[i][j - 3] & 0x11)) &&
+ (j < 4 || !(m_byModuleData[i][j - 4] & 0x11))) ||
+ ((j >= m_nSymbleSize - 8 || !(m_byModuleData[i][j + 8] & 0x11)) &&
+ (j >= m_nSymbleSize - 9 || !(m_byModuleData[i][j + 9] & 0x11)) &&
+ (j >= m_nSymbleSize - 10 || !(m_byModuleData[i][j + 10] & 0x11))))
+ {
+ nPenalty += 40;
+ }
+ }
+ }
+ }
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize - 6; ++j)
+ {
+ if(((j == 0) || (!(m_byModuleData[j - 1][i] & 0x11))) && // Ã÷»ò·ûºÅÍâ
+ (m_byModuleData[j] [i] & 0x11) && // °µ - 1
+ (!(m_byModuleData[j + 1][i] & 0x11)) && // Ã÷ - 1
+ (m_byModuleData[j + 2][i] & 0x11) && // °µ ©´
+ (m_byModuleData[j + 3][i] & 0x11) && // °µ ©¦3
+ (m_byModuleData[j + 4][i] & 0x11) && // °µ ©¼
+ (!(m_byModuleData[j + 5][i] & 0x11)) && // Ã÷ - 1
+ (m_byModuleData[j + 6][i] & 0x11) && // °µ - 1
+ ((j == m_nSymbleSize - 7) || (!(m_byModuleData[j + 7][i] & 0x11)))) // Ã÷»ò·ûºÅÍâ
+ {
+ if(((j < 2 || !(m_byModuleData[j - 2][i] & 0x11)) &&
+ (j < 3 || !(m_byModuleData[j - 3][i] & 0x11)) &&
+ (j < 4 || !(m_byModuleData[j - 4][i] & 0x11))) ||
+ ((j >= m_nSymbleSize - 8 || !(m_byModuleData[j + 8][i] & 0x11)) &&
+ (j >= m_nSymbleSize - 9 || !(m_byModuleData[j + 9][i] & 0x11)) &&
+ (j >= m_nSymbleSize - 10 || !(m_byModuleData[j + 10][i] & 0x11))))
+ {
+ nPenalty += 40;
+ }
+ }
+ }
+ }
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize; ++j)
+ {
+ if(!(m_byModuleData[i][j] & 0x11))
+ {
+ ++nCount;
+ }
+ }
+ }
+
+ if((50 - ((nCount * 100) / (m_nSymbleSize * m_nSymbleSize))) > 0)
+ s_nCount = 50 - ((nCount * 100) / (m_nSymbleSize * m_nSymbleSize));
+ else
+ s_nCount = 0 - (50 - ((nCount * 100) / (m_nSymbleSize * m_nSymbleSize)));
+ nPenalty += (s_nCount / 5) * 10;
+
+ return nPenalty;
+}
+
+static bool EncodeSourceData(char* lpsSource, int ncLength, int nVerGroup)
+{
+ int i, j;
+ int ncSrcBits, ncDstBits;
+ int nBlock = 0;
+ int ncComplete = 0;
+ WORD wBinCode;
+
+ memset(m_nBlockLength, 0, sizeof(m_nBlockLength));
+
+ for(m_ncDataBlock = i = 0; i < ncLength; ++i)
+ {
+ BYTE byMode;
+
+ if(IsNumeralData(lpsSource[i]))
+ byMode = QR_MODE_NUMERAL;
+ else if(IsAlphabetData(lpsSource[i]))
+ byMode = QR_MODE_ALPHABET;
+ else
+ byMode = QR_MODE_8BIT;
+
+ if(i == 0)
+ m_byBlockMode[0] = byMode;
+
+ if(m_byBlockMode[m_ncDataBlock] != byMode)
+ m_byBlockMode[++m_ncDataBlock] = byMode;
+
+ ++m_nBlockLength[m_ncDataBlock];
+ }
+
+ ++m_ncDataBlock;
+
+ while(nBlock < m_ncDataBlock - 1)
+ {
+ int ncJoinFront, ncJoinBehind;
+ int nJoinPosition = 0;
+
+ if((m_byBlockMode[nBlock] == QR_MODE_NUMERAL
+ && m_byBlockMode[nBlock + 1] == QR_MODE_ALPHABET) ||
+ (m_byBlockMode[nBlock] == QR_MODE_ALPHABET
+ && m_byBlockMode[nBlock + 1] == QR_MODE_NUMERAL))
+ {
+ ncSrcBits = GetBitLength(m_byBlockMode[nBlock], m_nBlockLength[nBlock], nVerGroup) +
+ GetBitLength(m_byBlockMode[nBlock + 1], m_nBlockLength[nBlock + 1], nVerGroup);
+
+ ncDstBits = GetBitLength(QR_MODE_ALPHABET,
+ m_nBlockLength[nBlock] + m_nBlockLength[nBlock + 1], nVerGroup);
+
+ if(ncSrcBits > ncDstBits)
+ {
+ if(nBlock >= 1 && m_byBlockMode[nBlock - 1] == QR_MODE_8BIT)
+ {
+ ncJoinFront = GetBitLength(QR_MODE_8BIT,
+ m_nBlockLength[nBlock - 1] + m_nBlockLength[nBlock], nVerGroup) +
+ GetBitLength(m_byBlockMode[nBlock + 1], m_nBlockLength[nBlock + 1], nVerGroup);
+
+ if(ncJoinFront > ncDstBits + GetBitLength(QR_MODE_8BIT, m_nBlockLength[nBlock - 1],
+ nVerGroup))
+ ncJoinFront = 0;
+ }
+ else
+ ncJoinFront = 0;
+
+ if(nBlock < m_ncDataBlock - 2 && m_byBlockMode[nBlock + 2] == QR_MODE_8BIT)
+ {
+ ncJoinBehind = GetBitLength(m_byBlockMode[nBlock], m_nBlockLength[nBlock], nVerGroup) +
+ GetBitLength(QR_MODE_8BIT, m_nBlockLength[nBlock + 1] + m_nBlockLength[nBlock + 2],
+ nVerGroup);
+
+ if(ncJoinBehind > ncDstBits + GetBitLength(QR_MODE_8BIT, m_nBlockLength[nBlock + 2],
+ nVerGroup))
+ ncJoinBehind = 0;
+ }
+ else
+ ncJoinBehind = 0;
+
+ if(ncJoinFront != 0 && ncJoinBehind != 0)
+ {
+ nJoinPosition = (ncJoinFront < ncJoinBehind) ? -1 : 1;
+ }
+ else
+ {
+ nJoinPosition = (ncJoinFront != 0) ? -1 : ((ncJoinBehind != 0) ? 1 : 0);
+ }
+
+ if(nJoinPosition != 0)
+ {
+ if(nJoinPosition == -1)
+ {
+ m_nBlockLength[nBlock - 1] += m_nBlockLength[nBlock];
+
+ for(i = nBlock; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+ }
+ else
+ {
+ m_byBlockMode[nBlock + 1] = QR_MODE_8BIT;
+ m_nBlockLength[nBlock + 1] += m_nBlockLength[nBlock + 2];
+
+ for(i = nBlock + 2; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+ }
+
+ --m_ncDataBlock;
+ }
+ else
+ {
+ if(nBlock < m_ncDataBlock - 2 && m_byBlockMode[nBlock + 2] == QR_MODE_ALPHABET)
+ {
+ m_nBlockLength[nBlock + 1] += m_nBlockLength[nBlock + 2];
+
+ for(i = nBlock + 2; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+
+ --m_ncDataBlock;
+ }
+
+ m_byBlockMode[nBlock] = QR_MODE_ALPHABET;
+ m_nBlockLength[nBlock] += m_nBlockLength[nBlock + 1];
+
+ for(i = nBlock + 1; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+
+ --m_ncDataBlock;
+
+ if(nBlock >= 1 && m_byBlockMode[nBlock - 1] == QR_MODE_ALPHABET)
+ {
+ m_nBlockLength[nBlock - 1] += m_nBlockLength[nBlock];
+
+ for(i = nBlock; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+
+ --m_ncDataBlock;
+ }
+ }
+
+ continue;
+ }
+ }
+
+ ++nBlock;
+ }
+
+ nBlock = 0;
+
+ while(nBlock < m_ncDataBlock - 1)
+ {
+ ncSrcBits = GetBitLength(m_byBlockMode[nBlock], m_nBlockLength[nBlock], nVerGroup)
+ + GetBitLength(m_byBlockMode[nBlock + 1], m_nBlockLength[nBlock + 1], nVerGroup);
+
+ ncDstBits = GetBitLength(QR_MODE_8BIT,
+ m_nBlockLength[nBlock] + m_nBlockLength[nBlock + 1], nVerGroup);
+
+ if(nBlock >= 1 && m_byBlockMode[nBlock - 1] == QR_MODE_8BIT)
+ ncDstBits -= (4 + nIndicatorLen8Bit[nVerGroup]);
+
+ if(nBlock < m_ncDataBlock - 2 && m_byBlockMode[nBlock + 2] == QR_MODE_8BIT)
+ ncDstBits -= (4 + nIndicatorLen8Bit[nVerGroup]);
+
+ if(ncSrcBits > ncDstBits)
+ {
+ if(nBlock >= 1 && m_byBlockMode[nBlock - 1] == QR_MODE_8BIT)
+ {
+ m_nBlockLength[nBlock - 1] += m_nBlockLength[nBlock];
+
+ for(i = nBlock; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+
+ --m_ncDataBlock;
+ --nBlock;
+ }
+
+ if(nBlock < m_ncDataBlock - 2 && m_byBlockMode[nBlock + 2] == QR_MODE_8BIT)
+ {
+ m_nBlockLength[nBlock + 1] += m_nBlockLength[nBlock + 2];
+
+ for(i = nBlock + 2; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+
+ --m_ncDataBlock;
+ }
+
+ m_byBlockMode[nBlock] = QR_MODE_8BIT;
+ m_nBlockLength[nBlock] += m_nBlockLength[nBlock + 1];
+
+ for(i = nBlock + 1; i < m_ncDataBlock - 1; ++i)
+ {
+ m_byBlockMode[i] = m_byBlockMode[i + 1];
+ m_nBlockLength[i] = m_nBlockLength[i + 1];
+ }
+
+ --m_ncDataBlock;
+
+ if(nBlock >= 1)
+ --nBlock;
+
+ continue;
+ }
+
+ ++nBlock;
+ }
+
+ m_ncDataCodeWordBit = 0;
+
+ memset(m_byDataCodeWord, 0, MAX_DATACODEWORD);
+
+ for(i = 0; i < m_ncDataBlock && m_ncDataCodeWordBit != -1; ++i)
+ {
+ if(m_byBlockMode[i] == QR_MODE_NUMERAL)
+ {
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, 1, 4);
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, (WORD)m_nBlockLength[i],
+ nIndicatorLenNumeral[nVerGroup]);
+
+ for(j = 0; j < m_nBlockLength[i]; j += 3)
+ {
+ if(j < m_nBlockLength[i] - 2)
+ {
+ wBinCode = (WORD)(((lpsSource[ncComplete + j] - '0') * 100) +
+ ((lpsSource[ncComplete + j + 1] - '0') * 10) +
+ (lpsSource[ncComplete + j + 2] - '0'));
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, wBinCode, 10);
+ }
+ else if(j == m_nBlockLength[i] - 2)
+ {
+ wBinCode = (WORD)(((lpsSource[ncComplete + j] - '0') * 10) +
+ (lpsSource[ncComplete + j + 1] - '0'));
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, wBinCode, 7);
+ }
+ else if(j == m_nBlockLength[i] - 1)
+ {
+ wBinCode = (WORD)(lpsSource[ncComplete + j] - '0');
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, wBinCode, 4);
+ }
+ }
+
+ ncComplete += m_nBlockLength[i];
+ }
+
+ else if(m_byBlockMode[i] == QR_MODE_ALPHABET)
+ {
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, 2, 4);
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, (WORD)m_nBlockLength[i],
+ nIndicatorLenAlphabet[nVerGroup]);
+
+ for(j = 0; j < m_nBlockLength[i]; j += 2)
+ {
+ if(j < m_nBlockLength[i] - 1)
+ {
+ wBinCode = (WORD)((AlphabetToBinaly(lpsSource[ncComplete + j]) * 45) +
+ AlphabetToBinaly(lpsSource[ncComplete + j + 1]));
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, wBinCode, 11);
+ }
+ else
+ {
+ wBinCode = (WORD)AlphabetToBinaly(lpsSource[ncComplete + j]);
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, wBinCode, 6);
+ }
+ }
+
+ ncComplete += m_nBlockLength[i];
+ }
+
+ else if(m_byBlockMode[i] == QR_MODE_8BIT)
+ {
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, 4, 4);
+
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, (WORD)m_nBlockLength[i],
+ nIndicatorLen8Bit[nVerGroup]);
+
+ for(j = 0; j < m_nBlockLength[i]; ++j)
+ {
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, (WORD)lpsSource[ncComplete + j],
+ 8);
+ }
+
+ ncComplete += m_nBlockLength[i];
+ }
+ }
+
+ return (bool)(m_ncDataCodeWordBit != -1);
+}
+
+static int GetEncodeVersion(int nVersion, char* lpsSource, int ncLength)
+{
+ int nVerGroup = nVersion >= 27 ? QR_VRESION_L : (nVersion >= 10 ? QR_VRESION_M :
+ QR_VRESION_S);
+ int i, j;
+
+ for(i = nVerGroup; i <= QR_VRESION_L; ++i)
+ {
+ if(EncodeSourceData(lpsSource, ncLength, i))
+ {
+ if(i == QR_VRESION_S)
+ {
+ for(j = 1; j <= 9; ++j)
+ {
+ if((m_ncDataCodeWordBit + 7) / 8 <= QR_VersonInfo[j].ncDataCodeWord[m_nLevel])
+ return j;
+ }
+ }
+ else if(i == QR_VRESION_M)
+ {
+ for(j = 10; j <= 26; ++j)
+ {
+ if((m_ncDataCodeWordBit + 7) / 8 <= QR_VersonInfo[j].ncDataCodeWord[m_nLevel])
+ return j;
+ }
+ }
+ else if(i == QR_VRESION_L)
+ {
+ for(j = 27; j <= 40; ++j)
+ {
+ if((m_ncDataCodeWordBit + 7) / 8 <= QR_VersonInfo[j].ncDataCodeWord[m_nLevel])
+ return j;
+ }
+ }
+ }
+ }
+ return 0;
+}
+
+static void SetFunctionModule(void)
+{
+ int i, j;
+
+ SetFinderPattern(0, 0);
+ SetFinderPattern(m_nSymbleSize - 7, 0);
+ SetFinderPattern(0, m_nSymbleSize - 7);
+
+ for(i = 0; i < 8; ++i)
+ {
+ m_byModuleData[i][7] = m_byModuleData[7][i] = '\x20';
+ m_byModuleData[m_nSymbleSize - 8][i] = m_byModuleData[m_nSymbleSize - 8 + i][7] = '\x20';
+ m_byModuleData[i][m_nSymbleSize - 8] = m_byModuleData[7][m_nSymbleSize - 8 + i] = '\x20';
+ }
+
+ for(i = 0; i < 9; ++i)
+ {
+ m_byModuleData[i][8] = m_byModuleData[8][i] = '\x20';
+ }
+
+ for(i = 0; i < 8; ++i)
+ {
+ m_byModuleData[m_nSymbleSize - 8 + i][8] = m_byModuleData[8][m_nSymbleSize - 8 + i] =
+ '\x20';
+ }
+
+ SetVersionPattern();
+
+ for(i = 0; i < QR_VersonInfo[m_nVersion].ncAlignPoint; ++i)
+ {
+ SetAlignmentPattern(QR_VersonInfo[m_nVersion].nAlignPoint[i], 6);
+ SetAlignmentPattern(6, QR_VersonInfo[m_nVersion].nAlignPoint[i]);
+
+ for(j = 0; j < QR_VersonInfo[m_nVersion].ncAlignPoint; ++j)
+ {
+ SetAlignmentPattern(QR_VersonInfo[m_nVersion].nAlignPoint[i],
+ QR_VersonInfo[m_nVersion].nAlignPoint[j]);
+ }
+ }
+
+ for(i = 8; i <= m_nSymbleSize - 9; ++i)
+ {
+ m_byModuleData[i][6] = (i % 2) == 0 ? '\x30' : '\x20';
+ m_byModuleData[6][i] = (i % 2) == 0 ? '\x30' : '\x20';
+ }
+}
+
+static void FormatModule(void)
+{
+ int i, j;
+ int nMinPenalty, nPenalty;
+
+ memset(m_byModuleData, 0, sizeof(m_byModuleData));
+
+ SetFunctionModule();
+
+ SetCodeWordPattern();
+
+ if(m_nMaskingNo == -1)
+ {
+ m_nMaskingNo = 0;
+
+ SetMaskingPattern(m_nMaskingNo);
+ SetFormatInfoPattern(m_nMaskingNo);
+
+ nMinPenalty = CountPenalty();
+
+ for(i = 1; i <= 7; ++i)
+ {
+ SetMaskingPattern(i);
+ SetFormatInfoPattern(i);
+
+ nPenalty = CountPenalty();
+
+ if(nPenalty < nMinPenalty)
+ {
+ nMinPenalty = nPenalty;
+ m_nMaskingNo = i;
+ }
+ }
+ }
+
+ SetMaskingPattern(m_nMaskingNo);
+ SetFormatInfoPattern(m_nMaskingNo);
+
+ for(i = 0; i < m_nSymbleSize; ++i)
+ {
+ for(j = 0; j < m_nSymbleSize; ++j)
+ {
+ m_byModuleData[i][j] = (BYTE)((m_byModuleData[i][j] & 0x11) != 0);
+ }
+ }
+}
+
+int QRencode(char* lpsSource, char* qr)
+{
+ int i, j, nVersion=2, bAutoExtent=1;
+ int ncLength, nEncodeVersion, ncDataCodeWord, ncTerminater;
+ BYTE byPaddingCode = 0xec;
+ int nDataCwIndex = 0, ncBlock1, ncBlock2, ncBlockSum;
+ int nBlockNo = 0, ncDataCw1, ncDataCw2;
+ int ncRSCw1, ncRSCw2;
+
+ m_nLevel = QR_LEVEL_M;
+ m_nMaskingNo = 0;
+
+ ncLength = strlen(lpsSource);
+ if(ncLength == 0)
+ return -1;
+
+ nEncodeVersion = GetEncodeVersion(nVersion, lpsSource, ncLength);
+ if(nEncodeVersion == 0)
+ return -1;
+
+ if(nVersion == 0)
+ {
+ m_nVersion = nEncodeVersion;
+ }
+ else
+ {
+ if(nEncodeVersion <= nVersion)
+ {
+ m_nVersion = nVersion;
+ }
+ else
+ {
+ if(bAutoExtent)
+ m_nVersion = nEncodeVersion;
+ else
+ return -1;
+ }
+ }
+
+ ncDataCodeWord = QR_VersonInfo[m_nVersion].ncDataCodeWord[m_nLevel];
+
+ ncTerminater = min(4, (ncDataCodeWord * 8) - m_ncDataCodeWordBit);
+
+ if(ncTerminater > 0)
+ m_ncDataCodeWordBit = SetBitStream(m_ncDataCodeWordBit, 0, ncTerminater);
+
+ for(i = (m_ncDataCodeWordBit + 7) / 8; i < ncDataCodeWord; ++i)
+ {
+ m_byDataCodeWord[i] = byPaddingCode;
+
+ byPaddingCode = (BYTE)(byPaddingCode == 0xec ? 0x11 : 0xec);
+ }
+
+ m_ncAllCodeWord = QR_VersonInfo[m_nVersion].ncAllCodeWord;
+ memset(m_byAllCodeWord, 0, m_ncAllCodeWord);
+
+ ncBlock1 = QR_VersonInfo[m_nVersion].RS_BlockInfo1[m_nLevel].ncRSBlock;
+ ncBlock2 = QR_VersonInfo[m_nVersion].RS_BlockInfo2[m_nLevel].ncRSBlock;
+ ncBlockSum = ncBlock1 + ncBlock2;
+
+ ncDataCw1 = QR_VersonInfo[m_nVersion].RS_BlockInfo1[m_nLevel].ncDataCodeWord;
+ ncDataCw2 = QR_VersonInfo[m_nVersion].RS_BlockInfo2[m_nLevel].ncDataCodeWord;
+
+ for(i = 0; i < ncBlock1; ++i)
+ {
+ for(j = 0; j < ncDataCw1; ++j)
+ {
+ m_byAllCodeWord[(ncBlockSum * j) + nBlockNo] = m_byDataCodeWord[nDataCwIndex++];
+ }
+
+ ++nBlockNo;
+ }
+
+ for(i = 0; i < ncBlock2; ++i)
+ {
+ for(j = 0; j < ncDataCw2; ++j)
+ {
+ if(j < ncDataCw1)
+ {
+ m_byAllCodeWord[(ncBlockSum * j) + nBlockNo] = m_byDataCodeWord[nDataCwIndex++];
+ }
+ else
+ {
+ m_byAllCodeWord[(ncBlockSum * ncDataCw1) + i] = m_byDataCodeWord[nDataCwIndex++];
+ }
+ }
+
+ ++nBlockNo;
+ }
+
+ ncRSCw1 = QR_VersonInfo[m_nVersion].RS_BlockInfo1[m_nLevel].ncAllCodeWord - ncDataCw1;
+ ncRSCw2 = QR_VersonInfo[m_nVersion].RS_BlockInfo2[m_nLevel].ncAllCodeWord - ncDataCw2;
+
+ nDataCwIndex = 0;
+ nBlockNo = 0;
+
+ for(i = 0; i < ncBlock1; ++i)
+ {
+ memset(m_byRSWork, 0, sizeof(m_byRSWork));
+
+ memmove(m_byRSWork, m_byDataCodeWord + nDataCwIndex, ncDataCw1);
+
+ GetRSCodeWord(m_byRSWork, ncDataCw1, ncRSCw1);
+
+ for(j = 0; j < ncRSCw1; ++j)
+ {
+ m_byAllCodeWord[ncDataCodeWord + (ncBlockSum * j) + nBlockNo] = m_byRSWork[j];
+ }
+
+ nDataCwIndex += ncDataCw1;
+ ++nBlockNo;
+ }
+
+ for(i = 0; i < ncBlock2; ++i)
+ {
+ memset(m_byRSWork, 0, sizeof(m_byRSWork));
+
+ memmove(m_byRSWork, m_byDataCodeWord + nDataCwIndex, ncDataCw2);
+
+ GetRSCodeWord(m_byRSWork, ncDataCw2, ncRSCw2);
+
+ for(j = 0; j < ncRSCw2; ++j)
+ {
+ m_byAllCodeWord[ncDataCodeWord + (ncBlockSum * j) + nBlockNo] = m_byRSWork[j];
+ }
+
+ nDataCwIndex += ncDataCw2;
+ ++nBlockNo;
+ }
+
+ m_nSymbleSize = m_nVersion * 4 + 17;
+
+ FormatModule();
+
+ //64x64
+ // for (i = 0; i < MAX_MODULESIZE; i++) {
+ // for (j = 0; j < MAX_MODULESIZE; j++) {
+ // n_byModuleData[i*2][j*2] = m_byModuleData[i][j];
+ // n_byModuleData[i*2][j*2+1] = m_byModuleData[i][j];
+ // }
+ // memcpy(n_byModuleData[i*2+1], n_byModuleData[i*2], MAX_MODULESIZE*2);
+ // }
+ // for (i = 0; i < MAX_MODULESIZE2; i++) {
+ // for (j = 0; j < (MAX_MODULESIZE2/8); j++) {
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] = n_byModuleData[i][j*8 + 0] << 7;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 1] << 6;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 2] << 5;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 3] << 4;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 4] << 3;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 5] << 2;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 6] << 1;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 7];
+ // }
+ // if (j == MAX_MODULESIZE2/8) {
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] = n_byModuleData[i][j*8 + 0] << 7;
+ // qr[i * (MAX_MODULESIZE2/8 + 1) + j] |= n_byModuleData[i][j*8 + 1] << 6;
+ // }
+ // }
+
+ //48x48
+ // for (i = 0; i < MAX_MODULESIZE; i++) {
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1)] = m_byModuleData[i][0];
+ // for (j = 1; j < ((MAX_MODULESIZE-1)/8 + 1); j++) {
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] = m_byModuleData[i][(j-1)*8 + 1] << 7;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 2] << 6;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 3] << 5;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 4] << 4;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 5] << 3;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 6] << 2;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 7] << 1;
+ // qr[i * ((MAX_MODULESIZE-1)/8 + 1) + j] |= m_byModuleData[i][(j-1)*8 + 8];
+ // }
+ // }
+ // for (i = 0; i < 7; i++) {
+ // for (j = 0; j < (MAX_MODULESIZE-1)/8 + 1; j++) {
+ // qr[MAX_MODULESIZE * 6 + i + j] = 0;
+ // }
+ // }
+
+ //32x32
+ // for (i = 0; i < MAX_MODULESIZE; i++) {
+ // for (j = 0; j < (MAX_MODULESIZE/8); j++) {
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] = m_byModuleData[i][j*8 + 0] << 7;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 1] << 6;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 2] << 5;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 3] << 4;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 4] << 3;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 5] << 2;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 6] << 1;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 7];
+ // }
+ // if (j == MAX_MODULESIZE/8) {
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] = m_byModuleData[i][j*8 + 0] << 7;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 1] << 6;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 2] << 5;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 3] << 4;
+ // qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 4] << 3;
+ // }
+ // }
+ //40x40
+ if(qr)
+ {
+ for(i = 0; i < MAX_MODULESIZE; i++)
+ {
+ for(j = 0; j < (MAX_MODULESIZE/8); j++)
+ {
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] = m_byModuleData[i][j*8 + 0] << 7;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 1] << 6;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 2] << 5;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 3] << 4;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 4] << 3;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 5] << 2;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 6] << 1;
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] |= m_byModuleData[i][j*8 + 7];
+ }
+ if(j == MAX_MODULESIZE/8)
+ {
+ qr[i * (MAX_MODULESIZE/8 + 1) + j] = m_byModuleData[i][j*8 + 0] << 7;
+ }
+ }
+ }
+ return 1;
+}
+
diff --git a/libqr/qrencode.h b/libqr/qrencode.h
new file mode 100644
index 0000000..a3a1130
--- /dev/null
+++ b/libqr/qrencode.h
@@ -0,0 +1,48 @@
+#ifndef QRENCODE_H
+#define QRENCODE_H
+
+#define MAX_MODULESIZE 25 //41 //50 // 21:Version=1,×î´ó×Ö·û=17(8.5¸öºº×Ö)
+ // 25:Version=2,×î´ó×Ö·û=32(16¸öºº×Ö)
+ // 29:Version=3,×î´ó×Ö·û=53(26.5¸öºº×Ö)
+ // 33:Version=4,×î´ó×Ö·û=78(39¸öºº×Ö)
+ // 37:Version=5,×î´ó×Ö·û=106(53¸öºº×Ö)
+ // 41:Version=6,×î´ó×Ö·û=134(67¸öºº×Ö) the one
+ // 45:Version=7,×î´ó×Ö·û=154(77¸öºº×Ö)
+ // 49:Version=8,×î´ó×Ö·û=192(96¸öºº×Ö)
+ // 53: 9
+ // 57: 10
+ // 61: 11
+// #define QR_MARGIN 4
+
+int QRencode(char *lpsSource, char *qr);
+
+//int GetEncodeVersion(int nVersion, char *lpsSource, int ncLength);
+//bool EncodeSourceData(char *lpsSource, int ncLength, int nVerGroup);
+
+//int GetBitLength(BYTE nMode, int ncData, int nVerGroup);
+
+//int SetBitStream(int nIndex, WORD wData, int ncData);
+
+//bool IsNumeralData(unsigned char c);
+//bool IsAlphabetData(unsigned char c);
+
+//BYTE AlphabetToBinaly(unsigned char c);
+
+//void GetRSCodeWord(BYTE *lpbyRSWork, int ncDataCodeWord, int ncRSCodeWord);
+
+//void FormatModule(void);
+
+//void SetFunctionModule(void);
+//void SetFinderPattern(int x, int y);
+//void SetAlignmentPattern(int x, int y);
+//void SetVersionPattern(void);
+//void SetCodeWordPattern(void);
+//void SetMaskingPattern(int nPatternNo);
+//void SetFormatInfoPattern(int nPatternNo);
+//int CountPenalty(void);
+
+extern int m_nSymbleSize;
+extern unsigned char m_byModuleData[MAX_MODULESIZE][MAX_MODULESIZE];
+
+#endif
+
diff --git a/msgpack/cwpack.c b/msgpack/cwpack.c
new file mode 100644
index 0000000..496b4b3
--- /dev/null
+++ b/msgpack/cwpack.c
@@ -0,0 +1,672 @@
+/* CWPack - cwpack.c */
+/*
+ The MIT License (MIT)
+
+ Copyright (c) 2017 Claes Wihlborg
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of this
+ software and associated documentation files (the "Software"), to deal in the Software
+ without restriction, including without limitation the rights to use, copy, modify,
+ merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+ persons to whom the Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all copies or
+ substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <string.h>
+
+#include "cwpack.h"
+#include "cwpack_defines.h"
+
+
+
+/************************* C S Y S T E M L I B R A R Y ****************/
+
+#ifdef FORCE_NO_LIBRARY
+
+static void *memcpy(void *dst, const void *src, size_t n)
+{
+ unsigned int i;
+ uint8_t *d=(uint8_t*)dst, *s=(uint8_t*)src;
+ for (i=0; i<n; i++)
+ {
+ *d++ = *s++;
+ }
+ return dst;
+}
+
+#endif
+
+
+
+/************************* B Y T E O R D E R ****************************/
+
+
+static int test_byte_order(void)
+{
+#ifdef COMPILE_FOR_BIG_ENDIAN
+ const char *endianness = "1234";
+ if (*(uint32_t*)endianness != 0x31323334UL)
+ return CWP_RC_WRONG_BYTE_ORDER;
+#else
+
+#ifdef COMPILE_FOR_LITTLE_ENDIAN
+ const char *endianness = "1234";
+ if (*(uint32_t*)endianness != 0x34333231UL)
+ return CWP_RC_WRONG_BYTE_ORDER;
+#endif
+#endif
+ return CWP_RC_OK;
+}
+
+
+/******************************* P A C K **********************************/
+
+
+
+int cw_pack_context_init (cw_pack_context* pack_context, void* data, unsigned long length, pack_overflow_handler hpo)
+{
+ pack_context->start = pack_context->current = (uint8_t*)data;
+ pack_context->end = pack_context->start + length;
+ pack_context->be_compatible = false;
+ pack_context->err_no = 0;
+ pack_context->handle_pack_overflow = hpo;
+ pack_context->return_code = test_byte_order();
+ return pack_context->return_code;
+}
+
+void cw_pack_set_compatibility (cw_pack_context* pack_context, bool be_compatible)
+{
+ pack_context->be_compatible = be_compatible;
+}
+
+
+
+/* Packing routines -------------------------------------------------------------------------------- */
+
+
+void cw_pack_unsigned(cw_pack_context* pack_context, uint64_t i)
+{
+ if (pack_context->return_code)
+ return;
+
+ if (i < 128)
+ tryMove0(i);
+
+ if (i < 256)
+ tryMove1(0xcc, i);
+
+ if (i < 0x10000L)
+ {
+ tryMove2(0xcd, i);
+ }
+ if (i < 0x100000000LL)
+ tryMove4(0xce, i);
+
+ tryMove8(0xcf,i);
+}
+
+
+void cw_pack_signed(cw_pack_context* pack_context, int64_t i)
+{
+ if (pack_context->return_code)
+ return;
+
+ if (i >127)
+ {
+ if (i < 256)
+ tryMove1(0xcc, i);
+
+ if (i < 0x10000L)
+ tryMove2(0xcd, i);
+
+ if (i < 0x100000000LL)
+ tryMove4(0xce, i);
+
+ tryMove8(0xcf,i);
+ }
+
+ if (i >= -32)
+ tryMove0(i);
+
+ if (i >= -128)
+ tryMove1(0xd0, i);
+
+ if (i >= -32768)
+ tryMove2(0xd1,i);
+
+ if (i >= (int64_t)0xffffffff80000000LL)
+ tryMove4(0xd2,i);
+
+ tryMove8(0xd3,i);
+}
+
+
+void cw_pack_float(cw_pack_context* pack_context, float f)
+{
+ if (pack_context->return_code)
+ return;
+
+ uint32_t tmp = *((uint32_t*)&f);
+ tryMove4(0xca,tmp);
+}
+
+
+void cw_pack_double(cw_pack_context* pack_context, double d)
+{
+ if (pack_context->return_code)
+ return;
+
+ uint64_t tmp = *((uint64_t*)&d);
+ tryMove8(0xcb,tmp);
+}
+
+
+void cw_pack_real (cw_pack_context* pack_context, double d)
+{
+ float f = (float)d;
+ double df = f;
+ if (df == d)
+ cw_pack_float (pack_context, f);
+ else
+ cw_pack_double (pack_context, d);
+}
+
+
+void cw_pack_nil(cw_pack_context* pack_context)
+{
+ if (pack_context->return_code)
+ return;
+
+ tryMove0(0xc0);
+}
+
+
+void cw_pack_true (cw_pack_context* pack_context)
+{
+ if (pack_context->return_code)
+ return;
+
+ tryMove0(0xc3);
+}
+
+
+void cw_pack_false (cw_pack_context* pack_context)
+{
+ if (pack_context->return_code)
+ return;
+
+ tryMove0(0xc2);
+}
+
+
+void cw_pack_boolean(cw_pack_context* pack_context, bool b)
+{
+ if (pack_context->return_code)
+ return;
+
+ tryMove0(b? 0xc3: 0xc2);
+}
+
+
+void cw_pack_array_size(cw_pack_context* pack_context, uint32_t n)
+{
+ if (pack_context->return_code)
+ return;
+
+ if (n < 16)
+ tryMove0(0x90 | n);
+
+ if (n < 65536)
+ tryMove2(0xdc, n);
+
+ tryMove4(0xdd, n);
+}
+
+
+void cw_pack_map_size(cw_pack_context* pack_context, uint32_t n)
+{
+ if (pack_context->return_code)
+ return;
+
+ if (n < 16)
+ tryMove0(0x80 | n);
+
+ if (n < 65536)
+ tryMove2(0xde, n);
+
+ tryMove4(0xdf, n);
+}
+
+
+void cw_pack_str(cw_pack_context* pack_context, const char* v, uint32_t l)
+{
+ if (pack_context->return_code)
+ return;
+
+ uint8_t *p;
+
+ if (l < 32) // Fixstr
+ {
+ cw_pack_reserve_space(l+1);
+ *p = (uint8_t)(0xa0 + l);
+ memcpy(p+1,v,l);
+ return;
+ }
+ if (l < 256 && !pack_context->be_compatible) // Str 8
+ {
+ cw_pack_reserve_space(l+2);
+ *p++ = (uint8_t)(0xd9);
+ *p = (uint8_t)(l);
+ memcpy(p+1,v,l);
+ return;
+ }
+ if (l < 65536) // Str 16
+ {
+ cw_pack_reserve_space(l+3)
+ *p++ = (uint8_t)0xda;
+ cw_store16(l);
+ memcpy(p+2,v,l);
+ return;
+ }
+ // Str 32
+ cw_pack_reserve_space(l+5)
+ *p++ = (uint8_t)0xdb;
+ cw_store32(l);
+ memcpy(p+4,v,l);
+ return;
+}
+
+
+void cw_pack_bin(cw_pack_context* pack_context, const void* v, uint32_t l)
+{
+ if (pack_context->return_code)
+ return;
+
+ if (pack_context->be_compatible)
+ {
+ cw_pack_str( pack_context, v, l);
+ return;
+ }
+
+ uint8_t *p;
+
+ if (l < 256) // Bin 8
+ {
+ cw_pack_reserve_space(l+2);
+ *p++ = (uint8_t)(0xc4);
+ *p = (uint8_t)(l);
+ memcpy(p+1,v,l);
+ return;
+ }
+ if (l < 65536) // Bin 16
+ {
+ cw_pack_reserve_space(l+3)
+ *p++ = (uint8_t)0xc5;
+ cw_store16(l);
+ memcpy(p+2,v,l);
+ return;
+ }
+ // Bin 32
+ cw_pack_reserve_space(l+5)
+ *p++ = (uint8_t)0xc6;
+ cw_store32(l);
+ memcpy(p+4,v,l);
+ return;
+}
+
+
+void cw_pack_ext (cw_pack_context* pack_context, int8_t type, const void* v, uint32_t l)
+{
+ if (pack_context->return_code)
+ return;
+
+ if (pack_context->be_compatible)
+ PACK_ERROR(CWP_RC_ILLEGAL_CALL);
+
+ uint8_t *p;
+
+ switch (l)
+ {
+ case 1: // Fixext 1
+ cw_pack_reserve_space(3);
+ *p++ = (uint8_t)0xd4;
+ *p++ = (uint8_t)type;
+ *p++ = *(uint8_t*)v;
+ return;
+ case 2: // Fixext 2
+ cw_pack_reserve_space(4);
+ *p++ = (uint8_t)0xd5;
+ break;
+ case 4: // Fixext 4
+ cw_pack_reserve_space(6);
+ *p++ = (uint8_t)0xd6;
+ break;
+ case 8: // Fixext 8
+ cw_pack_reserve_space(10);
+ *p++ = (uint8_t)0xd7;
+ break;
+ case 16: // Fixext16
+ cw_pack_reserve_space(18);
+ *p++ = (uint8_t)0xd8;
+ break;
+ default:
+ if (l < 256) // Ext 8
+ {
+ cw_pack_reserve_space(l+3);
+ *p++ = (uint8_t)0xc7;
+ *p++ = (uint8_t)(l);
+ }
+ else if (l < 65536) // Ext 16
+ {
+ cw_pack_reserve_space(l+4)
+ *p++ = (uint8_t)0xc8;
+ cw_store16(l);
+ p += 2;
+ }
+ else // Ext 32
+ {
+ cw_pack_reserve_space(l+6)
+ *p++ = (uint8_t)0xc9;
+ cw_store32(l);
+ p += 4;
+ }
+ }
+ *p++ = (uint8_t)type;
+ memcpy(p,v,l);
+}
+
+
+void cw_pack_insert (cw_pack_context* pack_context, const void* v, uint32_t l)
+{
+ uint8_t *p;
+ cw_pack_reserve_space(l);
+ memcpy(p,v,l);
+}
+
+/******************************* U N P A C K **********************************/
+
+
+int cw_unpack_context_init (cw_unpack_context* unpack_context, void* data, unsigned long length, unpack_underflow_handler huu)
+{
+ unpack_context->start = unpack_context->current = (uint8_t*)data;
+ unpack_context->end = unpack_context->start + length;
+ unpack_context->return_code = test_byte_order();
+ unpack_context->err_no = 0;
+ unpack_context->handle_unpack_underflow = huu;
+ return unpack_context->return_code;
+}
+
+
+/* Unpacking routines ---------------------------------------------------------- */
+
+
+
+void cw_unpack_next (cw_unpack_context* unpack_context)
+{
+ if (unpack_context->return_code)
+ return;
+
+ uint64_t tmpu64;
+ uint32_t tmpu32;
+ uint16_t tmpu16;
+ uint8_t* p;
+
+#define buffer_end_return_code CWP_RC_END_OF_INPUT;
+ cw_unpack_assert_space(1);
+ uint8_t c = *p;
+#undef buffer_end_return_code
+#define buffer_end_return_code CWP_RC_BUFFER_UNDERFLOW;
+ switch (c)
+ {
+ case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+ case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+ case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+ case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+ case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+ case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+ case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+ case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+ case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+ case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+ case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+ case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+ case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+ case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+ case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+ case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+ getDDItem(CWP_ITEM_POSITIVE_INTEGER, i64, c); return; // positive fixnum
+ case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+ case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+ getDDItem(CWP_ITEM_MAP, map.size, c & 0x0f); return; // fixmap
+ case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+ case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+ getDDItem(CWP_ITEM_ARRAY, array.size, c & 0x0f); return; // fixarray
+ case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+ case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+ case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+ case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+ getDDItem(CWP_ITEM_STR, str.length, c & 0x1f); // fixraw
+ cw_unpack_assert_blob(str);
+ case 0xc0: unpack_context->item.type = CWP_ITEM_NIL; return; // nil
+ case 0xc2: getDDItem(CWP_ITEM_BOOLEAN, boolean, false); return; // false
+ case 0xc3: getDDItem(CWP_ITEM_BOOLEAN, boolean, true); return; // true
+ case 0xc4: getDDItem1(CWP_ITEM_BIN, bin.length, uint8_t); // bin 8
+ cw_unpack_assert_blob(bin);
+ case 0xc5: getDDItem2(CWP_ITEM_BIN, bin.length, uint16_t); // bin 16
+ cw_unpack_assert_blob(bin);
+ case 0xc6: getDDItem4(CWP_ITEM_BIN, bin.length, uint32_t); // bin 32
+ cw_unpack_assert_blob(bin);
+ case 0xc7: getDDItem1(CWP_ITEM_EXT, ext.length, uint8_t); // ext 8
+ cw_unpack_assert_space(1);
+ unpack_context->item.type = *(int8_t*)p;
+ cw_unpack_assert_blob(ext);
+ case 0xc8: getDDItem2(CWP_ITEM_EXT, ext.length, uint16_t); // ext 16
+ cw_unpack_assert_space(1);
+ unpack_context->item.type = *(int8_t*)p;
+ cw_unpack_assert_blob(ext);
+ case 0xc9: getDDItem4(CWP_ITEM_EXT, ext.length, uint32_t); // ext 32
+ cw_unpack_assert_space(1);
+ unpack_context->item.type = *(int8_t*)p;
+ cw_unpack_assert_blob(ext);
+ case 0xca: unpack_context->item.type = CWP_ITEM_FLOAT; // float
+ cw_unpack_assert_space(4);
+ cw_load32(p);
+ unpack_context->item.as.real = *(float*)&tmpu32; return;
+ case 0xcb: getDDItem8(CWP_ITEM_DOUBLE); return; // double
+ case 0xcc: getDDItem1(CWP_ITEM_POSITIVE_INTEGER, u64, uint8_t); return; // unsigned int 8
+ case 0xcd: getDDItem2(CWP_ITEM_POSITIVE_INTEGER, u64, uint16_t); return; // unsigned int 16
+ case 0xce: getDDItem4(CWP_ITEM_POSITIVE_INTEGER, u64, uint32_t); return; // unsigned int 32
+ case 0xcf: getDDItem8(CWP_ITEM_POSITIVE_INTEGER); return; // unsigned int 64
+ case 0xd0: getDDItem1(CWP_ITEM_NEGATIVE_INTEGER, i64, int8_t); // signed int 8
+ if (unpack_context->item.as.i64 >= 0)
+ unpack_context->item.type = CWP_ITEM_POSITIVE_INTEGER;
+ return;
+ case 0xd1: getDDItem2(CWP_ITEM_NEGATIVE_INTEGER, i64, int16_t); // signed int 16
+ if (unpack_context->item.as.i64 >= 0)
+ unpack_context->item.type = CWP_ITEM_POSITIVE_INTEGER;
+ return;
+ case 0xd2: getDDItem4(CWP_ITEM_NEGATIVE_INTEGER, i64, int32_t); // signed int 32
+ if (unpack_context->item.as.i64 >= 0)
+ unpack_context->item.type = CWP_ITEM_POSITIVE_INTEGER;
+ return;
+ case 0xd3: getDDItem8(CWP_ITEM_NEGATIVE_INTEGER); // signed int 64
+ if (unpack_context->item.as.i64 >= 0)
+ unpack_context->item.type = CWP_ITEM_POSITIVE_INTEGER;
+ return;
+ case 0xd4: getDDItemFix(1); // fixext 1
+ case 0xd5: getDDItemFix(2); // fixext 2
+ case 0xd6: getDDItemFix(4); // fixext 4
+ case 0xd7: getDDItemFix(8); // fixext 8
+ case 0xd8: getDDItemFix(16); // fixext 16
+ case 0xd9: getDDItem1(CWP_ITEM_STR, str.length, uint8_t); // str 8
+ cw_unpack_assert_blob(str);
+ case 0xda: getDDItem2(CWP_ITEM_STR, str.length, uint16_t); // str 16
+ cw_unpack_assert_blob(str);
+ case 0xdb: getDDItem4(CWP_ITEM_STR, str.length, uint32_t); // str 32
+ cw_unpack_assert_blob(str);
+ case 0xdc: getDDItem2(CWP_ITEM_ARRAY, array.size, uint16_t); return; // array 16
+ case 0xdd: getDDItem4(CWP_ITEM_ARRAY, array.size, uint32_t); return; // array 32
+ case 0xde: getDDItem2(CWP_ITEM_MAP, map.size, uint16_t); return; // map 16
+ case 0xdf: getDDItem4(CWP_ITEM_MAP, map.size, uint32_t); return; // map 32
+ case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
+ case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
+ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
+ case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
+ getDDItem(CWP_ITEM_NEGATIVE_INTEGER, i64, (int8_t)c); return; // negative fixnum
+ default:
+ UNPACK_ERROR(CWP_RC_MALFORMED_INPUT)
+ }
+}
+
+#define cw_skip_bytes(n) \
+ cw_unpack_assert_space((n)); \
+ break;
+
+void cw_skip_items (cw_unpack_context* unpack_context, long item_count)
+{
+ if (unpack_context->return_code)
+ return;
+
+ uint32_t tmpu32;
+ uint16_t tmpu16;
+ uint8_t* p;
+
+ while (item_count-- > 0)
+ {
+#undef buffer_end_return_code
+#define buffer_end_return_code CWP_RC_END_OF_INPUT;
+ cw_unpack_assert_space(1);
+ uint8_t c = *p;
+
+#undef buffer_end_return_code
+#define buffer_end_return_code CWP_RC_BUFFER_UNDERFLOW;
+ switch (c)
+ {
+ case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+ case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+ case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+ case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+ case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+ case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+ case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+ case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+ case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+ case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+ case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+ case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+ case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+ case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+ case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+ case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+ // unsigned fixint
+ case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
+ case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
+ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
+ case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
+ // signed fixint
+ case 0xc0: // nil
+ case 0xc2: // false
+ case 0xc3: break; // true
+ case 0xcc: // unsigned int 8
+ case 0xd0: cw_skip_bytes(1); // signed int 8
+ case 0xcd: // unsigned int 16
+ case 0xd1: // signed int 16
+ case 0xd4: cw_skip_bytes(2); // fixext 1
+ case 0xd5: cw_skip_bytes(3); // fixext 2
+ case 0xca: // float
+ case 0xce: // unsigned int 32
+ case 0xd2: cw_skip_bytes(4); // signed int 32
+ case 0xd6: cw_skip_bytes(5); // fixext 4
+ case 0xcb: // double
+ case 0xcf: // unsigned int 64
+ case 0xd3: cw_skip_bytes(8); // signed int 64
+ case 0xd7: cw_skip_bytes(9); // fixext 8
+ case 0xd8: cw_skip_bytes(17); // fixext 16
+ case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+ case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+ case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+ case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+ cw_skip_bytes(c & 0x1f); // fixstr
+ case 0xd9: // str 8
+ case 0xc4: // bin 8
+ cw_unpack_assert_space(1);
+ tmpu32 = *p;
+ cw_skip_bytes(tmpu32);
+
+ case 0xda: // str 16
+ case 0xc5: // bin 16
+ cw_unpack_assert_space(2);
+ cw_load16(p);
+ cw_skip_bytes(tmpu16);
+
+ case 0xdb: // str 32
+ case 0xc6: // bin 32
+ cw_unpack_assert_space(4);
+ cw_load32(p);
+ cw_skip_bytes(tmpu32);
+
+ case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+ case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+ item_count += 2*(c & 15); // FixMap
+ break;
+
+ case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+ case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+ item_count += c & 15; // FixArray
+ break;
+
+ case 0xdc: // array 16
+ cw_unpack_assert_space(2);
+ cw_load16(p);
+ item_count += tmpu16;
+ break;
+
+ case 0xde: // map 16
+ cw_unpack_assert_space(2);
+ cw_load16(p);
+ item_count += 2*tmpu16;
+ break;
+
+ case 0xdd: // array 32
+ cw_unpack_assert_space(4);
+ cw_load32(p);
+ item_count += tmpu32;
+ break;
+
+ case 0xdf: // map 32
+ cw_unpack_assert_space(4);
+ cw_load32(p);
+ item_count += 2*tmpu32;
+ break;
+
+ case 0xc7: // ext 8
+ cw_unpack_assert_space(1);
+ tmpu32 = *p;
+ cw_skip_bytes(tmpu32 +1);
+
+ case 0xc8: // ext 16
+ cw_unpack_assert_space(2);
+ cw_load16(p);
+ cw_skip_bytes(tmpu16 +1);
+
+ case 0xc9: // ext 32
+ cw_unpack_assert_space(4);
+ cw_load32(p);
+ cw_skip_bytes(tmpu32 +1);
+
+ default: // illegal
+ UNPACK_ERROR(CWP_RC_MALFORMED_INPUT)
+ }
+ }
+ return;
+}
+
+/* end cwpack.c */
diff --git a/msgpack/cwpack.h b/msgpack/cwpack.h
new file mode 100644
index 0000000..c297d56
--- /dev/null
+++ b/msgpack/cwpack.h
@@ -0,0 +1,166 @@
+/* CWPack - cwpack.h */
+/*
+ The MIT License (MIT)
+
+ Copyright (c) 2017 Claes Wihlborg
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of this
+ software and associated documentation files (the "Software"), to deal in the Software
+ without restriction, including without limitation the rights to use, copy, modify,
+ merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+ persons to whom the Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all copies or
+ substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef CWPack_H__
+#define CWPack_H__
+
+
+//#include <stdint.h>
+#include <stdbool.h>
+
+//zzq add
+#include "stdint.h"
+
+
+
+/******************************* Return Codes *****************************/
+
+#define CWP_RC_OK 0
+#define CWP_RC_END_OF_INPUT -1
+#define CWP_RC_BUFFER_OVERFLOW -2
+#define CWP_RC_BUFFER_UNDERFLOW -3
+#define CWP_RC_MALFORMED_INPUT -4
+#define CWP_RC_WRONG_BYTE_ORDER -5
+#define CWP_RC_ERROR_IN_HANDLER -6
+#define CWP_RC_ILLEGAL_CALL -7
+#define CWP_RC_MALLOC_ERROR -8
+#define CWP_RC_STOPPED -9
+
+
+
+/******************************* P A C K **********************************/
+
+
+struct cw_pack_context;
+
+typedef int (*pack_overflow_handler)(struct cw_pack_context*, unsigned long);
+
+typedef struct cw_pack_context {
+ uint8_t* start;
+ uint8_t* current;
+ uint8_t* end;
+ bool be_compatible;
+ int return_code;
+ int err_no; /* handlers can save error here */
+ pack_overflow_handler handle_pack_overflow;
+} cw_pack_context;
+
+
+int cw_pack_context_init (cw_pack_context* pack_context, void* data, unsigned long length, pack_overflow_handler hpo);
+void cw_pack_set_compatibility (cw_pack_context* pack_context, bool be_compatible);
+
+void cw_pack_nil (cw_pack_context* pack_context);
+void cw_pack_true (cw_pack_context* pack_context);
+void cw_pack_false (cw_pack_context* pack_context);
+void cw_pack_boolean (cw_pack_context* pack_context, bool b);
+
+void cw_pack_signed (cw_pack_context* pack_context, int64_t i);
+void cw_pack_unsigned (cw_pack_context* pack_context, uint64_t i);
+
+void cw_pack_float (cw_pack_context* pack_context, float f);
+void cw_pack_double (cw_pack_context* pack_context, double d);
+void cw_pack_real (cw_pack_context* pack_context, double d); /* Pack as float if precision isn't destroyed */
+
+void cw_pack_array_size (cw_pack_context* pack_context, uint32_t n);
+void cw_pack_map_size (cw_pack_context* pack_context, uint32_t n);
+void cw_pack_str (cw_pack_context* pack_context, const char* v, uint32_t l);
+void cw_pack_bin (cw_pack_context* pack_context, const void* v, uint32_t l);
+void cw_pack_ext (cw_pack_context* pack_context, int8_t type, const void* v, uint32_t l);
+
+void cw_pack_insert (cw_pack_context* pack_context, const void* v, uint32_t l);
+
+
+/***************************** U N P A C K ********************************/
+
+
+typedef enum
+{
+ CWP_ITEM_MIN_RESERVED_EXT = -128,
+ CWP_ITEM_MAX_RESERVED_EXT = -1,
+ CWP_ITEM_MIN_USER_EXT = 0,
+ CWP_ITEM_MAX_USER_EXT = 127,
+ CWP_ITEM_NIL = 300,
+ CWP_ITEM_BOOLEAN = 301,
+ CWP_ITEM_POSITIVE_INTEGER = 302,
+ CWP_ITEM_NEGATIVE_INTEGER = 303,
+ CWP_ITEM_FLOAT = 304,
+ CWP_ITEM_DOUBLE = 305,
+ CWP_ITEM_STR = 306,
+ CWP_ITEM_BIN = 307,
+ CWP_ITEM_ARRAY = 308,
+ CWP_ITEM_MAP = 309,
+ CWP_ITEM_EXT = 310,
+ CWP_NOT_AN_ITEM = 999,
+} cwpack_item_types;
+
+
+typedef struct {
+ const void* start;
+ uint32_t length;
+} cwpack_blob;
+
+
+typedef struct {
+ uint32_t size;
+} cwpack_container;
+
+
+typedef struct {
+ cwpack_item_types type;
+ union
+ {
+ bool boolean;
+ uint64_t u64;
+ int64_t i64;
+ float real;
+ double long_real;
+ cwpack_container array;
+ cwpack_container map;
+ cwpack_blob str;
+ cwpack_blob bin;
+ cwpack_blob ext;
+ } as;
+} cwpack_item;
+
+struct cw_unpack_context;
+
+typedef int (*unpack_underflow_handler)(struct cw_unpack_context*, unsigned long);
+
+typedef struct cw_unpack_context {
+ cwpack_item item;
+ uint8_t* start;
+ uint8_t* current;
+ uint8_t* end; /* logical end of buffer */
+ int return_code;
+ int err_no; /* handlers can save error here */
+ unpack_underflow_handler handle_unpack_underflow;
+} cw_unpack_context;
+
+
+
+int cw_unpack_context_init (cw_unpack_context* unpack_context, void* data, unsigned long length, unpack_underflow_handler huu);
+
+void cw_unpack_next (cw_unpack_context* unpack_context);
+void cw_skip_items (cw_unpack_context* unpack_context, long item_count);
+
+
+#endif /* CWPack_H__ */
diff --git a/msgpack/cwpack_defines.h b/msgpack/cwpack_defines.h
new file mode 100644
index 0000000..b2f29f6
--- /dev/null
+++ b/msgpack/cwpack_defines.h
@@ -0,0 +1,365 @@
+/* CWPack - cwpack_defines.h */
+/*
+ The MIT License (MIT)
+
+ Copyright (c) 2017 Claes Wihlborg
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of this
+ software and associated documentation files (the "Software"), to deal in the Software
+ without restriction, including without limitation the rights to use, copy, modify,
+ merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+ persons to whom the Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all copies or
+ substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef cwpack_defines_h
+#define cwpack_defines_h
+
+
+
+/************************* A L I G N M E N T ******************************/
+
+/*
+ * Sometime the processor demands that integer access is to an even memory address.
+ * In that case define FORCE_ALIGNMENT
+ */
+
+/* #define FORCE_ALIGNMENT */
+
+
+/************************* C S Y S T E M L I B R A R Y ****************/
+
+/*
+ * The packer uses "memcpy" to move blobs. If you dont want to load C system library
+ * for just that, define FORCE_NO_LIBRARY and CWPack will use an internal "memcpy"
+ */
+
+/* #define FORCE_NO_LIBRARY */
+
+
+
+/************************* B Y T E O R D E R ****************************/
+
+/*
+ * The pack/unpack routines are written in three versions: for big endian, for
+ * little endian and insensitive to byte order. As you can get some speed gain
+ * if the byte order is known, we try that when we can certainly detect it.
+ * Define COMPILE_FOR_BIG_ENDIAN or COMPILE_FOR_LITTLE_ENDIAN if you know.
+ */
+
+#ifndef FORCE_ALIGNMENT
+#if defined(__BYTE_ORDER__) && defined(__ORDER_LITTLE_ENDIAN__) && defined(__ORDER_BIG_ENDIAN__)
+
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#define COMPILE_FOR_BIG_ENDIAN
+#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define COMPILE_FOR_LITTLE_ENDIAN
+#endif
+
+#elif defined(__BYTE_ORDER) && defined(__LITTLE_ENDIAN) && defined(__BIG_ENDIAN)
+
+#if __BYTE_ORDER == __BIG_ENDIAN
+#define COMPILE_FOR_BIG_ENDIAN
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#define COMPILE_FOR_LITTLE_ENDIAN
+#endif
+
+#elif defined(__BIG_ENDIAN__)
+#define COMPILE_FOR_BIG_ENDIAN
+
+#elif defined(__LITTLE_ENDIAN__)
+#define COMPILE_FOR_LITTLE_ENDIAN
+
+#elif defined(__i386__) || defined(__x86_64__)
+#define COMPILE_FOR_LITTLE_ENDIAN
+
+#endif
+#endif
+
+//zzq add
+#include "stdint.h"
+
+//#undef COMPILE_FOR_LITTLE_ENDIAN
+
+
+/******************************* P A C K **********************************/
+
+
+
+#define PACK_ERROR(error_code) \
+{ \
+ pack_context->return_code = error_code; \
+ return; \
+}
+
+
+
+#ifdef COMPILE_FOR_BIG_ENDIAN
+
+#define cw_store16(x) *(uint16_t*)p = *(uint16_t*)&x;
+#define cw_store32(x) *(uint32_t*)p = *(uint32_t*)&x;
+#define cw_store64(x) *(uint64_t*)p = *(uint64_t*)&x;
+
+#else /* Byte order little endian or undetermined */
+
+#ifdef COMPILE_FOR_LITTLE_ENDIAN
+
+#define cw_store16(d) \
+ *(uint16_t*)p = (uint16_t)((((d) >> 8) & 0x0ff) | (d) << 8)
+
+#define cw_store32(x) \
+ *(uint32_t*)p = \
+ ((uint32_t)((((uint32_t)(x)) >> 24) | \
+ (((uint32_t)(x) & 0x00ff0000) >> 8) | \
+ (((uint32_t)(x) & 0x0000ff00) << 8) | \
+ (((uint32_t)(x)) << 24))); \
+
+#define cw_store64(x) \
+ *(uint64_t*)p = \
+ ((uint64_t)( \
+ (((((uint64_t)(x)) >> 40) | \
+ (((uint64_t)(x)) << 24)) & 0x0000ff000000ff00ULL) | \
+ (((((uint64_t)(x)) >> 24) | \
+ (((uint64_t)(x)) << 40)) & 0x00ff000000ff0000ULL) | \
+ (((uint64_t)(x) & 0x000000ff00000000ULL) >> 8) | \
+ (((uint64_t)(x) & 0x00000000ff000000ULL) << 8) | \
+ (((uint64_t)(x)) >> 56) | \
+ (((uint64_t)(x)) << 56))); \
+
+#else /* Byte order undetermined */
+
+#define cw_store16(d) \
+ *p = (uint8_t)(d >> 8); \
+ p[1] = (uint8_t)d;
+
+#define cw_store32(d) \
+ *p = (uint8_t)(d >> 24); \
+ p[1] = (uint8_t)(d >> 16); \
+ p[2] = (uint8_t)(d >> 8); \
+ p[3] = (uint8_t)d;
+
+#define cw_store64(z) \
+ *p = (uint8_t)(z >> 56); \
+ p[1] = (uint8_t)(z >> 48); \
+ p[2] = (uint8_t)(z >> 40); \
+ p[3] = (uint8_t)(z >> 32); \
+ p[4] = (uint8_t)(z >> 24); \
+ p[5] = (uint8_t)(z >> 16); \
+ p[6] = (uint8_t)(z >> 8); \
+ p[7] = (uint8_t)z;
+#endif
+#endif
+
+
+
+#define cw_pack_reserve_space(more) \
+{ \
+ p = pack_context->current; \
+ uint8_t* nyp = p + more; \
+ if (nyp > pack_context->end) \
+ { \
+ if (!pack_context->handle_pack_overflow) \
+ PACK_ERROR(CWP_RC_BUFFER_OVERFLOW) \
+ int rc = pack_context->handle_pack_overflow (pack_context, (unsigned long)(more)); \
+ if (rc) \
+ PACK_ERROR(rc) \
+ p = pack_context->current; \
+ nyp = p + more; \
+ } \
+ pack_context->current = nyp; \
+}
+
+
+#define tryMove0(t) \
+{ \
+ uint8_t *p; \
+ cw_pack_reserve_space(1) \
+ *p = (uint8_t)(t); \
+ return; \
+}
+
+#define tryMove1(t,d) \
+{ \
+ uint8_t *p; \
+ cw_pack_reserve_space(2) \
+ *p++ = (uint8_t)t; \
+ *p = (uint8_t)d; \
+ return; \
+}
+
+#define tryMove2(t,d) \
+{ \
+ uint8_t *p; \
+ cw_pack_reserve_space(3) \
+ *p++ = (uint8_t)t; \
+ cw_store16(d); \
+ return; \
+}
+
+#define tryMove4(t,d) \
+{ \
+ uint8_t *p; \
+ cw_pack_reserve_space(5) \
+ *p++ = (uint8_t)t; \
+ cw_store32(d); \
+ return; \
+}
+
+#define tryMove8(t,d) \
+{ \
+ uint8_t *p; \
+ cw_pack_reserve_space(9) \
+ *p++ = (uint8_t)t; \
+ cw_store64(d); \
+ return; \
+}
+
+
+
+
+/******************************* U N P A C K **********************************/
+
+
+
+#define UNPACK_ERROR(error_code) \
+{ \
+ unpack_context->item.type = CWP_NOT_AN_ITEM; \
+ unpack_context->return_code = error_code; \
+ return; \
+}
+
+
+
+#ifdef COMPILE_FOR_BIG_ENDIAN
+
+#define cw_load16(ptr) tmpu16 = *(uint16_t*)ptr;
+#define cw_load32(ptr) tmpu32 = *(uint32_t*)ptr;
+#define cw_load64(ptr) tmpu64 = *(uint64_t*)ptr;
+
+#else /* Byte order little endian or undetermined */
+
+#ifdef COMPILE_FOR_LITTLE_ENDIAN
+
+#define cw_load16(ptr) \
+ tmpu16 = *(uint16_t*)ptr; \
+ tmpu16 = (uint16_t)((tmpu16<<8) | (tmpu16>>8))
+
+#define cw_load32(ptr) \
+ tmpu32 = *(uint32_t*)ptr; \
+ tmpu32 = (tmpu32<<24) | ((tmpu32 & 0xff00)<<8) | \
+ ((tmpu32 & 0xff0000)>>8) | (tmpu32>>24)
+
+#define cw_load64(ptr) \
+ tmpu64 = *((uint64_t*)ptr); \
+ tmpu64 = ( \
+ (((tmpu64 >> 40) | \
+ (tmpu64 << 24)) & 0x0000ff000000ff00ULL) | \
+ (((tmpu64 >> 24) | \
+ (tmpu64 << 40)) & 0x00ff000000ff0000ULL) | \
+ ((tmpu64 & 0x000000ff00000000ULL) >> 8) | \
+ ((tmpu64 & 0x00000000ff000000ULL) << 8) | \
+ (tmpu64 >> 56) | \
+ (tmpu64 << 56) )
+
+#else /* Byte order undetermined */
+
+#define cw_load16(ptr) \
+ tmpu16 = (uint16_t)((*ptr++) << 8); \
+ tmpu16 |= (uint16_t)(*ptr++)
+
+#define cw_load32(ptr) \
+ tmpu32 = (uint32_t)(*ptr++ << 24); \
+ tmpu32 |= (uint32_t)(*ptr++ << 16); \
+ tmpu32 |= (uint32_t)(*ptr++ << 8); \
+ tmpu32 |= (uint32_t)(*ptr++)
+
+#define cw_load64(ptr) \
+ tmpu64 = ((uint64_t)*ptr++) << 56; \
+ tmpu64 |= ((uint64_t)*ptr++) << 48; \
+ tmpu64 |= ((uint64_t)*ptr++) << 40; \
+ tmpu64 |= ((uint64_t)*ptr++) << 32; \
+ tmpu64 |= ((uint64_t)*ptr++) << 24; \
+ tmpu64 |= ((uint64_t)*ptr++) << 16; \
+ tmpu64 |= ((uint64_t)*ptr++) << 8; \
+ tmpu64 |= (uint64_t)*ptr++
+
+#endif
+#endif
+
+
+
+#define cw_unpack_assert_space(more) \
+{ \
+ p = unpack_context->current; \
+ uint8_t* nyp = p + more; \
+ if (nyp > unpack_context->end) \
+ { \
+ if (!unpack_context->handle_unpack_underflow) \
+ UNPACK_ERROR(buffer_end_return_code) \
+ int rc = unpack_context->handle_unpack_underflow (unpack_context, (unsigned long)(more)); \
+ if (rc != CWP_RC_OK) \
+ { \
+ if (rc != CWP_RC_END_OF_INPUT) \
+ UNPACK_ERROR(rc) \
+ else \
+ UNPACK_ERROR(buffer_end_return_code) \
+ } \
+ p = unpack_context->current; \
+ nyp = p + more; \
+ } \
+ unpack_context->current = nyp; \
+}
+
+
+#define cw_unpack_assert_blob(blob) \
+ cw_unpack_assert_space(unpack_context->item.as.blob.length); \
+ unpack_context->item.as.blob.start = p; \
+ return;
+
+
+#define getDDItem(typ,var,val) \
+ unpack_context->item.type = typ; \
+ unpack_context->item.as.var = val;
+
+#define getDDItem1(typ,var,cast) \
+ unpack_context->item.type = typ; \
+ cw_unpack_assert_space(1); \
+ unpack_context->item.as.var = (cast)*p;
+
+#define getDDItem2(typ,var,cast) \
+ unpack_context->item.type = typ; \
+ cw_unpack_assert_space(2); \
+ cw_load16(p); \
+ unpack_context->item.as.var = (cast)tmpu16;
+
+#define getDDItem4(typ,var,cast) \
+ unpack_context->item.type = typ; \
+ cw_unpack_assert_space(4); \
+ cw_load32(p); \
+ unpack_context->item.as.var = (cast)tmpu32;
+
+#define getDDItem8(typ) \
+ unpack_context->item.type = typ; \
+ cw_unpack_assert_space(8); \
+ cw_load64(p); \
+ unpack_context->item.as.u64 = tmpu64;
+
+#define getDDItemFix(len) \
+ cw_unpack_assert_space(1); \
+ unpack_context->item.type = *(int8_t*)p; \
+ unpack_context->item.as.ext.length = len; \
+ cw_unpack_assert_blob(ext);
+
+
+
+
+#endif /* cwpack_defines_h */
diff --git a/nec_apdu.h b/nec_apdu.h
new file mode 100644
index 0000000..c1bf60a
--- /dev/null
+++ b/nec_apdu.h
@@ -0,0 +1,21 @@
+#ifndef _NEC_APDU_H_
+#define _NEC_APDU_H_
+
+#include "config.h"
+
+int8 psam_poweron(uint8 cid);
+void psam_powreoff(uint8 cid);
+int8 card_request(uint8* sak,uint8 snr[8]);
+int8 card_m1_mode(uint8 cardphyid[8]);
+int8 card_cpu_mode(void);
+int8 card_cpu_exist(void);
+int8 card_rf_reset(void);
+void card_radio_on(void);
+void card_radio_off(void);
+uint16 card_m1_auth(uint8* cardphyid,uint8 blockno, uint8 key[6]);
+uint16 card_m1_read(uint8 blockno,uint8 readbuf[16]);
+uint16 card_m1_write(uint8 blockno,uint8 writebuf[16]);
+uint16 card_cpu_exchange(uint8* cmd_buf,uint8 cmd_len,uint8 ExpectedResponseLength,
+ uint8** rec_buf,uint8* rec_buf_len);
+
+#endif
diff --git a/nec_hardware.h b/nec_hardware.h
new file mode 100644
index 0000000..a9a1e7c
--- /dev/null
+++ b/nec_hardware.h
@@ -0,0 +1,21 @@
+#ifndef _NEC_HARDWARE_H_
+#define _NEC_HARDWARE_H_
+
+#include "config.h"
+//#include "./g401301/src/G401_drv_hw_V01.h"
+//#include "./g401301/src/stm32f10x_it.h"
+//#define DEVICE_TYPE 'd';
+
+
+/*LED ÏÔʾ»º³åÇø*/
+//extern uint8 LEDSEG[7]; //ÏÔʾ»º³åÇø
+
+uint16 sp_init(void);
+void sp_feed_dog(void);
+void sp_valve_control(void);
+void sp_flowsensor_control(void);
+uint32 sp_flowsensor_get_count(void);
+void sp_flowsensor_count_clear(void);
+uint8 sp_flowsensor_check_valid(void);
+
+#endif
diff --git a/st_fw_lib/inc/core_cm3.h b/st_fw_lib/inc/core_cm3.h
new file mode 100644
index 0000000..7ab7b4b
--- /dev/null
+++ b/st_fw_lib/inc/core_cm3.h
@@ -0,0 +1,1818 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V1.30
+ * @date 30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ * - Error 10: \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';'
+ * .
+ * - Error 530: \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized
+ * .
+ * - Error 550: \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed
+ * .
+ * - Error 754: \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
+ * .
+ * - Error 750: \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
+ * .
+ * - Error 528: \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
+ * .
+ * - Error 751: \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
+ * .
+ * Note: To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core registers and bitfields
+ - Cortex-M core peripheral base address
+ @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+#include <stdint.h> /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
+} NVIC_Type;
+/*@}*/ /* end of group CMSIS_CM3_NVIC */
+
+
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
+ memory mapped structure for System Control Block (SCB)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM3_SCB */
+
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+ memory mapped structure for SysTick
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+/*@}*/ /* end of group CMSIS_CM3_ITM */
+
+
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
+ memory mapped structure for Interrupt Type
+ @{
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
+ memory mapped structure for Memory Protection Unit (MPU)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@}*/ /* end of group CMSIS_CM3_MPU */
+#endif
+
+
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
+ memory mapped structure for Core Debug Register
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_register */
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
+
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
+static __INLINE void __WFI() { __ASM ("wfi"); }
+static __INLINE void __WFE() { __ASM ("wfe"); }
+static __INLINE void __SEV() { __ASM ("sev"); }
+static __INLINE void __CLREX() { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void) */
+/* intrinsic void __DSB(void) */
+/* intrinsic void __DMB(void) */
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }
+static __INLINE void __SEV() { __ASM volatile ("sev"); }
+static __INLINE void __ISB() { __ASM volatile ("isb"); }
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
+ Core Function Interface containing:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Reset Functions
+*/
+/*@{*/
+
+/* ########################## NVIC functions #################################### */
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param PriorityGroup is priority grouping field
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @return priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn The positive number of the external interrupt to enable
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn The positive number of the external interrupt to disable
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn The number of the device specifc interrupt
+ * @return 1 = interrupt pending, 0 = interrupt not pending
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for set pending
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for clear pending
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for read active bit
+ * @return 1 = interrupt active, 0 = interrupt not active
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn The number of the interrupt for set priority
+ * @param priority The priority to set
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn The number of the interrupt for get priority
+ * @return The priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/**
+ * @brief Encode the priority for an interrupt
+ *
+ * @param PriorityGroup The used priority group
+ * @param PreemptPriority The preemptive priority value (starting from 0)
+ * @param SubPriority The sub priority value (starting from 0)
+ * @return The encoded priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/**
+ * @brief Decode the priority of an interrupt
+ *
+ * @param Priority The priority for the interrupt
+ * @param PriorityGroup The used priority group
+ * @param pPreemptPriority The preemptive priority value (starting from 0)
+ * @param pSubPriority The sub priority value (starting from 0)
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param ticks number of ticks between two interrupts
+ * @return 1 = failed, 0 = successful
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+
+
+
+/* ################################## Reset function ############################################ */
+
+/**
+ * @brief Initiate a system reset request.
+ *
+ * Initiate a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
+ Core Debug Interface containing:
+ - Core Debug Receive / Transmit Functions
+ - Core Debug Defines
+ - Core Debug Variables
+*/
+/*@{*/
+
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/**
+ * @brief Outputs a character via the ITM channel 0
+ *
+ * @param ch character to output
+ * @return character to output
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/**
+ * @brief Inputs a character via variable ITM_RxBuffer
+ *
+ * @return received character, -1 = no character received
+ *
+ * The function inputs a character via variable ITM_RxBuffer.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE int ITM_ReceiveChar (void) {
+ int ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ * @brief Check if a character via variable ITM_RxBuffer is available
+ *
+ * @return 1 = character available, 0 = no character available
+ *
+ * The function checks variable ITM_RxBuffer whether a character is available or not.
+ * The function returns '1' if a character is available and '0' if no character is available.
+ */
+static __INLINE int ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
diff --git a/st_fw_lib/inc/misc.h b/st_fw_lib/inc/misc.h
new file mode 100644
index 0000000..9a6bd07
--- /dev/null
+++ b/st_fw_lib/inc/misc.h
@@ -0,0 +1,220 @@
+/**
+ ******************************************************************************
+ * @file misc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete STM32 Devices IRQ Channels list, please
+ refer to stm32f10x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_adc.h b/st_fw_lib/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..c465d33
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_adc.h
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
+ dual mode.
+ This parameter can be a value of @ref ADC_mode */
+
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode
+ * @{
+ */
+
+#define ADC_Mode_Independent ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+ ((MODE) == ADC_Mode_RegInjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult) || \
+ ((MODE) == ADC_Mode_FastInterl) || \
+ ((MODE) == ADC_Mode_SlowInterl) || \
+ ((MODE) == ADC_Mode_AlterTrig))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+#define ADC_Channel_10 ((uint8_t)0x0A)
+#define ADC_Channel_11 ((uint8_t)0x0B)
+#define ADC_Channel_12 ((uint8_t)0x0C)
+#define ADC_Channel_13 ((uint8_t)0x0D)
+#define ADC_Channel_14 ((uint8_t)0x0E)
+#define ADC_Channel_15 ((uint8_t)0x0F)
+#define ADC_Channel_16 ((uint8_t)0x10)
+#define ADC_Channel_17 ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+ ((TIME) == ADC_SampleTime_7Cycles5) || \
+ ((TIME) == ADC_SampleTime_13Cycles5) || \
+ ((TIME) == ADC_SampleTime_28Cycles5) || \
+ ((TIME) == ADC_SampleTime_41Cycles5) || \
+ ((TIME) == ADC_SampleTime_55Cycles5) || \
+ ((TIME) == ADC_SampleTime_71Cycles5) || \
+ ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_IT_EOC ((uint16_t)0x0220)
+#define ADC_IT_AWD ((uint16_t)0x0140)
+#define ADC_IT_JEOC ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+ ((IT) == ADC_IT_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWD ((uint8_t)0x01)
+#define ADC_FLAG_EOC ((uint8_t)0x02)
+#define ADC_FLAG_JEOC ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)
+#define ADC_FLAG_STRT ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+ ((FLAG) == ADC_FLAG_STRT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_rank
+ * @{
+ */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_bkp.h b/st_fw_lib/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..275c5e1
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_bkp.h
@@ -0,0 +1,195 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the BKP firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup BKP
+ * @{
+ */
+
+/** @defgroup BKP_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Tamper_Pin_active_level
+ * @{
+ */
+
+#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+ ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+ * @{
+ */
+
+#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+ ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+ * @}
+ */
+
+/** @defgroup Data_Backup_Register
+ * @{
+ */
+
+#define BKP_DR1 ((uint16_t)0x0004)
+#define BKP_DR2 ((uint16_t)0x0008)
+#define BKP_DR3 ((uint16_t)0x000C)
+#define BKP_DR4 ((uint16_t)0x0010)
+#define BKP_DR5 ((uint16_t)0x0014)
+#define BKP_DR6 ((uint16_t)0x0018)
+#define BKP_DR7 ((uint16_t)0x001C)
+#define BKP_DR8 ((uint16_t)0x0020)
+#define BKP_DR9 ((uint16_t)0x0024)
+#define BKP_DR10 ((uint16_t)0x0028)
+#define BKP_DR11 ((uint16_t)0x0040)
+#define BKP_DR12 ((uint16_t)0x0044)
+#define BKP_DR13 ((uint16_t)0x0048)
+#define BKP_DR14 ((uint16_t)0x004C)
+#define BKP_DR15 ((uint16_t)0x0050)
+#define BKP_DR16 ((uint16_t)0x0054)
+#define BKP_DR17 ((uint16_t)0x0058)
+#define BKP_DR18 ((uint16_t)0x005C)
+#define BKP_DR19 ((uint16_t)0x0060)
+#define BKP_DR20 ((uint16_t)0x0064)
+#define BKP_DR21 ((uint16_t)0x0068)
+#define BKP_DR22 ((uint16_t)0x006C)
+#define BKP_DR23 ((uint16_t)0x0070)
+#define BKP_DR24 ((uint16_t)0x0074)
+#define BKP_DR25 ((uint16_t)0x0078)
+#define BKP_DR26 ((uint16_t)0x007C)
+#define BKP_DR27 ((uint16_t)0x0080)
+#define BKP_DR28 ((uint16_t)0x0084)
+#define BKP_DR29 ((uint16_t)0x0088)
+#define BKP_DR30 ((uint16_t)0x008C)
+#define BKP_DR31 ((uint16_t)0x0090)
+#define BKP_DR32 ((uint16_t)0x0094)
+#define BKP_DR33 ((uint16_t)0x0098)
+#define BKP_DR34 ((uint16_t)0x009C)
+#define BKP_DR35 ((uint16_t)0x00A0)
+#define BKP_DR36 ((uint16_t)0x00A4)
+#define BKP_DR37 ((uint16_t)0x00A8)
+#define BKP_DR38 ((uint16_t)0x00AC)
+#define BKP_DR39 ((uint16_t)0x00B0)
+#define BKP_DR40 ((uint16_t)0x00B4)
+#define BKP_DR41 ((uint16_t)0x00B8)
+#define BKP_DR42 ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Functions
+ * @{
+ */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_can.h b/st_fw_lib/inc/stm32f10x_can.h
new file mode 100644
index 0000000..d185aa2
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_can.h
@@ -0,0 +1,697 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the CAN firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+ ((PERIPH) == CAN2))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of
+ @ref CAN_operating_mode */
+
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
+
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
+
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or
+ DISABLE. */
+
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMsg;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mode
+ * @{
+ */
+
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+ ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || \
+ ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
+
+
+/**
+ * @defgroup CAN_Operating_Mode
+ * @{
+ */
+#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+ ((MODE) == CAN_OperatingMode_Normal)|| \
+ ((MODE) == CAN_OperatingMode_Sleep))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#else
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+ ((MODE) == CAN_FilterMode_IdList))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+ ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+ ((FIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+ ((IDTYPE) == CAN_Id_Extended))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+
+
+
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Legacy
+ * @{
+ */
+#define CANINITFAILED CAN_InitStatus_Failed
+#define CANINITOK CAN_InitStatus_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Id_Standard
+#define CAN_ID_EXT CAN_Id_Extended
+#define CAN_RTR_DATA CAN_RTR_Data
+#define CAN_RTR_REMOTE CAN_RTR_Remote
+#define CANTXFAILE CAN_TxStatus_Failed
+#define CANTXOK CAN_TxStatus_Ok
+#define CANTXPENDING CAN_TxStatus_Pending
+#define CAN_NO_MB CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED CAN_Sleep_Failed
+#define CANSLEEPOK CAN_Sleep_Ok
+#define CANWAKEUPFAILED CAN_WakeUp_Failed
+#define CANWAKEUPOK CAN_WakeUp_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions
+ * @{
+ */
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CAN_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_cec.h b/st_fw_lib/inc/stm32f10x_cec.h
new file mode 100644
index 0000000..7ce6896
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_cec.h
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_cec.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the CEC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CEC_H
+#define __STM32F10x_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+
+/** @defgroup CEC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init structure definition
+ */
+typedef struct
+{
+ uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
+ This parameter can be a value of @ref CEC_BitTiming_Mode */
+ uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
+ This parameter can be a value of @ref CEC_BitPeriod_Mode */
+}CEC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CEC_BitTiming_Mode
+ * @{
+ */
+#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
+
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
+ ((MODE) == CEC_BitTimingErrFreeMode))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BitPeriod_Mode
+ * @{
+ */
+#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
+ ((MODE) == CEC_BitPeriodFlexibleMode))
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_interrupts_definition
+ * @{
+ */
+#define CEC_IT_TERR CEC_CSR_TERR
+#define CEC_IT_TBTRF CEC_CSR_TBTRF
+#define CEC_IT_RERR CEC_CSR_RERR
+#define CEC_IT_RBTF CEC_CSR_RBTF
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
+ ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Own_Address
+ * @{
+ */
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Prescaler
+ * @{
+ */
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_flags_definition
+ * @{
+ */
+
+/**
+ * @brief ESR register flags
+ */
+#define CEC_FLAG_BTE ((uint32_t)0x10010000)
+#define CEC_FLAG_BPE ((uint32_t)0x10020000)
+#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
+#define CEC_FLAG_SBE ((uint32_t)0x10080000)
+#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
+#define CEC_FLAG_LINE ((uint32_t)0x10200000)
+#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
+
+/**
+ * @brief CSR register flags
+ */
+#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
+#define CEC_FLAG_TERR ((uint32_t)0x00000004)
+#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
+#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
+#define CEC_FLAG_REOM ((uint32_t)0x00000020)
+#define CEC_FLAG_RERR ((uint32_t)0x00000040)
+#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
+ ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
+ ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
+ ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
+ ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
+ ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
+ ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions
+ * @{
+ */
+void CEC_DeInit(void);
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ITConfig(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
+void CEC_SendDataByte(uint8_t Data);
+uint8_t CEC_ReceiveDataByte(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessageCmd(FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CEC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_crc.h b/st_fw_lib/inc/stm32f10x_crc.h
new file mode 100644
index 0000000..3362fca
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_crc.h
@@ -0,0 +1,94 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CRC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_dac.h b/st_fw_lib/inc/stm32f10x_dac.h
new file mode 100644
index 0000000..174773c
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_dac.h
@@ -0,0 +1,317 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in High-density devices*/
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
+ only in Medium-density and Low-density Value Line devices*/
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+ ((STATE) == DAC_OutputBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/** @defgroup DAC_interrupts_definition
+ * @{
+ */
+
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+ * @}
+ */
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+#endif
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DAC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_dbgmcu.h b/st_fw_lib/inc/stm32f10x_dbgmcu.h
new file mode 100644
index 0000000..89ceb9a
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_dbgmcu.h
@@ -0,0 +1,119 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the DBGMCU
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DBGMCU_H
+#define __STM32F10x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+
+/** @defgroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
+#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
+#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
+#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
+#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
+#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
+#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
+#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
+#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
+#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_DBGMCU_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_dma.h b/st_fw_lib/inc/stm32f10x_dma.h
new file mode 100644
index 0000000..14275fe
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_dma.h
@@ -0,0 +1,439 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+ ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DMA_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_exti.h b/st_fw_lib/inc/stm32f10x_exti.h
new file mode 100644
index 0000000..bb9d7f6
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_exti.h
@@ -0,0 +1,184 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the EXTI firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+ Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_flash.h b/st_fw_lib/inc/stm32f10x_flash.h
new file mode 100644
index 0000000..63720de
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_flash.h
@@ -0,0 +1,426 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_PG,
+ FLASH_ERROR_WRP,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1) || \
+ ((LATENCY) == FLASH_Latency_2))
+/**
+ * @}
+ */
+
+/** @defgroup Half_Cycle_Enable_Disable
+ * @{
+ */
+
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+ ((STATE) == FLASH_HalfCycleAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+ ((STATE) == FLASH_PrefetchBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
+
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+#ifdef STM32F10X_XL
+/**
+ * @}
+ */
+/** @defgroup FLASH_Boot
+ * @{
+ */
+#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+ and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+ and this parameter is selected the device will boot from Bank 2 or Bank 1,
+ depending on the activation of the bank */
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
+#endif
+/**
+ * @}
+ */
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+#ifdef STM32F10X_XL
+#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
+#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
+
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#else
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+#ifdef STM32F10X_XL
+#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
+
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_OPTERR)|| \
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
+ ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
+#else
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_OPTERR))
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for all STM32F10x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/*------------ New function used for all STM32F10x devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef STM32F10X_XL
+/*---- New Functions used only with STM32F10x_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseAllBank2Pages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_fsmc.h b/st_fw_lib/inc/stm32f10x_fsmc.h
new file mode 100644
index 0000000..6e1769d
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_fsmc.h
@@ -0,0 +1,733 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the FSMC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FSMC_H
+#define __STM32F10x_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/** @defgroup FSMC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief Timing parameters For NOR/SRAM Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories. */
+
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories.*/
+
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between 0 and 0xFF.
+ @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is only used for multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+ This parameter can be a value between 1 and 0xF.
+ @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The value of this parameter depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between 0 and 0xF in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/**
+ * @brief FSMC NOR/SRAM Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the databus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory bank.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+/**
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between 0 and 0xFF.*/
+
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command deassertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ databus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/**
+ * @brief FSMC NAND Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/**
+ * @brief FSMC PCCARD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
+}FSMC_PCCARDInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Bank
+ * @{
+ */
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Bank
+ * @{
+ */
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
+/**
+ * @}
+ */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \
+ ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+ ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+ ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Width
+ * @{
+ */
+
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+ ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait
+ * @{
+ */
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+ ((STATE) == FSMC_AsynchronousWait_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+ ((POLARITY) == FSMC_WaitSignalPolarity_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+ ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+ ((OPERATION) == FSMC_WriteOperation_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+ ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+ ((MODE) == FSMC_ExtendedMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+ ((BURST) == FSMC_WriteBurst_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B ((uint32_t)0x10000000)
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+ ((MODE) == FSMC_AccessMode_B) || \
+ ((MODE) == FSMC_AccessMode_C) || \
+ ((MODE) == FSMC_AccessMode_D))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_PCCARD_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Wait_feature
+ * @{
+ */
+
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+ ((FEATURE) == FSMC_Waitfeature_Enable))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_ECC
+ * @{
+ */
+
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+ ((STATE) == FSMC_ECC_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size
+ * @{
+ */
+
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TCLR_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt_sources
+ * @{
+ */
+
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
+#define FSMC_IT_Level ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+ ((IT) == FSMC_IT_Level) || \
+ ((IT) == FSMC_IT_FallingEdge))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Flags
+ * @{
+ */
+
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+ ((FLAG) == FSMC_FLAG_Level) || \
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \
+ ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Functions
+ * @{
+ */
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_PCCARDDeInit(void);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_FSMC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_gpio.h b/st_fw_lib/inc/stm32f10x_gpio.h
new file mode 100644
index 0000000..dd28da8
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_gpio.h
@@ -0,0 +1,385 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF) || \
+ ((PERIPH) == GPIOG))
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_Speed_10MHz = 1,
+ GPIO_Speed_2MHz,
+ GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+ ((SPEED) == GPIO_Speed_50MHz))
+
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Remap_define
+ * @{
+ */
+
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ to TIM2 Internal Trigger 1 for calibration
+ (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
+
+#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
+#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
+#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
+
+#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
+#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
+#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
+ only for High density Value line devices) */
+
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
+ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
+ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
+ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
+ ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
+ ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
+ ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
+ ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
+ ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
+ ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
+ ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+
+/**
+ * @}
+ */
+
+/** @defgroup Ethernet_Media_Interface
+ * @{
+ */
+#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_i2c.h b/st_fw_lib/inc/stm32f10x_i2c.h
new file mode 100644
index 0000000..60e4b14
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_i2c.h
@@ -0,0 +1,684 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+ ((CYCLE) == I2C_DutyCycle_2))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint16_t)0x0400)
+#define I2C_Ack_Disable ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+ ((STATE) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint8_t)0x00)
+#define I2C_Direction_Receiver ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_DR ((uint8_t)0x10)
+#define I2C_Register_SR1 ((uint8_t)0x14)
+#define I2C_Register_SR2 ((uint8_t)0x18)
+#define I2C_Register_CCR ((uint8_t)0x1C)
+#define I2C_Register_TRISE ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_DR) || \
+ ((REGISTER) == I2C_Register_SR1) || \
+ ((REGISTER) == I2C_Register_SR2) || \
+ ((REGISTER) == I2C_Register_CCR) || \
+ ((REGISTER) == I2C_Register_TRISE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+ ((ALERT) == I2C_SMBusAlert_High))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PECPosition_Next ((uint16_t)0x0800)
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+ ((POSITION) == I2C_PECPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
+ ((POSITION) == I2C_NACKPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_BUF ((uint16_t)0x0400)
+#define I2C_IT_EVT ((uint16_t)0x0200)
+#define I2C_IT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
+#define I2C_IT_PECERR ((uint32_t)0x01001000)
+#define I2C_IT_OVR ((uint32_t)0x01000800)
+#define I2C_IT_AF ((uint32_t)0x01000400)
+#define I2C_IT_ARLO ((uint32_t)0x01000200)
+#define I2C_IT_BERR ((uint32_t)0x01000100)
+#define I2C_IT_TXE ((uint32_t)0x06000080)
+#define I2C_IT_RXNE ((uint32_t)0x06000040)
+#define I2C_IT_STOPF ((uint32_t)0x02000010)
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)
+#define I2C_IT_BTF ((uint32_t)0x02000004)
+#define I2C_IT_ADDR ((uint32_t)0x02000002)
+#define I2C_IT_SB ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief SR2 register flags
+ */
+
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
+/**
+ * @brief SR1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)
+#define I2C_FLAG_AF ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+#define I2C_FLAG_SB ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+ I2C Master Events (Events grouped in order of communication)
+ ==========================================*/
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateSTART() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* --EV5 */
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_ReceiveData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/*========================================
+
+ I2C Slave Events (Events grouped in order of communication)
+ ==========================================*/
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_AcknowledgeConfig()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* --EV4 */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
+/*=========================== End of Events Description ==========================================*/
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_clock_speed
+ * @{
+ */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (SR1 and SR2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occurred.
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the limitations of I2C_GetFlagStatus() function (see below).
+ * The returned value could be compared to events already defined in the
+ * library (stm32f10x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlagStatus() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_iwdg.h b/st_fw_lib/inc/stm32f10x_iwdg.h
new file mode 100644
index 0000000..25b0bb5
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_iwdg.h
@@ -0,0 +1,140 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IWDG_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_pwr.h b/st_fw_lib/inc/stm32f10x_pwr.h
new file mode 100644
index 0000000..1c025e2
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_pwr.h
@@ -0,0 +1,156 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+ * @}
+ */
+
+/** @defgroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
+
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU ((uint32_t)0x00000001)
+#define PWR_FLAG_SB ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_PWR_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_rcc.h b/st_fw_lib/inc/stm32f10x_rcc.h
new file mode 100644
index 0000000..1149c34
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_rcc.h
@@ -0,0 +1,727 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the RCC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint32_t)0x00000000)
+#define RCC_HSE_ON ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup PLL_entry_clock_source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
+ #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
+ #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))
+#else
+ #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup PLL_multiplication_factor
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define RCC_PLLMul_2 ((uint32_t)0x00000000)
+ #define RCC_PLLMul_3 ((uint32_t)0x00040000)
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_10 ((uint32_t)0x00200000)
+ #define RCC_PLLMul_11 ((uint32_t)0x00240000)
+ #define RCC_PLLMul_12 ((uint32_t)0x00280000)
+ #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
+ #define RCC_PLLMul_14 ((uint32_t)0x00300000)
+ #define RCC_PLLMul_15 ((uint32_t)0x00340000)
+ #define RCC_PLLMul_16 ((uint32_t)0x00380000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+
+#else
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
+
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_6_5))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup PREDIV1_division_factor
+ * @{
+ */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
+ #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
+ #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
+ #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
+ #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
+ #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
+ #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
+ #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
+ #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
+ #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
+ #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
+ #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
+ #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
+ #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
+ #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
+
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+#endif
+/**
+ * @}
+ */
+
+
+/** @defgroup PREDIV1_clock_source
+ * @{
+ */
+#ifdef STM32F10X_CL
+/* PREDIV1 clock source (for STM32 connectivity line devices) */
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
+ ((SOURCE) == RCC_PREDIV1_Source_PLL2))
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/* PREDIV1 clock source (for STM32 Value line devices) */
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
+#endif
+/**
+ * @}
+ */
+
+#ifdef STM32F10X_CL
+/** @defgroup PREDIV2_division_factor
+ * @{
+ */
+
+ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
+ #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
+ #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
+ #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
+ #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
+ #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
+ #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
+ #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
+ #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
+ #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
+ #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
+ #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
+ #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
+ #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
+ #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
+
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
+ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
+ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
+ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
+ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
+ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
+ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
+ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL2_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
+ #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
+ #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
+ #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
+ #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
+ #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
+ #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
+ #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
+ #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
+
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
+ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
+ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
+ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
+ ((MUL) == RCC_PLL2Mul_20))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL3_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
+ #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
+ #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
+ #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
+ #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
+ #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
+ #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
+ #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
+ #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
+
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
+ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
+ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
+ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
+ ((MUL) == RCC_PLL3Mul_20))
+/**
+ * @}
+ */
+
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+#else
+ #define RCC_IT_PLL2RDY ((uint8_t)0x20)
+ #define RCC_IT_PLL3RDY ((uint8_t)0x40)
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+#endif /* STM32F10X_CL */
+
+
+/**
+ * @}
+ */
+
+#ifndef STM32F10X_CL
+/** @defgroup USB_Device_clock_source
+ * @{
+ */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+ * @}
+ */
+#else
+/** @defgroup USB_OTG_FS_clock_source
+ * @{
+ */
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
+
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
+ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
+/**
+ * @}
+ */
+#endif /* STM32F10X_CL */
+
+
+#ifdef STM32F10X_CL
+/** @defgroup I2S2_clock_source
+ * @{
+ */
+ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+
+/** @defgroup I2S3_clock_source
+ * @{
+ */
+ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+ * @}
+ */
+
+/** @defgroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_Bypass ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+ * @}
+ */
+
+/** @defgroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NoClock ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2))
+#else
+ #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
+ #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
+ #define RCC_MCO_XT1 ((uint8_t)0x0A)
+ #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
+
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
+ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
+ ((MCO) == RCC_MCO_PLL3CLK))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#else
+ #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
+ #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#endif /* STM32F10X_CL */
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+#endif
+
+#ifdef STM32F10X_CL
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+ void RCC_PLL2Cmd(FunctionalState NewState);
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+ void RCC_PLL3Cmd(FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
+#ifndef STM32F10X_CL
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+#else
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+
+#ifdef STM32F10X_CL
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RCC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_rtc.h b/st_fw_lib/inc/stm32f10x_rtc.h
new file mode 100644
index 0000000..fd8beb5
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_rtc.h
@@ -0,0 +1,135 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RTC_interrupts_define
+ * @{
+ */
+
+#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
+#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
+#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+ ((IT) == RTC_IT_SEC))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_interrupts_flags
+ * @{
+ */
+
+#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
+#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
+#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+ ((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions
+ * @{
+ */
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RTC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_sdio.h b/st_fw_lib/inc/stm32f10x_sdio.h
new file mode 100644
index 0000000..81c058a
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_sdio.h
@@ -0,0 +1,531 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the SDIO firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between 0x00 and 0xFF. */
+
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register */
+
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+ ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+ ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+ ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+ ((WIDE) == SDIO_BusWide_8b))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Power_State
+ * @{
+ */
+
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+ * @}
+ */
+
+
+/** @defgroup SDIO_Interrupt_sources
+ * @{
+ */
+
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+
+#define SDIO_Response_No ((uint32_t)0x00000000)
+#define SDIO_Response_Short ((uint32_t)0x00000040)
+#define SDIO_Response_Long ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+ ((RESPONSE) == SDIO_Response_Short) || \
+ ((RESPONSE) == SDIO_Response_Long))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+ ((WAIT) == SDIO_Wait_Pend))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+ ((SIZE) == SDIO_DataBlockSize_2b) || \
+ ((SIZE) == SDIO_DataBlockSize_4b) || \
+ ((SIZE) == SDIO_DataBlockSize_8b) || \
+ ((SIZE) == SDIO_DataBlockSize_16b) || \
+ ((SIZE) == SDIO_DataBlockSize_32b) || \
+ ((SIZE) == SDIO_DataBlockSize_64b) || \
+ ((SIZE) == SDIO_DataBlockSize_128b) || \
+ ((SIZE) == SDIO_DataBlockSize_256b) || \
+ ((SIZE) == SDIO_DataBlockSize_512b) || \
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \
+ ((SIZE) == SDIO_DataBlockSize_16384b))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+ ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+ ((MODE) == SDIO_TransferMode_Block))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Flags
+ * @{
+ */
+
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+ ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Functions
+ * @{
+ */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_SDIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_spi.h b/st_fw_lib/inc/stm32f10x_spi.h
new file mode 100644
index 0000000..23cc26d
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_spi.h
@@ -0,0 +1,487 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the SPI firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DataSize_16b ((uint16_t)0x0800)
+#define SPI_DataSize_8b ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+ ((DATASIZE) == SPI_DataSize_8b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode
+ * @{
+ */
+
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx) || \
+ ((MODE) == I2S_Mode_MasterRx) )
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard
+ * @{
+ */
+
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AudioFreq_192k ((uint32_t)192000)
+#define I2S_AudioFreq_96k ((uint32_t)96000)
+#define I2S_AudioFreq_48k ((uint32_t)48000)
+#define I2S_AudioFreq_44k ((uint32_t)44100)
+#define I2S_AudioFreq_32k ((uint32_t)32000)
+#define I2S_AudioFreq_22k ((uint32_t)22050)
+#define I2S_AudioFreq_16k ((uint32_t)16000)
+#define I2S_AudioFreq_11k ((uint32_t)11025)
+#define I2S_AudioFreq_8k ((uint32_t)8000)
+#define I2S_AudioFreq_Default ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+ ((FREQ) <= I2S_AudioFreq_192k)) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_IT_CRCERR ((uint8_t)0x54)
+#define I2S_IT_UDR ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_SPI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_tim.h b/st_fw_lib/inc/stm32f10x_tim.h
new file mode 100644
index 0000000..65bf76a
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_tim.h
@@ -0,0 +1,1164 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/**
+ * @brief BDTR structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10)|| \
+ ((PERIPH) == TIM11)|| \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM13)|| \
+ ((PERIPH) == TIM14)|| \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST1: TIM 1 and 8 */
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8, 15 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM15))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM15))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10)|| \
+ ((PERIPH) == TIM11)|| \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM13)|| \
+ ((PERIPH) == TIM14)|| \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+ ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+ ((STATE) == TIM_OutputNState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+ ((CCXN) == TIM_CCxN_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+ ((STATE) == TIM_Break_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+ ((POLARITY) == TIM_BreakPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+ ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+ ((LEVEL) == TIM_LOCKLevel_1) || \
+ ((LEVEL) == TIM_LOCKLevel_2) || \
+ ((LEVEL) == TIM_LOCKLevel_3))
+/**
+ * @}
+ */
+
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+ ((STATE) == TIM_OSSIState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+ ((STATE) == TIM_OSSRState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+ ((STATE) == TIM_OCIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+ ((STATE) == TIM_OCNIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling))
+#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \
+ ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_Trigger) || \
+ ((IT) == TIM_IT_Break))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_COM ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_Break ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_Break) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_TIM_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_usart.h b/st_fw_lib/inc/stm32f10x_usart.h
new file mode 100644
index 0000000..162fa87
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_usart.h
@@ -0,0 +1,412 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4) || \
+ ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint16_t)0x0000)
+#define USART_WordLength_9b ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint16_t)0x0000)
+#define USART_StopBits_0_5 ((uint16_t)0x1000)
+#define USART_StopBits_2 ((uint16_t)0x2000)
+#define USART_StopBits_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_0_5) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint16_t)0x0000)
+#define USART_Parity_Even ((uint16_t)0x0400)
+#define USART_Parity_Odd ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx ((uint16_t)0x0004)
+#define USART_Mode_Tx ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_Clock_Disable ((uint16_t)0x0000)
+#define USART_Clock_Enable ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint16_t)0x0000)
+#define USART_CPOL_High ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint16_t)0x0000)
+#define USART_CPHA_2Edge ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint16_t)0x0000)
+#define USART_LastBit_Enable ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_LBD ((uint16_t)0x0846)
+#define USART_IT_CTS ((uint16_t)0x096A)
+#define USART_IT_ERR ((uint16_t)0x0060)
+#define USART_IT_ORE ((uint16_t)0x0360)
+#define USART_IT_NE ((uint16_t)0x0260)
+#define USART_IT_FE ((uint16_t)0x0160)
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAReq_Tx ((uint16_t)0x0080)
+#define USART_DMAReq_Rx ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTS ((uint16_t)0x0200)
+#define USART_FLAG_LBD ((uint16_t)0x0100)
+#define USART_FLAG_TXE ((uint16_t)0x0080)
+#define USART_FLAG_TC ((uint16_t)0x0040)
+#define USART_FLAG_RXNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLE ((uint16_t)0x0010)
+#define USART_FLAG_ORE ((uint16_t)0x0008)
+#define USART_FLAG_NE ((uint16_t)0x0004)
+#define USART_FLAG_FE ((uint16_t)0x0002)
+#define USART_FLAG_PE ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+ ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTS))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_USART_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/inc/stm32f10x_wwdg.h b/st_fw_lib/inc/stm32f10x_wwdg.h
new file mode 100644
index 0000000..bdfa177
--- /dev/null
+++ b/st_fw_lib/inc/stm32f10x_wwdg.h
@@ -0,0 +1,115 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the WWDG firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/core_cm3.c b/st_fw_lib/src/core_cm3.c
new file mode 100644
index 0000000..fcff0d1
--- /dev/null
+++ b/st_fw_lib/src/core_cm3.c
@@ -0,0 +1,784 @@
+/**************************************************************************//**
+ * @file core_cm3.c
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version V1.30
+ * @date 30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+ clrex
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ __ASM("rev16 r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, psp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, msp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief Return the Control Register value
+*
+* @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ uint8_t result=0;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ uint16_t result=0;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
diff --git a/st_fw_lib/src/misc.c b/st_fw_lib/src/misc.c
new file mode 100644
index 0000000..c0a5e11
--- /dev/null
+++ b/st_fw_lib/src/misc.c
@@ -0,0 +1,225 @@
+/**
+ ******************************************************************************
+ * @file misc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @defgroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_adc.c b/st_fw_lib/src/stm32f10x_adc.c
new file mode 100644
index 0000000..8155dc9
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_adc.c
@@ -0,0 +1,1307 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the ADC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @defgroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set ((uint32_t)0x00000001)
+#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set ((uint32_t)0x00000100)
+#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set ((uint32_t)0x00300000)
+#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS ((uint32_t)0x4001244C)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ if (ADCx == ADC1)
+ {
+ /* Enable ADC1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+ }
+ else if (ADCx == ADC2)
+ {
+ /* Enable ADC2 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+ /* Release ADC2 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+ }
+ else
+ {
+ if (ADCx == ADC3)
+ {
+ /* Enable ADC3 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+ /* Release ADC3 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+ * the configuration information for the specified ADC peripheral.
+ * @retval None
+ */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+ /*---------------------------- ADCx CR1 Configuration -----------------*/
+ /* Get the ADCx CR1 value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CR1_CLEAR_Mask;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to ADC_Mode value */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+ /* Write to ADCx CR1 */
+ ADCx->CR1 = tmpreg1;
+
+ /*---------------------------- ADCx CR2 Configuration -----------------*/
+ /* Get the ADCx CR2 value */
+ tmpreg1 = ADCx->CR2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CR2_CLEAR_Mask;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to ADC_DataAlign value */
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+ /* Set CONT bit according to ADC_ContinuousConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+ /* Write to ADCx CR2 */
+ ADCx->CR2 = tmpreg1;
+
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+ /* Clear L bits */
+ tmpreg1 &= SQR1_CLEAR_Mask;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfChannel value */
+ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* Initialize the ADC_Mode member */
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+ /* initialize the ADC_ScanConvMode member */
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+ /* Initialize the ADC_ContinuousConvMode member */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+ /* Initialize the ADC_ExternalTrigConv member */
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+ /* Initialize the ADC_DataAlign member */
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+ /* Initialize the ADC_NbrOfChannel member */
+ ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ADON bit to wake up the ADC from power down mode */
+ ADCx->CR2 |= CR2_ADON_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CR2 &= CR2_ADON_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.
+ * Note: ADC2 hasn't a DMA capability.
+ * @param NewState: new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CR2 |= CR2_DMA_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CR2 &= CR2_DMA_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @param NewState: new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CR1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CR1 &= (~(uint32_t)itmask);
+ }
+}
+
+/**
+ * @brief Resets the selected ADC calibration registers.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Resets the selected ADC calibration registers */
+ ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC reset calibration registers status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC reset calibration registers (SET or RESET).
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of RSTCAL bit */
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+ {
+ /* RSTCAL bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* RSTCAL bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the RSTCAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Enable the selected ADC calibration process */
+ ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of SWSTART bit */
+ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+ {
+ /* SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Number: specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ * @retval None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CR1 |= CR1_DISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CR1 &= CR1_DISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_REGULAR_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CR2 |= CR2_EXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t) ADCx->DR;
+}
+
+/**
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ * @retval The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+ /* Return the dual mode conversion value */
+ return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CR1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CR1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CR1 |= CR1_JDISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CR1 &= CR1_JDISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+ /* Clear the old external event selection for injected group */
+ tmpreg &= CR2_JEXTSEL_Reset;
+ /* Set the external event selection for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of JSWSTART bit */
+ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+ {
+ /* JSWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JSWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JSWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_INJECTED_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Get JL value: Number = JL+1 */
+ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Length: The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ * @retval None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Clear the old injected sequnence lenght JL bits */
+ tmpreg1 &= JSQR_JL_Reset;
+ /* Set the injected sequnence lenght JL bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @param Offset: the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDR_Offset;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+ * @retval None
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpreg &= CR1_AWDMode_Reset;
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+ uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->HTR = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->LTR = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= CR1_AWDCH_Reset;
+ /* Set the Analog watchdog channel */
+ tmpreg |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param NewState: new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 |= CR2_TSVREFE_Set;
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 &= CR2_TSVREFE_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval None
+ */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval The new state of ADC_IT (SET or RESET).
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval None
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_bkp.c b/st_fw_lib/src/stm32f10x_bkp.c
new file mode 100644
index 0000000..997eecc
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_bkp.c
@@ -0,0 +1,308 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the BKP firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup BKP
+ * @brief BKP driver modules
+ * @{
+ */
+
+/** @defgroup BKP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Defines
+ * @{
+ */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
+
+/* --- CR Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CR_OFFSET (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber 0x01
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber 0x00
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber 0x02
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber 0x09
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber 0x08
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
+#define RTCCR_MASK ((uint16_t)0xFC7F)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup BKP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void BKP_DeInit(void)
+{
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+ * @brief Configures the Tamper Pin active level.
+ * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ * This parameter can be one of the following values:
+ * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+ * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+ * @retval None
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+ /* Check the parameters */
+ assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+ *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin activation.
+ * @param NewState: new state of the Tamper Pin activation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin Interrupt.
+ * @param NewState: new state of the Tamper Pin Interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Select the RTC output source to output on the Tamper pin.
+ * @param BKP_RTCOutputSource: specifies the RTC output source.
+ * This parameter can be one of the following values:
+ * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+ * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+ * divided by 64 on the Tamper pin.
+ * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+ * the Tamper pin.
+ * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+ * the Tamper pin.
+ * @retval None
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
+ tmpreg = BKP->RTCCR;
+ /* Clear CCO, ASOE and ASOS bits */
+ tmpreg &= RTCCR_MASK;
+
+ /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+ tmpreg |= BKP_RTCOutputSource;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Sets RTC Clock Calibration value.
+ * @param CalibrationValue: specifies the RTC Clock Calibration value.
+ * This parameter must be a number between 0 and 0x7F.
+ * @retval None
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+ tmpreg = BKP->RTCCR;
+ /* Clear CAL[6:0] bits */
+ tmpreg &= RTCCR_CAL_MASK;
+ /* Set CAL[6:0] bits according to CalibrationValue value */
+ tmpreg |= CalibrationValue;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Writes user data to the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @param Data: data to write
+ * @retval None
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Reads data from the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @retval The content of the specified Data Backup Register
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Event flag is set or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+ return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Event pending flag.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearFlag(void)
+{
+ /* Set CTE bit to clear Tamper Pin Event flag */
+ BKP->CSR |= BKP_CSR_CTE;
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+ */
+ITStatus BKP_GetITStatus(void)
+{
+ return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Interrupt pending bit.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearITPendingBit(void)
+{
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+ BKP->CSR |= BKP_CSR_CTI;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_can.c b/st_fw_lib/src/stm32f10x_can.c
new file mode 100644
index 0000000..ec8e049
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_can.c
@@ -0,0 +1,1415 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the CAN firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @defgroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+
+
+#define CAN_MODE_MASK ((uint32_t) 0x00000003)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @retval None.
+ */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (CANx == CAN1)
+ {
+ /* Enable CAN1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+ /* Release CAN1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+ }
+ else
+ {
+ /* Enable CAN2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+ /* Release CAN2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param CANx: where x can be 1 or 2 to to select the CAN
+ * peripheral.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+ * contains the configuration information for the
+ * CAN peripheral.
+ * @retval Constant indicates initialization succeed which will be
+ * CAN_InitStatus_Failed or CAN_InitStatus_Success.
+ */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+ uint8_t InitStatus = CAN_InitStatus_Failed;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ CANx->MCR |= CAN_MCR_INRQ ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CAN_InitStatus_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitStruct->CAN_NART == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+ ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ InitStatus = CAN_InitStatus_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitStatus_Success ;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+ * structure that contains the configuration
+ * information.
+ * @retval None.
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+ /* Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Filter Deactivation */
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CAN1->FS1R |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CAN1->FA1R |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Fills each CAN_InitStruct member with its default value.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+ * will be initialized.
+ * @retval None.
+ */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitStruct->CAN_TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitStruct->CAN_ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitStruct->CAN_AWUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitStruct->CAN_NART = DISABLE;
+
+ /* Initialize the receive FIFO locked mode */
+ CAN_InitStruct->CAN_RFLM = DISABLE;
+
+ /* Initialize the transmit FIFO priority */
+ CAN_InitStruct->CAN_TXFP = DISABLE;
+
+ /* Initialize the CAN_Mode member */
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
+ /* Initialize the CAN_SJW member */
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+
+ /* Initialize the CAN_BS1 member */
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
+ /* Initialize the CAN_BS2 member */
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
+ /* Initialize the CAN_Prescaler member */
+ CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+ * @brief Select the start bank filter for slave CAN.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
+ * @retval None.
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+
+ /* Enter Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Select the start slave bank */
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+
+ /* Leave Initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCR |= MCR_DBF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCR &= ~MCR_DBF;
+ }
+}
+
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState : Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ * @retval None
+ */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCR |= CAN_MCR_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+ }
+}
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN data.
+ * @retval The number of the mailbox that is used for transmission
+ * or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+ assert_param(IS_CAN_RTR(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxStatus_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Id_Standard)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+ TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+ TxMessage->IDE | \
+ TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
+ ((uint32_t)TxMessage->Data[2] << 16) |
+ ((uint32_t)TxMessage->Data[1] << 8) |
+ ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
+ ((uint32_t)TxMessage->Data[6] << 16) |
+ ((uint32_t)TxMessage->Data[5] << 8) |
+ ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the
+ * CAN peripheral.
+ * @param TransmitMailbox: the number of the mailbox that is used for
+ * transmission.
+ * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
+ * in an other case.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+ break;
+ default:
+ state = CAN_TxStatus_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0): state = CAN_TxStatus_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+ break;
+ default: state = CAN_TxStatus_Failed;
+ break;
+ }
+ return (uint8_t) state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Mailbox: Mailbox number.
+ * @retval None.
+ */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+ break;
+ case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+ break;
+ case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+ break;
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @brief Receives a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage: pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ * @retval None.
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ if (RxMessage->IDE == CAN_Id_Standard)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified FIFO.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None.
+ */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ uint8_t message_pending=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ if (FIFONumber == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+ }
+ else if (FIFONumber == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+
+/**
+ * @brief Select the CAN Operation mode.
+ * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
+ * of @ref CAN_OperatingMode_TypeDef enumeration.
+ * @retval status of the requested mode which can be
+ * - CAN_ModeStatus_Failed CAN failed entering the specific mode
+ * - CAN_ModeStatus_Success CAN Succeed entering the specific mode
+
+ */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeStatus_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+ {
+ /* Request initialisation */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+ {
+ /* Request Sleep mode */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+
+ return (uint8_t) status;
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
+ * other case.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+ uint8_t sleepstatus = CAN_Sleep_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_Sleep_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
+ * other case.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+ uint32_t wait_slak = SLAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WakeUp_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Sleep mode status */
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+ {
+ wait_slak--;
+ }
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WakeUp_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+ uint8_t errorcode=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_IT_TME,
+ * - CAN_IT_FMP0,
+ * - CAN_IT_FF0,
+ * - CAN_IT_FOV0,
+ * - CAN_IT_FMP1,
+ * - CAN_IT_FF1,
+ * - CAN_IT_FOV1,
+ * - CAN_IT_EWG,
+ * - CAN_IT_EPV,
+ * - CAN_IT_LEC,
+ * - CAN_IT_ERR,
+ * - CAN_IT_WKU or
+ * - CAN_IT_SLK.
+ * @param NewState: new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->IER &= ~CAN_IT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to check.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWG
+ * - CAN_FLAG_EPV
+ * - CAN_FLAG_BOF
+ * - CAN_FLAG_RQCP0
+ * - CAN_FLAG_RQCP1
+ * - CAN_FLAG_RQCP2
+ * - CAN_FLAG_FMP1
+ * - CAN_FLAG_FF1
+ * - CAN_FLAG_FOV1
+ * - CAN_FLAG_FMP0
+ * - CAN_FLAG_FF0
+ * - CAN_FLAG_FOV0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @retval The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+
+ if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCP0
+ * - CAN_FLAG_RQCP1
+ * - CAN_FLAG_RQCP2
+ * - CAN_FLAG_FF1
+ * - CAN_FLAG_FOV1
+ * - CAN_FLAG_FF0
+ * - CAN_FLAG_FOV0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @retval None.
+ */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESR = (uint32_t)RESET;
+ }
+ else /* MSR or TSR or RF0R or RF1R */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RF0R = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RF1R = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSR = (uint32_t)(flagtmp);
+ }
+ else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSR = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_IT_TME
+ * - CAN_IT_FMP0
+ * - CAN_IT_FF0
+ * - CAN_IT_FOV0
+ * - CAN_IT_FMP1
+ * - CAN_IT_FF1
+ * - CAN_IT_FOV1
+ * - CAN_IT_WKU
+ * - CAN_IT_SLK
+ * - CAN_IT_EWG
+ * - CAN_IT_EPV
+ * - CAN_IT_BOF
+ * - CAN_IT_LEC
+ * - CAN_IT_ERR
+ * @retval The current state of CAN_IT (SET or RESET).
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ ITStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+
+ /* check the enable interrupt bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_IT)
+ {
+ case CAN_IT_TME:
+ /* Check CAN_TSR_RQCPx bits */
+ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
+ break;
+ case CAN_IT_FMP0:
+ /* Check CAN_RF0R_FMP0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
+ break;
+ case CAN_IT_FF0:
+ /* Check CAN_RF0R_FULL0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
+ break;
+ case CAN_IT_FOV0:
+ /* Check CAN_RF0R_FOVR0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
+ break;
+ case CAN_IT_FMP1:
+ /* Check CAN_RF1R_FMP1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
+ break;
+ case CAN_IT_FF1:
+ /* Check CAN_RF1R_FULL1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
+ break;
+ case CAN_IT_FOV1:
+ /* Check CAN_RF1R_FOVR1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
+ break;
+ case CAN_IT_WKU:
+ /* Check CAN_MSR_WKUI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
+ break;
+ case CAN_IT_SLK:
+ /* Check CAN_MSR_SLAKI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
+ break;
+ case CAN_IT_EWG:
+ /* Check CAN_ESR_EWGF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
+ break;
+ case CAN_IT_EPV:
+ /* Check CAN_ESR_EPVF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
+ break;
+ case CAN_IT_BOF:
+ /* Check CAN_ESR_BOFF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
+ break;
+ case CAN_IT_LEC:
+ /* Check CAN_ESR_LEC bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
+ break;
+ case CAN_IT_ERR:
+ /* Check CAN_MSR_ERRI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
+ break;
+ default :
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_IT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the interrupt pending bit to clear.
+ * - CAN_IT_TME
+ * - CAN_IT_FF0
+ * - CAN_IT_FOV0
+ * - CAN_IT_FF1
+ * - CAN_IT_FOV1
+ * - CAN_IT_WKU
+ * - CAN_IT_SLK
+ * - CAN_IT_EWG
+ * - CAN_IT_EPV
+ * - CAN_IT_BOF
+ * - CAN_IT_LEC
+ * - CAN_IT_ERR
+ * @retval None.
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+ switch (CAN_IT)
+ {
+ case CAN_IT_TME:
+ /* Clear CAN_TSR_RQCPx (rc_w1)*/
+ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
+ break;
+ case CAN_IT_FF0:
+ /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+ CANx->RF0R = CAN_RF0R_FULL0;
+ break;
+ case CAN_IT_FOV0:
+ /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+ CANx->RF0R = CAN_RF0R_FOVR0;
+ break;
+ case CAN_IT_FF1:
+ /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+ CANx->RF1R = CAN_RF1R_FULL1;
+ break;
+ case CAN_IT_FOV1:
+ /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+ CANx->RF1R = CAN_RF1R_FOVR1;
+ break;
+ case CAN_IT_WKU:
+ /* Clear CAN_MSR_WKUI (rc_w1)*/
+ CANx->MSR = CAN_MSR_WKUI;
+ break;
+ case CAN_IT_SLK:
+ /* Clear CAN_MSR_SLAKI (rc_w1)*/
+ CANx->MSR = CAN_MSR_SLAKI;
+ break;
+ case CAN_IT_EWG:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_IT_EPV:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_IT_BOF:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_IT_LEC:
+ /* Clear LEC bits */
+ CANx->ESR = RESET;
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ break;
+ case CAN_IT_ERR:
+ /*Clear LEC bits */
+ CANx->ESR = RESET;
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ default :
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg: specifies the CAN interrupt register to check.
+ * @param It_Bit: specifies the interrupt source bit to check.
+ * @retval The new state of the CAN Interrupt (SET or RESET).
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_IT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_IT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_cec.c b/st_fw_lib/src/stm32f10x_cec.c
new file mode 100644
index 0000000..4dc615f
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_cec.c
@@ -0,0 +1,433 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_cec.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the CEC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_cec.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CEC
+ * @brief CEC driver modules
+ * @{
+ */
+
+/** @defgroup CEC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Defines
+ * @{
+ */
+
+/* ------------ CEC registers bit address in the alias region ----------- */
+#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of PE bit */
+#define CFGR_OFFSET (CEC_OFFSET + 0x00)
+#define PE_BitNumber 0x00
+#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
+
+/* Alias word address of IE bit */
+#define IE_BitNumber 0x01
+#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TSOM bit */
+#define CSR_OFFSET (CEC_OFFSET + 0x10)
+#define TSOM_BitNumber 0x00
+#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
+
+/* Alias word address of TEOM bit */
+#define TEOM_BitNumber 0x01
+#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
+
+#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
+#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CEC peripheral registers to their default reset
+ * values.
+ * @param None
+ * @retval None
+ */
+void CEC_DeInit(void)
+{
+ /* Enable CEC reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
+ /* Release CEC from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
+}
+
+
+/**
+ * @brief Initializes the CEC peripheral according to the specified
+ * parameters in the CEC_InitStruct.
+ * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
+ * contains the configuration information for the specified
+ * CEC peripheral.
+ * @retval None
+ */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
+ assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
+
+ /*---------------------------- CEC CFGR Configuration -----------------*/
+ /* Get the CEC CFGR value */
+ tmpreg = CEC->CFGR;
+
+ /* Clear BTEM and BPEM bits */
+ tmpreg &= CFGR_CLEAR_Mask;
+
+ /* Configure CEC: Bit Timing Error and Bit Period Error */
+ tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
+
+ /* Write to CEC CFGR register*/
+ CEC->CFGR = tmpreg;
+
+}
+
+/**
+ * @brief Enables or disables the specified CEC peripheral.
+ * @param NewState: new state of the CEC peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CEC_Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
+
+ if(NewState == DISABLE)
+ {
+ /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
+ while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
+ {
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the CEC interrupt.
+ * @param NewState: new state of the CEC interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CEC_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Defines the Own Address of the CEC device.
+ * @param CEC_OwnAddress: The CEC own address
+ * @retval None
+ */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+
+ /* Set the CEC own address */
+ CEC->OAR = CEC_OwnAddress;
+}
+
+/**
+ * @brief Sets the CEC prescaler value.
+ * @param CEC_Prescaler: CEC prescaler new value
+ * @retval None
+ */
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
+
+ /* Set the Prescaler value*/
+ CEC->PRES = CEC_Prescaler;
+}
+
+/**
+ * @brief Transmits single data through the CEC peripheral.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void CEC_SendDataByte(uint8_t Data)
+{
+ /* Transmit Data */
+ CEC->TXD = Data ;
+}
+
+
+/**
+ * @brief Returns the most recent received data by the CEC peripheral.
+ * @param None
+ * @retval The received data.
+ */
+uint8_t CEC_ReceiveDataByte(void)
+{
+ /* Receive Data */
+ return (uint8_t)(CEC->RXD);
+}
+
+/**
+ * @brief Starts a new message.
+ * @param None
+ * @retval None
+ */
+void CEC_StartOfMessage(void)
+{
+ /* Starts of new message */
+ *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
+}
+
+/**
+ * @brief Transmits message with or without an EOM bit.
+ * @param NewState: new state of the CEC Tx End Of Message.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CEC_EndOfMessageCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* The data byte will be transmitted with or without an EOM bit*/
+ *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Gets the CEC flag status
+ * @param CEC_FLAG: specifies the CEC flag to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_BTE: Bit Timing Error
+ * @arg CEC_FLAG_BPE: Bit Period Error
+ * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
+ * @arg CEC_FLAG_SBE: Start Bit Error
+ * @arg CEC_FLAG_ACKE: Block Acknowledge Error
+ * @arg CEC_FLAG_LINE: Line Error
+ * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
+ * @arg CEC_FLAG_TEOM: Tx End Of Message
+ * @arg CEC_FLAG_TERR: Tx Error
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message
+ * @arg CEC_FLAG_REOM: Rx End Of Message
+ * @arg CEC_FLAG_RERR: Rx Error
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+ * @retval The new state of CEC_FLAG (SET or RESET)
+ */
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t cecreg = 0, cecbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+
+ /* Get the CEC peripheral base address */
+ cecbase = (uint32_t)(CEC_BASE);
+
+ /* Read flag register index */
+ cecreg = CEC_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ CEC_FLAG &= FLAG_Mask;
+
+ if(cecreg != 0)
+ {
+ /* Flag in CEC ESR Register */
+ CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
+
+ /* Get the CEC ESR register address */
+ cecbase += 0xC;
+ }
+ else
+ {
+ /* Get the CEC CSR register address */
+ cecbase += 0x10;
+ }
+
+ if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
+ {
+ /* CEC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CEC_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the CEC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CEC's pending flags.
+ * @param CEC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg CEC_FLAG_TERR: Tx Error
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message
+ * @arg CEC_FLAG_REOM: Rx End Of Message
+ * @arg CEC_FLAG_RERR: Rx Error
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+ * @retval None
+ */
+void CEC_ClearFlag(uint32_t CEC_FLAG)
+{
+ uint32_t tmp = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+ tmp = CEC->CSR & 0x2;
+
+ /* Clear the selected CEC flags */
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+ * @brief Checks whether the specified CEC interrupt has occurred or not.
+ * @param CEC_IT: specifies the CEC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TERR: Tx Error
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished
+ * @arg CEC_IT_RERR: Rx Error
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished
+ * @retval The new state of CEC_IT (SET or RESET).
+ */
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_GET_IT(CEC_IT));
+
+ /* Get the CEC IT enable bit status */
+ enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
+
+ /* Check the status of the specified CEC interrupt */
+ if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* CEC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CEC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the CEC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CEC's interrupt pending bits.
+ * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg CEC_IT_TERR: Tx Error
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished
+ * @arg CEC_IT_RERR: Rx Error
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished
+ * @retval None
+ */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+ uint32_t tmp = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_GET_IT(CEC_IT));
+
+ tmp = CEC->CSR & 0x2;
+
+ /* Clear the selected CEC interrupt pending bits */
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_crc.c b/st_fw_lib/src/stm32f10x_crc.c
new file mode 100644
index 0000000..6501728
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_crc.c
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the CRC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @defgroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DR).
+ * @param None
+ * @retval None
+ */
+void CRC_ResetDR(void)
+{
+ /* Reset CRC generator */
+ CRC->CR = CRC_CR_RESET;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data: data word(32-bit) to compute its CRC
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+ CRC->DR = Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer: pointer to the buffer containing the data to be computed
+ * @param BufferLength: length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < BufferLength; index++)
+ {
+ CRC->DR = pBuffer[index];
+ }
+ return (CRC->DR);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @param None
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_GetCRC(void)
+{
+ return (CRC->DR);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+ CRC->IDR = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @param None
+ * @retval 8-bit value of the ID register
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+ return (CRC->IDR);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_dac.c b/st_fw_lib/src/stm32f10x_dac.c
new file mode 100644
index 0000000..1cfc71d
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_dac.c
@@ -0,0 +1,571 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the DAC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @defgroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Defines
+ * @{
+ */
+
+/* CR register Mask */
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+ * contains the configuration information for the specified DAC channel.
+ * @retval None
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set WAVEx bits according to DAC_WaveGeneration value */
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the DAC_Trigger member */
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+ /* Initialize the DAC_WaveGeneration member */
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+ /* Initialize the DAC_OutputBuffer member */
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
+ }
+}
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+ * @brief Enables or disables the specified DAC interrupts.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @param NewState: new state of the specified DAC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC interrupts */
+ DAC->CR |= (DAC_IT << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC interrupts */
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+ }
+}
+#endif
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param NewState: new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_Wave: Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_Wave_Noise: noise wave generation
+ * @arg DAC_Wave_Triangle: triangle wave generation
+ * @param NewState: new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ DAC->CR |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R1_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R2_OFFSET + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel
+ * DAC.
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ * @retval None
+ */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_Align_8b_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12RD_OFFSET + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t) DAC_BASE ;
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+ * @brief Checks whether the specified DAC flag is set or not.
+ * @param DAC_Channel: thee selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to check.
+ * This parameter can be only of the following value:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @retval The new state of DAC_FLAG (SET or RESET).
+ */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Check the status of the specified DAC flag */
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+ {
+ /* DAC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channelx's pending flags.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to clear.
+ * This parameter can be of the following value:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @retval None
+ */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Clear the selected DAC flags */
+ DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+ * @brief Checks whether the specified DAC interrupt has occurred or not.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt source to check.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @retval The new state of DAC_IT (SET or RESET).
+ */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Get the DAC_IT enable bit status */
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+
+ /* Check the status of the specified DAC interrupt */
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+ {
+ /* DAC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channelx's interrupt pending bits.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @retval None
+ */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Clear the selected DAC interrupt pending bits */
+ DAC->SR = (DAC_IT << DAC_Channel);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_dbgmcu.c b/st_fw_lib/src/stm32f10x_dbgmcu.c
new file mode 100644
index 0000000..96a8fde
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_dbgmcu.c
@@ -0,0 +1,162 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the DBGMCU firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DBGMCU
+ * @brief DBGMCU driver modules
+ * @{
+ */
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Returns the device revision identifier.
+ * @param None
+ * @retval Device revision identifier
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+ return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @param None
+ * @retval Device identifier
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+ * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
+ * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
+ * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
+ * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
+ * @param NewState: new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->CR |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->CR &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_dma.c b/st_fw_lib/src/stm32f10x_dma.c
new file mode 100644
index 0000000..bf072df
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_dma.c
@@ -0,0 +1,714 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the DMA firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @defgroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Defines
+ * @{
+ */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval None
+ */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
+
+ /* Reset DMAy Channelx control register */
+ DMAy_Channelx->CCR = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAy_Channelx->CNDTR = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAy_Channelx->CPAR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAy_Channelx->CMAR = 0;
+
+ if (DMAy_Channelx == DMA1_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;
+ }
+ else
+ {
+ if (DMAy_Channelx == DMA2_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+ * contains the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+ /* Get the DMAy_Channelx CCR value */
+ tmpreg = DMAy_Channelx->CCR;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+ /* Write to DMAy Channelx CCR */
+ DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+ /* Write to DMAy Channelx CPAR */
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+ /* Write to DMAy Channelx CMAR */
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAy_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAy_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DataNumber: The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAy_Channelx is disabled.
+ * @retval None.
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMAy_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+ {
+ /* DMAy_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAy_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMAy_FLAG: specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval None
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy flags */
+ DMA2->IFCR = DMAy_FLAG;
+ }
+ else
+ {
+ /* Clear the selected DMAy flags */
+ DMA1->IFCR = DMAy_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMAy_IT: specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+ /* Calculate the used DMA */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR;
+ }
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMA_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's interrupt pending bits.
+ * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval None
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA2->IFCR = DMAy_IT;
+ }
+ else
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA1->IFCR = DMAy_IT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_exti.c b/st_fw_lib/src/stm32f10x_exti.c
new file mode 100644
index 0000000..b6290d5
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_exti.c
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the EXTI firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x00000000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->PR = 0x000FFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ * that contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMR & EXTI_Line;
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_flash.c b/st_fw_lib/src/stm32f10x_flash.c
new file mode 100644
index 0000000..cdff9e9
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_flash.c
@@ -0,0 +1,1684 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the FLASH firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_flash.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @defgroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set ((uint32_t)0x00000001)
+#define CR_PG_Reset ((uint32_t)0x00001FFE)
+#define CR_PER_Set ((uint32_t)0x00000002)
+#define CR_PER_Reset ((uint32_t)0x00001FFD)
+#define CR_MER_Set ((uint32_t)0x00000004)
+#define CR_MER_Reset ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set ((uint32_t)0x00000020)
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
+#define CR_STRT_Set ((uint32_t)0x00000040)
+#define CR_LOCK_Set ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask ((uint32_t)0x00000002)
+#define WRP0_Mask ((uint32_t)0x000000FF)
+#define WRP1_Mask ((uint32_t)0x0000FF00)
+#define WRP2_Mask ((uint32_t)0x00FF0000)
+#define WRP3_Mask ((uint32_t)0xFF000000)
+#define OB_USER_BFB2 ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+@code
+
+ This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
+ including the latest STM32F10x_XL density devices.
+
+ STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
+ - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
+ - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
+ While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
+
+ In version V3.3.0, some functions were updated and new ones were added to support
+ STM32F10x_XL devices. Thus some functions manages all devices, while other are
+ dedicated for XL devices only.
+
+ The table below presents the list of available functions depending on the used STM32F10x devices.
+
+ ***************************************************
+ * Legacy functions used for all STM32F10x devices *
+ ***************************************************
+ +----------------------------------------------------------------------------------------------------------------------------------+
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
+ | | devices | devices | |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_SetLatency | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_PrefetchBufferCmd | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |
+ | | | | - For other devices: unlock Bank1 and it is equivalent |
+ | | | | to FLASH_UnlockBank1 function. |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |
+ | | | | - For other devices: lock Bank1 and it is equivalent |
+ | | | | to FLASH_LockBank1 function. |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |
+ | | | | - For other devices: erase a page in Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
+ | | | | - For other devices: erase all pages in Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_EraseOptionBytes | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ProgramOptionByteData | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_EnableWriteProtection | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ReadOutProtection | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_UserOptionByteConfig | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetUserOptionByte | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
+ | | | | - For other devices: enable Bank1's interrupts |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
+ | | | | - For other devices: return Bank1's flag status |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |
+ | | | | - For other devices: clear Bank1's flag |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |
+ | | | | equivalent to FLASH_GetBank1Status function |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |
+ | | | | equivalent to: FLASH_WaitForLastBank1Operation function |
+ +----------------------------------------------------------------------------------------------------------------------------------+
+
+ ************************************************************************************************************************
+ * New functions used for all STM32F10x devices to manage Bank1: *
+ * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
+ * - For other devices, these functions are optional (covered by functions listed above) *
+ ************************************************************************************************************************
+ +----------------------------------------------------------------------------------------------------------------------------------+
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
+ | | devices | devices | |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |
+ +----------------------------------------------------------------------------------------------------------------------------------+
+
+ *****************************************************************************
+ * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
+ *****************************************************************************
+ +----------------------------------------------------------------------------------------------------------------------------------+
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
+ | | devices | devices | |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_LockBank2 | Yes | No | - Lock Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |
+ +----------------------------------------------------------------------------------------------------------------------------------+
+@endcode
+*/
+
+
+/**
+ * @brief Sets the code latency value.
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_Latency: specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+ * @arg FLASH_Latency_1: FLASH One Latency cycle
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles
+ * @retval None
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpreg = FLASH->ACR;
+
+ /* Sets the Latency value */
+ tmpreg &= ACR_LATENCY_Mask;
+ tmpreg |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->ACR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Half cycle flash access.
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+ * This parameter can be one of the following values:
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+ * @retval None
+ */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+
+ /* Enable or disable the Half cycle access */
+ FLASH->ACR &= ACR_HLFCYA_Mask;
+ FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+ * @retval None
+ */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->ACR &= ACR_PRFTBE_Mask;
+ FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
+ * - For all other devices it unlocks Bank1 and it is equivalent
+ * to FLASH_UnlockBank1 function..
+ * @param None
+ * @retval None
+ */
+void FLASH_Unlock(void)
+{
+ /* Authorize the FPEC of Bank1 Access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+
+#ifdef STM32F10X_XL
+ /* Authorize the FPEC of Bank2 Access */
+ FLASH->KEYR2 = FLASH_KEY1;
+ FLASH->KEYR2 = FLASH_KEY2;
+#endif /* STM32F10X_XL */
+}
+/**
+ * @brief Unlocks the FLASH Bank1 Program Erase Controller.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function unlocks Bank1.
+ * - For all other devices it unlocks Bank1 and it is
+ * equivalent to FLASH_Unlock function.
+ * @param None
+ * @retval None
+ */
+void FLASH_UnlockBank1(void)
+{
+ /* Authorize the FPEC of Bank1 Access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Unlocks the FLASH Bank2 Program Erase Controller.
+ * @note This function can be used only for STM32F10X_XL density devices.
+ * @param None
+ * @retval None
+ */
+void FLASH_UnlockBank2(void)
+{
+ /* Authorize the FPEC of Bank2 Access */
+ FLASH->KEYR2 = FLASH_KEY1;
+ FLASH->KEYR2 = FLASH_KEY2;
+
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
+ * - For all other devices it Locks Bank1 and it is equivalent
+ * to FLASH_LockBank1 function.
+ * @param None
+ * @retval None
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
+ FLASH->CR |= CR_LOCK_Set;
+
+#ifdef STM32F10X_XL
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
+ FLASH->CR2 |= CR_LOCK_Set;
+#endif /* STM32F10X_XL */
+}
+
+/**
+ * @brief Locks the FLASH Bank1 Program Erase Controller.
+ * @note this function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function Locks Bank1.
+ * - For all other devices it Locks Bank1 and it is equivalent
+ * to FLASH_Lock function.
+ * @param None
+ * @retval None
+ */
+void FLASH_LockBank1(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
+ FLASH->CR |= CR_LOCK_Set;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Locks the FLASH Bank2 Program Erase Controller.
+ * @note This function can be used only for STM32F10X_XL density devices.
+ * @param None
+ * @retval None
+ */
+void FLASH_LockBank2(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
+ FLASH->CR2 |= CR_LOCK_Set;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Page_Address: The page address to be erased.
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+#ifdef STM32F10X_XL
+ if(Page_Address < FLASH_BANK1_END_ADDRESS)
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR|= CR_PER_Set;
+ FLASH->AR = Page_Address;
+ FLASH->CR|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CR &= CR_PER_Reset;
+ }
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR2|= CR_PER_Set;
+ FLASH->AR2 = Page_Address;
+ FLASH->CR2|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CR2 &= CR_PER_Reset;
+ }
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR|= CR_PER_Set;
+ FLASH->AR = Page_Address;
+ FLASH->CR|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CR &= CR_PER_Reset;
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+#ifdef STM32F10X_XL
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR2 |= CR_MER_Set;
+ FLASH->CR2 |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR2 &= CR_MER_Reset;
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all Bank1 FLASH pages.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function erases all Bank1 pages.
+ * - For all other devices it erases all Bank1 pages and it is equivalent
+ * to FLASH_EraseAllPages function.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Erases all Bank2 FLASH pages.
+ * @note This function can be used only for STM32F10x_XL density devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank2Pages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR2 |= CR_MER_Set;
+ FLASH->CR2 |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR2 &= CR_MER_Reset;
+ }
+ /* Return the Erase Status */
+ return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+ uint16_t rdptmp = RDP_Key;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Get the actual read protection Option Byte value */
+ if(FLASH_GetReadOutProtectionStatus() != RESET)
+ {
+ rdptmp = 0x00;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ /* Restore the last read protection Option Byte value */
+ OB->RDP = (uint16_t)rdptmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+#ifdef STM32F10X_XL
+ if(Address < FLASH_BANK1_END_ADDRESS - 2)
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ }
+ else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ FLASH->CR2 |= CR_PG_Set;
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR2 |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ }
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified address.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+#ifdef STM32F10X_XL
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(Address < FLASH_BANK1_END_ADDRESS)
+ {
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ else
+ {
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR2 |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_Pages: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
+ * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
+ * and FLASH_WRProt_Pages124to127
+ * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
+ * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
+ * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
+ * @arg FLASH_WRProt_AllPages
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTPG_Set;
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 = WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 = WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 = WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 = WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Newstate: new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ if(NewState != DISABLE)
+ {
+ OB->RDP = 0x00;
+ }
+ else
+ {
+ OB->RDP = RDP_Key;
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note This function can be used for all STM32F10x devices.
+ * @param OB_IWDG: Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+
+ OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Configures to boot from Bank1 or Bank2.
+ * @note This function can be used only for STM32F10x_XL density devices.
+ * @param FLASH_BOOT: select the FLASH Bank to boot from.
+ * This parameter can be one of the following values:
+ * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
+ * position and this parameter is selected the device will boot from Bank1(Default).
+ * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
+ * position and this parameter is selected the device will boot from Bank2 or Bank1,
+ * depending on the activation of the bank. The active banks are checked in
+ * the following order: Bank2, followed by Bank1.
+ * The active bank is recognized by the value programmed at the base address
+ * of the respective bank (corresponding to the initial stack pointer value
+ * in the interrupt vector table).
+ * For more information, please refer to AN2606 from www.st.com.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ assert_param(IS_FLASH_BOOT(FLASH_BOOT));
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+
+ if(FLASH_BOOT == FLASH_BOOT_Bank1)
+ {
+ OB->USER |= OB_USER_BFB2;
+ }
+ else
+ {
+ OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+ /* Return the Flash write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
+ for Bank1 and Bank2.
+ * - For other devices it enables or disables the specified FLASH interrupts for Bank1.
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+ * @param NewState: new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+#ifdef STM32F10X_XL
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if((FLASH_IT & 0x80000000) != 0x0)
+ {
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
+ }
+ }
+ else
+ {
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+ }
+#else
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+#endif /* STM32F10X_XL */
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices, this function checks whether the specified
+ * Bank1 or Bank2 flag is set or not.
+ * - For other devices, it checks whether the specified Bank1 flag is
+ * set or not.
+ * @param FLASH_FLAG: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+#ifdef STM32F10X_XL
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+ {
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH_FLAG & 0x80000000) != 0x0)
+ {
+ if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ }
+#else
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+ {
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags
+ * - For other devices, it clears Bank1s pending flags.
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @retval None
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+#ifdef STM32F10X_XL
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+ if((FLASH_FLAG & 0x80000000) != 0x0)
+ {
+ /* Clear the flags */
+ FLASH->SR2 = FLASH_FLAG;
+ }
+ else
+ {
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+ }
+
+#else
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+#endif /* STM32F10X_XL */
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @note This function can be used for all STM32F10x devices, it is equivalent
+ * to FLASH_GetBank1Status function.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Returns the FLASH Bank1 Status.
+ * @note This function can be used for all STM32F10x devices, it is equivalent
+ * to FLASH_GetStatus function.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Returns the FLASH Bank2 Status.
+ * @note This function can be used for STM32F10x_XL density devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetBank2Status(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+#endif /* STM32F10X_XL */
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note This function can be used for all STM32F10x devices,
+ * it is equivalent to FLASH_WaitForLastBank1Operation.
+ * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
+ * to complete or a TIMEOUT to occur.
+ * - For all other devices it waits for a Flash operation to complete
+ * or a TIMEOUT to occur.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetBank1Status();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetBank1Status();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ * @note This function can be used for all STM32F10x devices,
+ * it is equivalent to FLASH_WaitForLastOperation.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetBank1Status();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetBank1Status();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
+ * @note This function can be used only for STM32F10x_XL density devices.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetBank2Status();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
+ {
+ status = FLASH_GetBank2Status();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_fsmc.c b/st_fw_lib/src/stm32f10x_fsmc.c
new file mode 100644
index 0000000..51669ee
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_fsmc.c
@@ -0,0 +1,866 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the FSMC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FSMC
+ * @brief FSMC driver modules
+ * @{
+ */
+
+/** @defgroup FSMC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Defines
+ * @{
+ */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
+ * reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @retval None
+ */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+
+ /* FSMC_Bank1_NORSRAM1 */
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
+ }
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+ else
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
+ }
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval None
+ */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Set the FSMC_Bank2 registers to their reset values */
+ FSMC_Bank2->PCR2 = 0x00000018;
+ FSMC_Bank2->SR2 = 0x00000040;
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC;
+ }
+ /* FSMC_Bank3_NAND */
+ else
+ {
+ /* Set the FSMC_Bank3 registers to their reset values */
+ FSMC_Bank3->PCR3 = 0x00000018;
+ FSMC_Bank3->SR3 = 0x00000040;
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void FSMC_PCCARDDeInit(void)
+{
+ /* Set the FSMC_Bank4 registers to their reset values */
+ FSMC_Bank4->PCR4 = 0x00000018;
+ FSMC_Bank4->SR4 = 0x00000000;
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
+ * parameters in the FSMC_NORSRAMInitStruct.
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+ * structure that contains the configuration information for
+ * the FSMC NOR/SRAM specified Banks.
+ * @retval None
+ */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+ assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
+
+ /* Bank1 NOR/SRAM control register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+ {
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+ }
+
+ /* Bank1 NOR/SRAM timing register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+
+
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+ {
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+ }
+ else
+ {
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC NAND Banks according to the specified
+ * parameters in the FSMC_NANDInitStruct.
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
+ * structure that contains the configuration information for the FSMC
+ * NAND specified Banks.
+ * @retval None
+ */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+ /* Check the parameters */
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+ assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+ PCR_MemoryType_NAND |
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NANDInitStruct->FSMC_ECC |
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* FSMC_Bank2_NAND registers configuration */
+ FSMC_Bank2->PCR2 = tmppcr;
+ FSMC_Bank2->PMEM2 = tmppmem;
+ FSMC_Bank2->PATT2 = tmppatt;
+ }
+ else
+ {
+ /* FSMC_Bank3_NAND registers configuration */
+ FSMC_Bank3->PCR3 = tmppcr;
+ FSMC_Bank3->PMEM3 = tmppmem;
+ FSMC_Bank3->PATT3 = tmppatt;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC PCCARD Bank according to the specified
+ * parameters in the FSMC_PCCARDInitStruct.
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+ * structure that contains the configuration information for the FSMC
+ * PCCARD Bank.
+ * @retval None
+ */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+ FSMC_MemoryDataWidth_16b |
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+}
+
+/**
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Reset NOR/SRAM Init structure parameters values */
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ /* Reset NAND Init structure parameters values */
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Reset PCCARD Init structure parameters values */
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+ }
+ else
+ {
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified NAND Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the PCCARD Memory Bank.
+ * @param NewState: new state of the PCCARD Memory Bank.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the FSMC NAND ECC feature.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC NAND ECC feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Returns the error correction code register value.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval The Error Correction Code (ECC) value.
+ */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+ uint32_t eccval = 0x00000000;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the ECCR2 register value */
+ eccval = FSMC_Bank2->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ eccval = FSMC_Bank3->ECCR3;
+ }
+ /* Return the error correction code value */
+ return(eccval);
+}
+
+/**
+ * @brief Enables or disables the specified FSMC interrupts.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @param NewState: new state of the specified FSMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 |= FSMC_IT;
+ }
+ }
+ else
+ {
+ /* Disable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC flag is set or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
+ * @retval The new state of FSMC_FLAG (SET or RESET).
+ */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ /* Get the flag status */
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC's pending flags.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @retval None
+ */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval The new state of FSMC_IT (SET or RESET).
+ */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ itstatus = tmpsr & FSMC_IT;
+
+ itenable = tmpsr & (FSMC_IT >> 3);
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC's interrupt pending bits.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval None
+ */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_gpio.c b/st_fw_lib/src/stm32f10x_gpio.c
new file mode 100644
index 0000000..457ff11
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_gpio.c
@@ -0,0 +1,650 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the GPIO firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @defgroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* --- MAPR Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber ((u8)0x17)
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
+#define LSB_MASK ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+ }
+ else if (GPIOx == GPIOE)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+ }
+ else if (GPIOx == GPIOF)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+ }
+ else
+ {
+ if (GPIOx == GPIOG)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void GPIO_AFIODeInit(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+ uint32_t tmpreg = 0x00, pinmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+ /* Output mode */
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+ }
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+ /* Configure the eight low port pins */
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+ {
+ tmpreg = GPIOx->CRL;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding low control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+ }
+ else
+ {
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+ }
+ }
+ }
+ }
+ GPIOx->CRL = tmpreg;
+ }
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+ /* Configure the eight high port pins */
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+ {
+ tmpreg = GPIOx->CRH;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));
+ /* Get the port pins position */
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding high control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ }
+ }
+ GPIOx->CRH = tmpreg;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enum values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ * @param GPIO_PinSource: specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmpreg = AFIO->EVCR;
+ /* Clear the PORT[6:4] and PIN[3:0] bits */
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+ tmpreg |= GPIO_PinSource;
+ AFIO->EVCR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param NewState: new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param GPIO_Remap: selects the pin to remap.
+ * This parameter can be one of the following values:
+ * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
+ * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
+ * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
+ * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
+ * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
+ * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
+ * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
+ * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
+ * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
+ * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
+ * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
+ * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
+ * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
+ * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
+ * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
+ * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
+ * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
+ * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
+ * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
+ * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
+ * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
+ * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
+ * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
+ * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
+ * When the SPI3/I2S3 is remapped using this function, the SWJ is configured
+ * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
+ * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
+ * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
+ * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
+ * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
+ * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
+ * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
+ * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
+ * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
+ * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
+ * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
+ * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
+ * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
+ * only for High density Value line devices)
+ * @param NewState: new state of the port pin remapping.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if((GPIO_Remap & 0x80000000) == 0x80000000)
+ {
+ tmpreg = AFIO->MAPR2;
+ }
+ else
+ {
+ tmpreg = AFIO->MAPR;
+ }
+
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+ tmp = GPIO_Remap & LSB_MASK;
+
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+ {
+ tmpreg &= DBGAFR_SWJCFG_MASK;
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+ }
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+ {
+ tmp1 = ((uint32_t)0x03) << tmpmask;
+ tmpreg &= ~tmp1;
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+ else
+ {
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+
+ if (NewState != DISABLE)
+ {
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+ }
+
+ if((GPIO_Remap & 0x80000000) == 0x80000000)
+ {
+ AFIO->MAPR2 = tmpreg;
+ }
+ else
+ {
+ AFIO->MAPR = tmpreg;
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+ * @brief Selects the Ethernet media interface.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+ * This parameter can be one of the following values:
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode
+ * @retval None
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
+
+ /* Configure MII_RMII selection bit */
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_i2c.c b/st_fw_lib/src/stm32f10x_i2c.c
new file mode 100644
index 0000000..4ea321c
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_i2c.c
@@ -0,0 +1,1331 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the I2C firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @defgroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CR1_PE_Set ((uint16_t)0x0001)
+#define CR1_PE_Reset ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CR1_START_Set ((uint16_t)0x0100)
+#define CR1_START_Reset ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set ((uint16_t)0x0200)
+#define CR1_STOP_Reset ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set ((uint16_t)0x0400)
+#define CR1_ACK_Reset ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set ((uint16_t)0x0040)
+#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set ((uint16_t)0x8000)
+#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set ((uint16_t)0x1000)
+#define CR1_PEC_Reset ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set ((uint16_t)0x0020)
+#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set ((uint16_t)0x0010)
+#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
+#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set ((uint16_t)0x0800)
+#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set ((uint16_t)0x1000)
+#define CR2_LAST_Reset ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set ((uint16_t)0x0001)
+#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
+#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CCR_FS_Set ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+ * contains the configuration information for the specified I2C peripheral.
+ * @retval None
+ */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+ uint16_t tmpreg = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksTypeDef rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpreg &= CR2_FREQ_Reset;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreq(&rcc_clocks);
+ pclk1 = rcc_clocks.PCLK1_Frequency;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpreg |= freqrange;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TRISE */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ /* Reset tmpreg value */
+ /* Clear F/S, DUTY and CCR[11:0] bits */
+ tmpreg = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+ /* Test if CCR value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpreg |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+ {
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+ }
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_DutyCycle_16_9;
+ }
+
+ /* Test if CCR value is under 0x1*/
+ if ((result & CCR_CCR_Set) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpreg |= (uint16_t)(result | CCR_FS_Set);
+ /* Set Maximum Rise Time for fast mode */
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+
+ /* Write to I2Cx CCR */
+ I2Cx->CCR = tmpreg;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+ /* Set ACK bit according to I2C_Ack value */
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the I2C_ClockSpeed member */
+ I2C_InitStruct->I2C_ClockSpeed = 5000;
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+ /* Initialize the I2C_DutyCycle member */
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR2 |= CR2_DMAEN_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR2 &= CR2_DMAEN_Reset;
+ }
+}
+
+/**
+ * @brief Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CR2 |= CR2_LAST_Set;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CR2 &= CR2_LAST_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR1 |= CR1_START_Set;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR1 &= CR1_START_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR1 |= CR1_STOP_Set;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR1 &= CR1_STOP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CR1 &= CR1_ACK_Reset;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the 7bit I2C own address2.
+ * @retval None.
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpreg &= OAR2_ADD2_Reset;
+
+ /* Set I2Cx Own address2 */
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CR1 |= CR1_ENGC_Set;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CR1 &= CR1_ENGC_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt mask
+ * @arg I2C_IT_EVT: Event interrupt mask
+ * @arg I2C_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data: Byte to be transmitted..
+ * @retval None
+ */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Write in the DR register the data to be sent */
+ I2Cx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the data in the DR register */
+ return (uint8_t)I2Cx->DR;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address which will be transmitted
+ * @param I2C_Direction: specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_Direction_Transmitter: Transmitter mode
+ * @arg I2C_Direction_Receiver: Receiver mode
+ * @retval None.
+ */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_Direction_Transmitter)
+ {
+ /* Set the address bit0 for read */
+ Address |= OAR1_ADD0_Set;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OAR1_ADD0_Reset;
+ }
+ /* Send the address */
+ I2Cx->DR = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2C_Register: specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_Register_CR1: CR1 register.
+ * @arg I2C_Register_CR2: CR2 register.
+ * @arg I2C_Register_OAR1: OAR1 register.
+ * @arg I2C_Register_OAR2: OAR2 register.
+ * @arg I2C_Register_DR: DR register.
+ * @arg I2C_Register_SR1: SR1 register.
+ * @arg I2C_Register_SR2: SR2 register.
+ * @arg I2C_Register_CCR: CCR register.
+ * @arg I2C_Register_TRISE: TRISE register.
+ * @retval The value of the read register.
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_REGISTER(I2C_Register));
+
+ tmp = (uint32_t) I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CR1 |= CR1_SWRST_Set;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CR1 &= CR1_SWRST_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACKPosition_Next) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition: specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACKPosition_Current: indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
+ * but is intended to be used in I2C mode while I2C_PECPositionConfig()
+ * is intended to used in SMBUS mode.
+ *
+ * @retval None
+ */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACKPosition_Next)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CR1 |= I2C_NACKPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CR1 &= I2C_NACKPosition_Current;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+ * @retval None
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CR1 &= I2C_SMBusAlert_High;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CR1 |= CR1_PEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CR1 &= CR1_PEC_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition: specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
+ * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
+ * is intended to used in I2C mode.
+ *
+ * @retval None
+ */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PECPosition_Next)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CR1 |= I2C_PECPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CR1 &= I2C_PECPosition_Current;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CR1 |= CR1_ENPEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CR1 &= CR1_ENPEC_Reset;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->SR2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CR1 |= CR1_ENARP_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CR1 &= CR1_ENARP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+ * @retval None
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CCR &= I2C_DutyCycle_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CCR |= I2C_DutyCycle_16_9;
+ }
+}
+
+
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (SR1 and SR2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occured.
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the mentioned limitation of I2C_GetFlagStatus() function.
+ * The returned value could be compared to events already defined in the
+ * library (stm32f10x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlagStatus() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ * For detailed description of Events, please refer to section I2C_Events in
+ * stm32f10x_i2c.h file.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT: specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in stm32f10x_i2c.h file.
+ *
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+
+ /* Check whether the last event contains the I2C_EVENT */
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in stm32f10x_i2c.h file.
+ *
+ * @retval The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_Mask;
+
+ if(i2creg != 0)
+ {
+ /* Get the I2Cx SR1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx SR2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx SR2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
+ * second byte of the address in DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+ * register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_IT_PECERR: PEC error in reception flag
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure flag
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_IT_BERR: Bus error flag
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_IT_BTF: Byte transfer finished flag
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
+ * @arg I2C_IT_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_IT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
+
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_Mask;
+
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cxs interrupt pending bits.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure interrupt
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+ * @arg I2C_IT_BERR: Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
+ * byte of the address in I2C_DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_DR register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_iwdg.c b/st_fw_lib/src/stm32f10x_iwdg.c
new file mode 100644
index 0000000..c7cbf7e
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_iwdg.c
@@ -0,0 +1,190 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the IWDG firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @defgroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload ((uint16_t)0xAAAA)
+#define KR_KEY_Enable ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+ * @retval None
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+ * @retval None
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload: specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ * @retval None
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RLR = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going
+ * @retval The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_pwr.c b/st_fw_lib/src/stm32f10x_pwr.c
new file mode 100644
index 0000000..a5a5c57
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_pwr.c
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the PWR firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @defgroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void PWR_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param NewState: new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param NewState: new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+ * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+ * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+ * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+ * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+ * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+ * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+ * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpreg = PWR->CR;
+ /* Clear PLS[7:5] bits */
+ tmpreg &= CR_PLS_MASK;
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+ tmpreg |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param NewState: new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= CR_DS_MASK;
+ /* Set LPDS bit according to PWR_Regulator value */
+ tmpreg |= PWR_Regulator;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @param None
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+ /* Clear Wake-up flag */
+ PWR->CR |= PWR_CR_CWUF;
+ /* Select STANDBY mode */
+ PWR->CR |= PWR_CR_PDDS;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @arg PWR_FLAG_PVDO: PVD Output
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @retval None
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CR |= PWR_FLAG << 2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_rcc.c b/st_fw_lib/src/stm32f10x_rcc.c
new file mode 100644
index 0000000..a29034b
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_rcc.c
@@ -0,0 +1,1470 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the RCC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @defgroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+ /* Alias word address of PLL2ON bit */
+ #define PLL2ON_BitNumber 0x1A
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
+
+ /* Alias word address of PLL3ON bit */
+ #define PLL3ON_BitNumber 0x1C
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+
+#ifndef STM32F10X_CL
+ #define USBPRE_BitNumber 0x16
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+#else
+ #define OTGFSPRE_BitNumber 0x16
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+/* --- CFGR2 Register ---*/
+
+ /* Alias word address of I2S2SRC bit */
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
+ #define I2S2SRC_BitNumber 0x11
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
+
+ /* Alias word address of I2S3SRC bit */
+ #define I2S3SRC_BitNumber 0x12
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
+#define CR_HSEON_Set ((uint32_t)0x00010000)
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
+#else
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
+#endif /* STM32F10X_CL */
+
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RMVF_Set ((uint32_t)0x01000000)
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+/* CFGR2 register bit mask */
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
+#endif
+#ifdef STM32F10X_CL
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
+#endif /* STM32F10X_CL */
+
+/* RCC Flag Mask */
+#define FLAG_Mask ((uint8_t)0x1F)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CFGR register byte 4 (Bits[31:24]) base address */
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
+
+/* BDCR register base address */
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Variables
+ * @{
+ */
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: HSE oscillator OFF
+ * @arg RCC_HSE_ON: HSE oscillator ON
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CR &= CR_HSEON_Reset;
+ /* Reset HSEBYP bit */
+ RCC->CR &= CR_HSEBYP_Reset;
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+ switch(RCC_HSE)
+ {
+ case RCC_HSE_ON:
+ /* Set HSEON bit */
+ RCC->CR |= CR_HSEON_Set;
+ break;
+
+ case RCC_HSE_Bypass:
+ /* Set HSEBYP and HSEON bits */
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @param None
+ * @retval An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+ tmpreg = RCC->CR;
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= CR_HSITRIM_Mask;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
+ * this parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ tmpreg &= CFGR_PLL_Mask;
+ /* Set the PLL configuration bits */
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+/**
+ * @brief Configures the PREDIV1 division factor.
+ * @note
+ * - This function must be used only when the PLL is disabled.
+ * - This function applies only to STM32 Connectivity line and Value line
+ * devices.
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
+ * @note
+ * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+ /* Set the PREDIV1 clock source and division factor */
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+#endif
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the PREDIV2 division factor.
+ * @note
+ * - This function must be used only when both PLL2 and PLL3 are disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV2[3:0] bits */
+ tmpreg &= ~CFGR2_PREDIV2;
+ /* Set the PREDIV2 division factor */
+ tmpreg |= RCC_PREDIV2_Div;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the PLL2 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL2 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL2Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL2MUL;
+ /* Set the PLL2 configuration bits */
+ tmpreg |= RCC_PLL2Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL2.
+ * @note
+ * - The PLL2 can not be disabled if it is used indirectly as system clock
+ * (i.e. it is used as PLL clock entry that is used as System clock).
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
+}
+
+
+/**
+ * @brief Configures the PLL3 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL3 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL3Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL3MUL;
+ /* Set the PLL3 configuration bits */
+ tmpreg |= RCC_PLL3Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL3.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+ tmpreg = RCC->CFGR;
+ /* Clear SW[1:0] bits */
+ tmpreg &= CFGR_SW_Mask;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= CFGR_HPRE_Reset_Mask;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= CFGR_PPRE1_Reset_Mask;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= CFGR_PPRE2_Reset_Mask;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+#ifndef STM32F10X_CL
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ * clock source
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+ * @retval None
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+#else
+/**
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).
+ * This function applies only to STM32 Connectivity line devices.
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
+ * This clock is derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @retval None
+ */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
+
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the ADC clock (ADCCLK).
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
+ * the APB2 clock (PCLK2).
+ * This parameter can be one of the following values:
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+ * @retval None
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+ tmpreg = RCC->CFGR;
+ /* Clear ADCPRE[1:0] bits */
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+ tmpreg |= RCC_PCLK2;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the I2S2 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S2 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
+ * @retval None
+ */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
+}
+
+/**
+ * @brief Configures the I2S3 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S3 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
+ * @retval None
+ */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: LSE oscillator OFF
+ * @arg RCC_LSE_ON: LSE oscillator ON
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Reset LSEBYP bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+ switch(RCC_LSE)
+ {
+ case RCC_LSE_ON:
+ /* Set LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
+ break;
+
+ case RCC_LSE_Bypass:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & CFGR_SWS_Mask;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+ tmp = tmp >> 4;
+ presc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+ tmp = tmp >> 11;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get ADCCLK prescaler */
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+ tmp = tmp >> 14;
+ presc = ADCPrescTable[tmp];
+ /* ADCCLK clock frequency */
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_FSMC
+ * @arg RCC_AHBPeriph_SDIO
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBRSTR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;
+ }
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param NewState: new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO: specifies the clock source to output.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ *
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ /* Perform Byte access to MCO bits to select the MCO source */
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_Mask;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= CSR_RMVF_Set;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_rtc.c b/st_fw_lib/src/stm32f10x_rtc.c
new file mode 100644
index 0000000..f05aef5
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_rtc.c
@@ -0,0 +1,339 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the RTC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/** @defgroup RTC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Defines
+ * @{
+ */
+#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
+#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @param NewState: new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RTC->CRH |= RTC_IT;
+ }
+ else
+ {
+ RTC->CRH &= (uint16_t)~RTC_IT;
+ }
+}
+
+/**
+ * @brief Enters the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_EnterConfigMode(void)
+{
+ /* Set the CNF flag to enter in the Configuration Mode */
+ RTC->CRL |= RTC_CRL_CNF;
+}
+
+/**
+ * @brief Exits from the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_ExitConfigMode(void)
+{
+ /* Reset the CNF flag to exit from the Configuration Mode */
+ RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
+}
+
+/**
+ * @brief Gets the RTC counter value.
+ * @param None
+ * @retval RTC counter value.
+ */
+uint32_t RTC_GetCounter(void)
+{
+ uint16_t tmp = 0;
+ tmp = RTC->CNTL;
+ return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+ * @brief Sets the RTC counter value.
+ * @param CounterValue: RTC counter new value.
+ * @retval None
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+ RTC_EnterConfigMode();
+ /* Set RTC COUNTER MSB word */
+ RTC->CNTH = CounterValue >> 16;
+ /* Set RTC COUNTER LSB word */
+ RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC prescaler value.
+ * @param PrescalerValue: RTC prescaler new value.
+ * @retval None
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_PRESCALER(PrescalerValue));
+
+ RTC_EnterConfigMode();
+ /* Set RTC PRESCALER MSB word */
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+ /* Set RTC PRESCALER LSB word */
+ RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC alarm value.
+ * @param AlarmValue: RTC alarm new value.
+ * @retval None
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+ RTC_EnterConfigMode();
+ /* Set the ALARM MSB word */
+ RTC->ALRH = AlarmValue >> 16;
+ /* Set the ALARM LSB word */
+ RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Gets the RTC divider value.
+ * @param None
+ * @retval RTC Divider value.
+ */
+uint32_t RTC_GetDivider(void)
+{
+ uint32_t tmp = 0x00;
+ tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+ tmp |= RTC->DIVL;
+ return tmp;
+}
+
+/**
+ * @brief Waits until last write operation on RTC registers has finished.
+ * @note This function must be called before any write to RTC registers.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForLastTask(void)
+{
+ /* Loop until RTOFF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+ * are synchronized with RTC APB clock.
+ * @note This function must be called before any read operation after an APB reset
+ * or an APB clock stop.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForSynchro(void)
+{
+ /* Clear RSF flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
+ /* Loop until RSF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG: specifies the flag to check.
+ * This parameter can be one the following values:
+ * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
+ * an APB reset or an APB Clock stop.
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval None
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the corresponding RTC flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_IT: specifies the RTC interrupts sources to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval The new state of the RTC_IT (SET or RESET).
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_IT(RTC_IT));
+
+ bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
+ if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval None
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+
+ /* Clear the corresponding RTC pending bit */
+ RTC->CRL &= (uint16_t)~RTC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_sdio.c b/st_fw_lib/src/stm32f10x_sdio.c
new file mode 100644
index 0000000..bc1719d
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_sdio.c
@@ -0,0 +1,799 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the SDIO firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+/** @defgroup SDIO_Private_TypesDefinitions
+ * @{
+ */
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void SDIO_DeInit(void)
+{
+ SDIO->POWER = 0x00000000;
+ SDIO->CLKCR = 0x00000000;
+ SDIO->ARG = 0x00000000;
+ SDIO->CMD = 0x00000000;
+ SDIO->DTIMER = 0x00000000;
+ SDIO->DLEN = 0x00000000;
+ SDIO->DCTRL = 0x00000000;
+ SDIO->ICR = 0x00C007FF;
+ SDIO->MASK = 0x00000000;
+}
+
+/**
+ * @brief Initializes the SDIO peripheral according to the specified
+ * parameters in the SDIO_InitStruct.
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+ * that contains the configuration information for the SDIO peripheral.
+ * @retval None
+ */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
+
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/
+ /* Get the SDIO CLKCR value */
+ tmpreg = SDIO->CLKCR;
+
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+ tmpreg &= CLKCR_CLEAR_MASK;
+
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+ /* Set BYPASS bit according to SDIO_ClockBypass value */
+ /* Set WIDBUS bits according to SDIO_BusWide value */
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
+
+ /* Write to SDIO CLKCR */
+ SDIO->CLKCR = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_InitStruct member with its default value.
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ /* SDIO_InitStruct members default value */
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+ * @brief Enables or disables the SDIO Clock.
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Sets the power status of the controller.
+ * @param SDIO_PowerState: new state of the Power state.
+ * This parameter can be one of the following values:
+ * @arg SDIO_PowerState_OFF
+ * @arg SDIO_PowerState_ON
+ * @retval None
+ */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+
+ SDIO->POWER &= PWR_PWRCTRL_MASK;
+ SDIO->POWER |= SDIO_PowerState;
+}
+
+/**
+ * @brief Gets the power status of the controller.
+ * @param None
+ * @retval Power status of the controller. The returned value can
+ * be one of the following:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDIO_GetPowerState(void)
+{
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+ * @brief Enables or disables the SDIO interrupts.
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @param NewState: new state of the specified SDIO interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_IT(SDIO_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the SDIO interrupts */
+ SDIO->MASK |= SDIO_IT;
+ }
+ else
+ {
+ /* Disable the SDIO interrupts */
+ SDIO->MASK &= ~SDIO_IT;
+ }
+}
+
+/**
+ * @brief Enables or disables the SDIO DMA request.
+ * @param NewState: new state of the selected SDIO DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Initializes the SDIO Command according to the specified
+ * parameters in the SDIO_CmdInitStruct and send the command.
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
+ * structure that contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+ /* Set the SDIO Argument value */
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+
+/*---------------------------- SDIO CMD Configuration ------------------------*/
+ /* Get the SDIO CMD value */
+ tmpreg = SDIO->CMD;
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+ tmpreg &= CMD_CLEAR_MASK;
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+ /* Set WAITRESP bits according to SDIO_Response value */
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+ /* Set CPSMEN bits according to SDIO_CPSM value */
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+ /* Write to SDIO CMD */
+ SDIO->CMD = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+ /* SDIO_CmdInitStruct members default value */
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+ * @brief Returns command index of last command for which response received.
+ * @param None
+ * @retval Returns the command index of the last command response received.
+ */
+uint8_t SDIO_GetCommandResponse(void)
+{
+ return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+ * @brief Returns response received from the card for the last command.
+ * @param SDIO_RESP: Specifies the SDIO response register.
+ * This parameter can be one of the following values:
+ * @arg SDIO_RESP1: Response Register 1
+ * @arg SDIO_RESP2: Response Register 2
+ * @arg SDIO_RESP3: Response Register 3
+ * @arg SDIO_RESP4: Response Register 4
+ * @retval The Corresponding response register value.
+ */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;
+
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @brief Initializes the SDIO data path according to the specified
+ * parameters in the SDIO_DataInitStruct.
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+ * contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+ /* Set the SDIO Data TimeOut value */
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+ /* Set the SDIO DataLength value */
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/
+ /* Get the SDIO DCTRL value */
+ tmpreg = SDIO->DCTRL;
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+ tmpreg &= DCTRL_CLEAR_MASK;
+ /* Set DEN bit according to SDIO_DPSM value */
+ /* Set DTMODE bit according to SDIO_TransferMode value */
+ /* Set DTDIR bit according to SDIO_TransferDir value */
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+ /* Write to SDIO DCTRL */
+ SDIO->DCTRL = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_DataInitStruct member with its default value.
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ /* SDIO_DataInitStruct members default value */
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @param None
+ * @retval Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCounter(void)
+{
+ return SDIO->DCOUNT;
+}
+
+/**
+ * @brief Read one data word from Rx FIFO.
+ * @param None
+ * @retval Data received
+ */
+uint32_t SDIO_ReadData(void)
+{
+ return SDIO->FIFO;
+}
+
+/**
+ * @brief Write one data word to Tx FIFO.
+ * @param Data: 32-bit data word to write.
+ * @retval None
+ */
+void SDIO_WriteData(uint32_t Data)
+{
+ SDIO->FIFO = Data;
+}
+
+/**
+ * @brief Returns the number of words left to be written to or read from FIFO.
+ * @param None
+ * @retval Remaining number of words.
+ */
+uint32_t SDIO_GetFIFOCount(void)
+{
+ return SDIO->FIFOCNT;
+}
+
+/**
+ * @brief Starts the SD I/O Read Wait operation.
+ * @param NewState: new state of the Start SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Stops the SD I/O Read Wait operation.
+ * @param NewState: new state of the Stop SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+ * This parameter can be:
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+ * @retval None
+ */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode Operation.
+ * @param NewState: new state of SDIO specific operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode suspend command sending.
+ * @param NewState: new state of the SD I/O Mode suspend command.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the command completion signal.
+ * @param NewState: new state of command completion signal.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the CE-ATA interrupt.
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+ * @brief Sends CE-ATA command (CMD61).
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param SDIO_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param SDIO_FLAG: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+
+ SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param SDIO_IT: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's interrupt pending bits.
+ * @param SDIO_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+
+ SDIO->ICR = SDIO_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_spi.c b/st_fw_lib/src/stm32f10x_spi.c
new file mode 100644
index 0000000..4ec65b2
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_spi.c
@@ -0,0 +1,908 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the SPI firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @defgroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPE mask */
+#define CR1_SPE_Set ((uint16_t)0x0040)
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set ((uint16_t)0x2000)
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set ((uint16_t)0x0004)
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select ((uint16_t)0xF7FF)
+#define I2S_Mode_Select ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+ }
+ else
+ {
+ if (SPIx == SPI3)
+ {
+ /* Enable SPI3 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+ /* Release SPI3 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral.
+ * @retval None
+ */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ SPIx->I2SCFGR &= SPI_Mode_Select;
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ * @retval None
+ */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksTypeDef RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+ SPIx->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = SPIx->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if(((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLOCK_SRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S3 */
+ tmp = I2S3_CLOCK_SRC;
+ }
+
+ /* Check the I2S clock source configuration depending on the Device:
+ Only Connectivity line devices have the PLL3 VCO clock */
+#ifdef STM32F10X_CL
+ if((RCC->CFGR2 & tmp) != 0)
+ {
+ /* Get the configuration bits of RCC PLL3 multiplier */
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
+
+ /* Get the value of the PLL3 multiplier */
+ if((tmp > 5) && (tmp < 15))
+ {
+ /* Multiplier is between 8 and 14 (value 15 is forbidden) */
+ tmp += 2;
+ }
+ else
+ {
+ if (tmp == 15)
+ {
+ /* Multiplier is 20 */
+ tmp = 20;
+ }
+ }
+ /* Get the PREDIV2 value */
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
+
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
+ }
+ else
+ {
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+ }
+#else /* STM32F10X_HD */
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+#endif /* STM32F10X_CL */
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the SPI_Direction member */
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ /* initialize the SPI_Mode member */
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+ /* initialize the SPI_DataSize member */
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+ /* Initialize the SPI_CPOL member */
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+ /* Initialize the SPI_CPHA member */
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+ /* Initialize the SPI_NSS member */
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+ /* Initialize the SPI_BaudRatePrescaler member */
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ /* Initialize the SPI_FirstBit member */
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+ /* Initialize the SPI_CRCPolynomial member */
+ SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2S_Mode member */
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+ /* Initialize the I2S_Standard member */
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+ /* Initialize the I2S_DataFormat member */
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+ /* Initialize the I2S_MCLKOutput member */
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+ /* Initialize the I2S_AudioFreq member */
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+ /* Initialize the I2S_CPOL member */
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CR1 &= CR1_SPE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+ uint16_t itpos = 0, itmask = 0 ;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CR2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CR2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CR2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param Data : Data to be transmitted.
+ * @retval None
+ */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Write in the DR register the data to be sent */
+ SPIx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @retval The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the data in the DR register */
+ return SPIx->DR;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+ * @retval None
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CR2 |= CR2_SSOE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CR2 &= CR2_SSOE_Reset;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_DataSize: specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit
+ * @retval None
+ */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+ /* Clear DFF bit */
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+ /* Set new DFF bit value */
+ SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CR1 |= CR1_CRCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CR1 &= CR1_CRCEN_Reset;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRC: specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_Tx: Selects Tx CRC register
+ * @arg SPI_CRC_Rx: Selects Rx CRC register
+ * @retval The selected CRC register value..
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_Rx)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->TXCRCR;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->RXCRCR;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPR;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction
+ * @arg SPI_Direction_Rx: Selects Rx receive direction
+ * @retval None
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));
+ if (SPI_Direction == SPI_Direction_Tx)
+ {
+ /* Set the Tx only mode */
+ SPIx->CR1 |= SPI_Direction_Tx;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CR1 &= SPI_Direction_Rx;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.
+ * @arg SPI_FLAG_MODF: Mode Fault flag.
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.
+ * @arg I2S_FLAG_UDR: Underrun Error flag.
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.
+ * @arg SPI_IT_MODF: Mode Fault interrupt.
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.
+ * @arg I2S_IT_UDR: Underrun Error interrupt.
+ * @retval The new state of SPI_I2S_IT (SET or RESET).
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CR2 & itmask) ;
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR interrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
+ * the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->SR = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_tim.c b/st_fw_lib/src/stm32f10x_tim.c
new file mode 100644
index 0000000..bfb4dd1
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_tim.c
@@ -0,0 +1,2890 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the TIM firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @defgroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_Mask ((uint16_t)0x00FF)
+#define CCMR_Offset ((uint16_t)0x0018)
+#define CCER_CCE_Set ((uint16_t)0x0001)
+#define CCER_CCNE_Set ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM9)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
+ }
+ else if (TIMx == TIM10)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
+ }
+ else if (TIMx == TIM11)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
+ }
+ else if (TIMx == TIM12)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
+ }
+ else if (TIMx == TIM13)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
+ }
+ else if (TIMx == TIM14)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
+ }
+ else if (TIMx == TIM15)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
+ }
+ else if (TIMx == TIM16)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
+ }
+ else
+ {
+ if (TIMx == TIM17)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
+ * @retval None
+ */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ uint16_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+ tmpcr1 = TIMx->CR1;
+
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
+ (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+ }
+
+ if((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler and the Repetition counter
+ values immediately */
+ TIMx->EGR = TIM_PSCReloadMode_Immediate;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
+ (TIMx == TIM16)|| (TIMx == TIM17))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+ * the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ }
+ else
+ {
+ assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+ {
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* TI3 Configuration */
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* TI4 Configuration */
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+ {
+ icoppositepolarity = TIM_ICPolarity_Falling;
+ }
+ else
+ {
+ icoppositepolarity = TIM_ICPolarity_Rising;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+ {
+ icoppositeselection = TIM_ICSelection_IndirectTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_ICSelection_DirectTI;
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI2 Configuration */
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI1 Configuration */
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval None
+ */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+ * @param NewState: new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= TIM_CR1_CEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BDTR |= TIM_BDTR_MOE;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+ * TIM_IT_CC2 or TIM_IT_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_EventSource: specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EventSource_Update: Timer update Event source
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM: Timer COM event source
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source
+ * @arg TIM_EventSource_Break: Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
+ * the TIM peripheral.
+ * @param TIM_DMABase: DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+ * TIM_DMABase_DCR.
+ * @param TIM_DMABurstLength: DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * @retval None
+ */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
+ * to select the TIM peripheral.
+ * @param TIM_DMASource: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_Update: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST9_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DIER |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
+ * to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ITRSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @param TIM_TS_ITR0: Internal Trigger 0
+ * @param TIM_TS_ITR1: Internal Trigger 1
+ * @param TIM_TS_ITR2: Internal Trigger 2
+ * @param TIM_TS_ITR3: Internal Trigger 3
+ * @retval None
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+ * @param TIM_ICPolarity: specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param ICFilter : specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ * @retval None
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert_param(IS_TIM_IC_FILTER(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SlaveMode_External1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+ tmpsmcr |= TIM_TS_ETRF;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= TIM_SMCR_ECE;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCR_ETR_Mask;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param Prescaler: specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+ * @retval None
+ */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CounterMode: specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+ * @retval None
+ */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+ uint16_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+ tmpcr1 = TIMx->CR1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+ /* Write to TIMx CR1 register */
+ TIMx->CR1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @retval None
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+ * @retval None
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+ * @retval None
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+ * @retval None
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+ * @retval None
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ TIMx->CR1 |= TIM_CR1_ARPE;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CR2 |= TIM_CR2_CCUS;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
+ * the TIM peripheral.
+ * @param NewState: new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CR2 |= TIM_CR2_CCDS;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
+ * to select the TIMx peripheral
+ * @param NewState: new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CR2 |= TIM_CR2_CCPC;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+ * the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+ * the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
+ tmpccer |= TIM_OCPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
+ tmpccer |= TIM_OCNPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCX(TIM_CCx));
+
+ tmp = CCER_CCE_Set << TIM_Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t)~ tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+ * @retval None
+ */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+ tmp = CCER_CCNE_Set << TIM_Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode.
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMode_Timing
+ * @arg TIM_OCMode_Active
+ * @arg TIM_OCMode_Toggle
+ * @arg TIM_OCMode_PWM1
+ * @arg TIM_OCMode_PWM2
+ * @arg TIM_ForcedAction_Active
+ * @arg TIM_ForcedAction_InActive
+ * @retval None
+ */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_OCM(TIM_OCMode));
+
+ tmp = (uint32_t) TIMx;
+ tmp += CCMR_Offset;
+
+ tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp1;
+
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+ {
+ tmp += (TIM_Channel>>1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= TIM_OCMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CR1 |= TIM_CR1_UDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_UpdateSource: specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+ * @retval None
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)
+ {
+ /* Set the URS Bit */
+ TIMx->CR1 |= TIM_CR1_URS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= TIM_CR2_TI1S;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_OPMode: specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMode_Single
+ * @arg TIM_OPMode_Repetitive
+ * @retval None
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
+ /* Configure the OPM Mode */
+ TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_TRGOSource: specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST7_PERIPH(TIMx));
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+ * @retval None
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
+ /* Select the Slave Mode */
+ TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MasterSlaveMode_Disable: No action
+ * @retval None
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param Counter: specifies the Counter register new value.
+ * @retval None
+ */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param Autoreload: specifies the Autoreload register new value.
+ * @retval None
+ */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1: specifies the Capture Compare1 register new value.
+ * @retval None
+ */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param Compare2: specifies the Capture Compare2 register new value.
+ * @retval None
+ */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3: specifies the Capture Compare3 register new value.
+ * @retval None
+ */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4: specifies the Capture Compare4 register new value.
+ * @retval None
+ */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
+ /* Set the IC1PSC value */
+ TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
+ /* Set the IC2PSC value */
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
+ /* Set the IC3PSC value */
+ TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
+ /* Set the IC4PSC value */
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select
+ * the TIM peripheral.
+ * @param TIM_CKD: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+ * @retval None
+ */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
+ /* Set the CKD value */
+ TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @retval Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @retval Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @retval Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @retval Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval None
+ */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_IT: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+ * TIM_IT_CC2 or TIM_IT_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval The new state of the TIM_IT(SET or RESET).
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_IT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_IT: specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM1 update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+ * TIM_IT_CC2 or TIM_IT_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval None
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+ }
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
+ }
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
+ }
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 12);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
+ }
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_usart.c b/st_fw_lib/src/stm32f10x_usart.c
new file mode 100644
index 0000000..e794eae
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_usart.c
@@ -0,0 +1,1058 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the USART firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @defgroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Defines
+ * @{
+ */
+
+#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
+#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
+#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
+
+#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
+
+#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */
+#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */
+#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+ }
+ else
+ {
+ if (USARTx == UART5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART
+ * peripheral.
+ * @retval None
+ */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+ uint32_t tmpreg = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksTypeDef RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear STOP[13:12] bits */
+ tmpreg &= CR2_STOP_CLEAR_Mask;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to USART_StopBits value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = USARTx->CR1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to USART_WordLength value */
+ /* Set PCE and PS bits according to USART_Parity value */
+ /* Set TE and RE bits according to USART_Mode value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+ USART_InitStruct->USART_Mode;
+ /* Write to USART CR1 */
+ USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = USARTx->CR3;
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= CR3_CLEAR_Mask;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+ /* Write to USART CR3 */
+ USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreq(&RCC_ClocksStatus);
+ if (usartxbase == USART1_BASE)
+ {
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+ }
+
+ /* Determine the integer part */
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+ {
+ /* Integer part computing in case Oversampling mode is 8 Samples */
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
+ }
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+ {
+ /* Integer part computing in case Oversampling mode is 16 Samples */
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
+ }
+ tmpreg = (integerdivider / 100) << 4;
+
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+ /* Implement the fractional part in the register */
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+ {
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+ }
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+ {
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+ }
+
+ /* Write to USART BRR */
+ USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->USART_BaudRate = 9600;
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;
+ USART_InitStruct->USART_Parity = USART_Parity_No ;
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to USART_Clock value */
+ /* Set CPOL bit according to USART_CPOL value */
+ /* Set CPHA bit according to USART_CPHA value */
+ /* Set LBCL bit according to USART_LastBit value */
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CR1 register */
+ USARTx->CR1 |= CR1_UE_Set;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */
+ USARTx->CR1 &= CR1_UE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CONFIG_IT(USART_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_IT & IT_Mask;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CR3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USARTs DMA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_DMAReq: specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAReq_Tx: USART DMA transmit request
+ * @arg USART_DMAReq_Rx: USART DMA receive request
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The DMA mode is not available for UART5 except in the STM32
+ * High density value line devices(STM32F10X_HD_VL).
+ * @retval None
+ */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Address: Indicates the address of the USART node.
+ * @retval None
+ */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Address));
+
+ /* Clear the USART address */
+ USARTx->CR2 &= CR2_Address_Mask;
+ /* Set the USART address node */
+ USARTx->CR2 |= USART_Address;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUp: specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+ * @retval None
+ */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));
+
+ USARTx->CR1 &= CR1_WAKE_Mask;
+ USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
+ USARTx->CR1 |= CR1_RWU_Set;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+ USARTx->CR1 &= CR1_RWU_Reset;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+ * @retval None
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CR2 &= CR2_LBDL_Mask;
+ USARTx->CR2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USARTs LIN mode.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ USARTx->CR2 |= CR2_LINEN_Set;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+ USARTx->CR2 &= CR2_LINEN_Reset;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime: specifies the guard time.
+ * @note The guard time bits are not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTPR &= GTPR_LSB_Mask;
+ /* Set the USART guard time */
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler: specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ * @retval None
+ */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTPR &= GTPR_MSB_Mask;
+ /* Set the USART prescaler */
+ USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USARTs Smart Card mode.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ USARTx->CR3 |= CR3_SCEN_Set;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+ USARTx->CR3 &= CR3_SCEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+ USARTx->CR3 |= CR3_NACK_Set;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+ USARTx->CR3 &= CR3_NACK_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the USARTs Half Duplex communication.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ USARTx->CR3 |= CR3_HDSEL_Set;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+ USARTx->CR3 &= CR3_HDSEL_Reset;
+ }
+}
+
+
+/**
+ * @brief Enables or disables the USART's 8x oversampling mode.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART one bit sampling method.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * This function has to be called before calling USART_Init()
+ * function in order to have correct baudrate Divider value.
+ * @retval None
+ */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+ USARTx->CR1 |= CR1_OVER8_Set;
+ }
+ else
+ {
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+ USARTx->CR1 &= CR1_OVER8_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's one bit sampling method.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART one bit sampling method.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+ USARTx->CR3 |= CR3_ONEBITE_Set;
+ }
+ else
+ {
+ /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
+ USARTx->CR3 &= CR3_ONEBITE_Reset;
+ }
+}
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode: specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IrDAMode_LowPower
+ * @arg USART_IrDAMode_Normal
+ * @retval None
+ */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CR3 &= CR3_IRLP_Mask;
+ USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ USARTx->CR3 |= CR3_IREN_Set;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+ USARTx->CR3 &= CR3_IREN_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LBD: LIN Break detection flag
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if (USART_FLAG == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LBD: LIN Break detection flag.
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of USART_IT (SET or RESET).
+ */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_IT & IT_Mask;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ itmask &= USARTx->CR1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ itmask &= USARTx->CR2;
+ }
+ else /* The IT is in CR3 register */
+ {
+ itmask &= USARTx->CR3;
+ }
+
+ bitpos = USART_IT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->SR;
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_IT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->SR = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/src/stm32f10x_wwdg.c b/st_fw_lib/src/stm32f10x_wwdg.c
new file mode 100644
index 0000000..4a901e4
--- /dev/null
+++ b/st_fw_lib/src/stm32f10x_wwdg.c
@@ -0,0 +1,224 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the WWDG firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber 0x09
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_WDGA_Set ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
+#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
+#define BIT_Mask ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void WWDG_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+ * @retval None
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpreg |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ * @retval None
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpreg = WWDG->CFR & CFR_W_Mask;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ * @param None
+ * @retval None
+ */
+void WWDG_EnableIT(void)
+{
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CR = Counter & BIT_Mask;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @param None
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+ return (FlagStatus)(WWDG->SR);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ * @param None
+ * @retval None
+ */
+void WWDG_ClearFlag(void)
+{
+ WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/startup_stm32f10x_hd.s b/st_fw_lib/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..baab28a
--- /dev/null
+++ b/st_fw_lib/startup_stm32f10x_hd.s
@@ -0,0 +1,358 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_hd.s
+;* Author : MCD Application Team
+;* Version : V3.5.0
+;* Date : 11-March-2011
+;* Description : STM32F10x High Density Devices vector table for MDK-ARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the clock system and also configure the external
+;* SRAM mounted on STM3210E-EVAL board to be used as data
+;* memory (optional, to be enabled by user)
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00003000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT FSMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FSMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/st_fw_lib/stm32f10x.h b/st_fw_lib/stm32f10x.h
new file mode 100644
index 0000000..8bf7624
--- /dev/null
+++ b/st_fw_lib/stm32f10x.h
@@ -0,0 +1,8336 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F10x Connectivity line,
+ * High density, High density value line, Medium density,
+ * Medium density Value line, Low density, Low density Value line
+ * and XL-density devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x
+ * @{
+ */
+
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
+ /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
+ /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
+ /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
+ /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
+ /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
+ /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash
+ memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Medium-density value line devices are STM32F100xx microcontrollers where the
+ Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+ the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density value line devices are STM32F100xx microcontrollers where the
+ Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+ the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+ */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_VALUE
+ #ifdef STM32F10X_CL
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_VALUE */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+
+#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+ */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F10X_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+#ifdef STM32F10X_XL
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
+#else
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#endif /* STM32F10X_XL */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+
+#ifdef STM32F10X_LD
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_LD */
+
+#ifdef STM32F10X_LD_VL
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */
+#endif /* STM32F10X_LD_VL */
+
+#ifdef STM32F10X_MD
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_MD */
+
+#ifdef STM32F10X_MD_VL
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */
+#endif /* STM32F10X_MD_VL */
+
+#ifdef STM32F10X_HD
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_HD_VL
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+ DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
+ mapped at position 60 only if the MISC_REMAP bit in
+ the AFIO_MAPR2 register is set) */
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_XL
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+#endif /* STM32F10X_XL */
+
+#ifdef STM32F10X_CL
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
+#endif /* STM32F10X_CL */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value HSE_VALUE
+#define HSI_Value HSI_VALUE
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint16_t DR1;
+ uint16_t RESERVED1;
+ __IO uint16_t DR2;
+ uint16_t RESERVED2;
+ __IO uint16_t DR3;
+ uint16_t RESERVED3;
+ __IO uint16_t DR4;
+ uint16_t RESERVED4;
+ __IO uint16_t DR5;
+ uint16_t RESERVED5;
+ __IO uint16_t DR6;
+ uint16_t RESERVED6;
+ __IO uint16_t DR7;
+ uint16_t RESERVED7;
+ __IO uint16_t DR8;
+ uint16_t RESERVED8;
+ __IO uint16_t DR9;
+ uint16_t RESERVED9;
+ __IO uint16_t DR10;
+ uint16_t RESERVED10;
+ __IO uint16_t RTCCR;
+ uint16_t RESERVED11;
+ __IO uint16_t CR;
+ uint16_t RESERVED12;
+ __IO uint16_t CSR;
+ uint16_t RESERVED13[5];
+ __IO uint16_t DR11;
+ uint16_t RESERVED14;
+ __IO uint16_t DR12;
+ uint16_t RESERVED15;
+ __IO uint16_t DR13;
+ uint16_t RESERVED16;
+ __IO uint16_t DR14;
+ uint16_t RESERVED17;
+ __IO uint16_t DR15;
+ uint16_t RESERVED18;
+ __IO uint16_t DR16;
+ uint16_t RESERVED19;
+ __IO uint16_t DR17;
+ uint16_t RESERVED20;
+ __IO uint16_t DR18;
+ uint16_t RESERVED21;
+ __IO uint16_t DR19;
+ uint16_t RESERVED22;
+ __IO uint16_t DR20;
+ uint16_t RESERVED23;
+ __IO uint16_t DR21;
+ uint16_t RESERVED24;
+ __IO uint16_t DR22;
+ uint16_t RESERVED25;
+ __IO uint16_t DR23;
+ uint16_t RESERVED26;
+ __IO uint16_t DR24;
+ uint16_t RESERVED27;
+ __IO uint16_t DR25;
+ uint16_t RESERVED28;
+ __IO uint16_t DR26;
+ uint16_t RESERVED29;
+ __IO uint16_t DR27;
+ uint16_t RESERVED30;
+ __IO uint16_t DR28;
+ uint16_t RESERVED31;
+ __IO uint16_t DR29;
+ uint16_t RESERVED32;
+ __IO uint16_t DR30;
+ uint16_t RESERVED33;
+ __IO uint16_t DR31;
+ uint16_t RESERVED34;
+ __IO uint16_t DR32;
+ uint16_t RESERVED35;
+ __IO uint16_t DR33;
+ uint16_t RESERVED36;
+ __IO uint16_t DR34;
+ uint16_t RESERVED37;
+ __IO uint16_t DR35;
+ uint16_t RESERVED38;
+ __IO uint16_t DR36;
+ uint16_t RESERVED39;
+ __IO uint16_t DR37;
+ uint16_t RESERVED40;
+ __IO uint16_t DR38;
+ uint16_t RESERVED41;
+ __IO uint16_t DR39;
+ uint16_t RESERVED42;
+ __IO uint16_t DR40;
+ uint16_t RESERVED43;
+ __IO uint16_t DR41;
+ uint16_t RESERVED44;
+ __IO uint16_t DR42;
+ uint16_t RESERVED45;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+#ifndef STM32F10X_CL
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+ CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */
+} CAN_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t CFGR;
+ __IO uint32_t OAR;
+ __IO uint32_t PRES;
+ __IO uint32_t ESR;
+ __IO uint32_t CSR;
+ __IO uint32_t TXD;
+ __IO uint32_t RXD;
+} CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR;
+ __IO uint8_t IDR;
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CR;
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ __IO uint32_t SR;
+#endif
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ uint32_t RESERVED8[567];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ uint32_t RESERVED9[9];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+#ifdef STM32F10X_XL
+ uint32_t RESERVED1[8];
+ __IO uint32_t KEYR2;
+ uint32_t RESERVED2;
+ __IO uint32_t SR2;
+ __IO uint32_t CR2;
+ __IO uint32_t AR2;
+#endif /* STM32F10X_XL */
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2;
+ __IO uint32_t SR2;
+ __IO uint32_t PMEM2;
+ __IO uint32_t PATT2;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR2;
+} FSMC_Bank2_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR3;
+ __IO uint32_t SR3;
+ __IO uint32_t PMEM3;
+ __IO uint32_t PATT3;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR3;
+} FSMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t OAR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OAR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DR;
+ uint16_t RESERVED4;
+ __IO uint16_t SR1;
+ uint16_t RESERVED5;
+ __IO uint16_t SR2;
+ uint16_t RESERVED6;
+ __IO uint16_t CCR;
+ uint16_t RESERVED7;
+ __IO uint16_t TRISE;
+ uint16_t RESERVED8;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR;
+ __IO uint32_t PR;
+ __IO uint32_t RLR;
+ __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+#ifdef STM32F10X_CL
+ __IO uint32_t AHBRSTR;
+ __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ uint32_t RESERVED0;
+ __IO uint32_t CFGR2;
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint16_t CRH;
+ uint16_t RESERVED0;
+ __IO uint16_t CRL;
+ uint16_t RESERVED1;
+ __IO uint16_t PRLH;
+ uint16_t RESERVED2;
+ __IO uint16_t PRLL;
+ uint16_t RESERVED3;
+ __IO uint16_t DIVH;
+ uint16_t RESERVED4;
+ __IO uint16_t DIVL;
+ uint16_t RESERVED5;
+ __IO uint16_t CNTH;
+ uint16_t RESERVED6;
+ __IO uint16_t CNTL;
+ uint16_t RESERVED7;
+ __IO uint16_t ALRH;
+ uint16_t RESERVED8;
+ __IO uint16_t ALRL;
+ uint16_t RESERVED9;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SR;
+ uint16_t RESERVED2;
+ __IO uint16_t DR;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPR;
+ uint16_t RESERVED4;
+ __IO uint16_t RXCRCR;
+ uint16_t RESERVED5;
+ __IO uint16_t TXCRCR;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFGR;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPR;
+ uint16_t RESERVED8;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SMCR;
+ uint16_t RESERVED2;
+ __IO uint16_t DIER;
+ uint16_t RESERVED3;
+ __IO uint16_t SR;
+ uint16_t RESERVED4;
+ __IO uint16_t EGR;
+ uint16_t RESERVED5;
+ __IO uint16_t CCMR1;
+ uint16_t RESERVED6;
+ __IO uint16_t CCMR2;
+ uint16_t RESERVED7;
+ __IO uint16_t CCER;
+ uint16_t RESERVED8;
+ __IO uint16_t CNT;
+ uint16_t RESERVED9;
+ __IO uint16_t PSC;
+ uint16_t RESERVED10;
+ __IO uint16_t ARR;
+ uint16_t RESERVED11;
+ __IO uint16_t RCR;
+ uint16_t RESERVED12;
+ __IO uint16_t CCR1;
+ uint16_t RESERVED13;
+ __IO uint16_t CCR2;
+ uint16_t RESERVED14;
+ __IO uint16_t CCR3;
+ uint16_t RESERVED15;
+ __IO uint16_t CCR4;
+ uint16_t RESERVED16;
+ __IO uint16_t BDTR;
+ uint16_t RESERVED17;
+ __IO uint16_t DCR;
+ uint16_t RESERVED18;
+ __IO uint16_t DMAR;
+ uint16_t RESERVED19;
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR;
+ uint16_t RESERVED0;
+ __IO uint16_t DR;
+ uint16_t RESERVED1;
+ __IO uint16_t BRR;
+ uint16_t RESERVED2;
+ __IO uint16_t CR1;
+ uint16_t RESERVED3;
+ __IO uint16_t CR2;
+ uint16_t RESERVED4;
+ __IO uint16_t CR3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTPR;
+ uint16_t RESERVED6;
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFR;
+ __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
+ #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
+ #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
+ #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
+ #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+
+ #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+ #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+ #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
+ #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#else
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+ #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
+ #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
+ #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
+ #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
+ #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
+ #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
+#endif
+
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
+ #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+ #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
+#endif
+
+#ifdef STM32F10X_XL
+ #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
+ #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
+ #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
+#endif /* STM32F10X_XL */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
+#endif
+
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
+ #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+ #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
+#endif /* STM32F10X_XL */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
+ #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
+ #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
+ #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
+ #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
+ #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
+#endif
+
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
+ #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+ #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
+#endif
+
+#ifdef STM32F10X_XL
+ #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
+ #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
+ #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
+#endif
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
+#endif
+
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+ #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+ #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+ #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
+ #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+ #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
+#endif
+
+#ifdef STM32F10X_HD_VL
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
+#endif /* STM32F10X_XL */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+ #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
+ #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
+ #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+ #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
+ #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
+ #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
+ #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
+ #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
+ #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
+ #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
+ #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
+ #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
+ #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
+ #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
+ #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
+ #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
+ #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
+ #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
+ #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
+ #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
+ #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
+ #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
+
+ #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
+ #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+#endif
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
+#endif
+
+#ifdef STM32F10X_HD_VL
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
+#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */
+#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */
+#endif
+
+#ifdef STM32F10X_XL
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
+#endif
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR1 register *******************/
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR2 register *******************/
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR3 register *******************/
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CCR4 register *******************/
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CCR5 register *******************/
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CCR6 register *******************/
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR7 register *******************/
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_CNDTR1 register ******************/
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR2 register ******************/
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR3 register ******************/
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR4 register ******************/
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR5 register ******************/
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR6 register ******************/
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR7 register ******************/
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR1 register *******************/
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR2 register *******************/
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR3 register *******************/
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR4 register *******************/
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR5 register *******************/
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR6 register *******************/
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR7 register *******************/
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR1 register *******************/
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR2 register *******************/
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR3 register *******************/
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+
+/****************** Bit definition for DMA_CMAR4 register *******************/
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR5 register *******************/
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR6 register *******************/
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR7 register *******************/
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* CEC */
+/* */
+/******************************************************************************/
+/******************** Bit definition for CEC_CFGR register ******************/
+#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
+
+/******************** Bit definition for CEC_OAR register ******************/
+#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
+
+/******************** Bit definition for CEC_PRES register ******************/
+#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
+
+/******************** Bit definition for CEC_ESR register ******************/
+#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
+#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
+#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
+#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
+#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */
+
+/******************** Bit definition for CEC_CSR register ******************/
+#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
+#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
+#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
+#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
+#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
+#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
+
+/******************** Bit definition for CEC_TXD register ******************/
+#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
+
+/******************** Bit definition for CEC_RXD register ******************/
+#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */
+
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */
+#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */
+#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */
+#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */
+#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */
+
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */
+
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */
+
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
+
+#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */
+#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */
+
+#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+#ifdef STM32F10X_CL
+/******************************************************************************/
+/* Ethernet MAC Registers bits definitions */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+ #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32f10x_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/stm32f10x_conf.h b/st_fw_lib/stm32f10x_conf.h
new file mode 100644
index 0000000..b0a0df2
--- /dev/null
+++ b/st_fw_lib/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+ ******************************************************************************
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief Library configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "inc/stm32f10x_adc.h"
+#include "inc/stm32f10x_bkp.h"
+#include "inc/stm32f10x_can.h"
+#include "inc/stm32f10x_cec.h"
+#include "inc/stm32f10x_crc.h"
+#include "inc/stm32f10x_dac.h"
+#include "inc/stm32f10x_dbgmcu.h"
+#include "inc/stm32f10x_dma.h"
+#include "inc/stm32f10x_exti.h"
+#include "inc/stm32f10x_flash.h"
+#include "inc/stm32f10x_fsmc.h"
+#include "inc/stm32f10x_gpio.h"
+#include "inc/stm32f10x_i2c.h"
+#include "inc/stm32f10x_iwdg.h"
+#include "inc/stm32f10x_pwr.h"
+#include "inc/stm32f10x_rcc.h"
+#include "inc/stm32f10x_rtc.h"
+#include "inc/stm32f10x_sdio.h"
+#include "inc/stm32f10x_spi.h"
+#include "inc/stm32f10x_tim.h"
+#include "inc/stm32f10x_usart.h"
+#include "inc/stm32f10x_wwdg.h"
+#include "inc/misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+ Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT 1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function which reports
+ * the name of the source file and the source line number of the call
+ * that failed. If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/system_stm32f10x.c b/st_fw_lib/system_stm32f10x.c
new file mode 100644
index 0000000..1cb760e
--- /dev/null
+++ b/st_fw_lib/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f10x_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+ * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz 24000000
+#else
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
+ STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x4000 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_VALUE <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/st_fw_lib/system_stm32f10x.h b/st_fw_lib/system_stm32f10x.h
new file mode 100644
index 0000000..54bc1ab
--- /dev/null
+++ b/st_fw_lib/system_stm32f10x.h
@@ -0,0 +1,98 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/supwisdom/main.c b/supwisdom/main.c
new file mode 100644
index 0000000..c5fdc97
--- /dev/null
+++ b/supwisdom/main.c
@@ -0,0 +1,53 @@
+//пªÆÕË®¿Ø³ÌÐò
+#include "stdio.h"
+#include "stdlib.h"
+#include "string.h"
+#include "sp_config.h"
+#include "sp_display.h"
+#include "sp_data.h"
+#include "sp_util.h"
+#include "sp_consume.h"
+#include "sp_communicate.h"
+
+static sp_pos_t POS;
+
+int main(void)
+{
+ uint32 tick = 0;
+ uint32 lasttick = 0;
+ sp_cardworkstate_t cardWorkState;
+ MEMCLEAR(&POS, sizeof(POS));
+ MEMCLEAR(&cardWorkState, sizeof(cardWorkState));
+ sp_init();
+ sp_key_init();
+ Delay_ms(DELAY_TIME1s);
+ sp_load_config(&POS);
+
+ show_home(&POS);
+
+ while(1)
+ {
+ tick = sp_get_ticker();
+ sp_feed_dog();
+ sp_valve_control();
+ sp_confirm_paymode(&POS, &cardWorkState);
+ sp_communicate(&POS);
+ if(POS.paymode == PAYMODE_QRCODE)
+ {
+ if(tick - lasttick >= DELAY_TIME100ms)
+ {
+ lasttick = tick;
+ sp_qrcode_handle(&POS, &cardWorkState);
+ }
+ }
+ else
+ {
+ if(tick - lasttick >= DELAY_TIME100ms)
+ {
+ lasttick = tick;
+ sp_test_card_state(&POS, &cardWorkState, tick);
+ sp_card_handle(&POS, &cardWorkState);
+ }
+ }
+ }
+}
diff --git a/supwisdom/sp_card.c b/supwisdom/sp_card.c
new file mode 100644
index 0000000..5c6796a
--- /dev/null
+++ b/supwisdom/sp_card.c
@@ -0,0 +1,98 @@
+#include "../nec_apdu.h"
+#include "sp_des.h"
+#include "sp_constant.h"
+#include "sp_util.h"
+#include "sp_card.h"
+
+static uint8* prcv_buff = NULL;
+static uint8 rcv_len = 0;
+
+uint16 sp_select_sfi(uint8 sfi[2])
+{
+ uint16 ret;
+ uint8 cmd_buff[10];
+
+ cmd_buff[0] = 0x00; //CLA
+ cmd_buff[1] = 0xA4; //INS
+ cmd_buff[2] = 0x00; //P1
+ cmd_buff[3] = 0x00; //P2
+ cmd_buff[4] = 0x02; //Lc
+ memcpy(cmd_buff + 5, sfi, 2);
+
+ ret = card_cpu_exchange(cmd_buff, 2 + 5, 0, &prcv_buff, &rcv_len);
+ if(ret != RETCODE_OK)
+ {
+ return ret;
+ }
+ return 0;
+}
+
+uint16 sp_select_adf(void)
+{
+ uint16 ret;
+ uint8 cmd_buff[] = {"\x00\xA4\x04\x00\x0F\xD1\x56\x00\x00\x01\xBD\xF0\xCA\xCB\xB4\xEF\xD6\xA7\xB8\xB6"};
+ ret = card_cpu_exchange(cmd_buff, sizeof(cmd_buff) - 1, 0, &prcv_buff, &rcv_len);
+ if(ret != RETCODE_OK)
+ {
+ return ret;
+ }
+ return 0;
+}
+
+uint8 sp_card_request(sp_card_t* cardpcd)
+{
+
+ uint8 sak;
+ uint8 snr[8];
+
+ if(!card_request(&sak, snr))
+ {
+ if((sak & 0x20))
+ {
+ if(!card_cpu_mode())
+ {
+ Delay_ms(200);
+ if(sp_select_sfi("\x3f\x00") == 0)
+ {
+ sp_select_adf();
+ cardpcd->cardphyid[0] = snr[3];
+ cardpcd->cardphyid[1] = snr[2];
+ cardpcd->cardphyid[2] = snr[1];
+ cardpcd->cardphyid[3] = snr[0];
+ cardpcd->cardtype = TAG_TYPE_CPU;
+ return 0;
+ }
+ }
+ }
+ else
+ {
+ cardpcd->cardtype = TAG_TYPE_UNKONWN;
+ return 1;
+ }
+ }
+ return 1;
+}
+
+int8 sp_check_cpu_exist(void)
+{
+ return card_cpu_exist();
+}
+
+static uint16 sp_cpu_read(sp_card_t* card)
+{
+ uint16 ret = 0;
+ MEMCLEAR(card->citizen_cardno, sizeof(card->citizen_cardno));
+ MEMCPY(card->expiredate, "\x20\x22\x08\x02", 4);
+ return ret;
+}
+
+uint16 sp_card_read(sp_card_t* card)
+{
+ switch(card->cardtype)
+ {
+ case TAG_TYPE_CPU:
+ return sp_cpu_read(card);
+ default:
+ return 1;
+ }
+}
diff --git a/supwisdom/sp_card.h b/supwisdom/sp_card.h
new file mode 100644
index 0000000..5981cfa
--- /dev/null
+++ b/supwisdom/sp_card.h
@@ -0,0 +1,26 @@
+#ifndef _SP_CARD_H_
+#define _SP_CARD_H_
+
+#include "sp_config.h"
+
+#define SP_FILE09 0x01
+#define SP_FILE10 0x02
+#define SP_FILE12 0x04
+#define SP_FILE15 0x08
+
+#define WATER_RECORD_NO 4
+#define RETCODE_OK 0x9000
+#define RETCODE_INSUFFICIENT 0x9401 //Óà¶î²»×ã
+#define RC_CPU_FILENOTFOUND 0x6A82
+#define RC_CPU_NO_EXTAUTH 0x6982
+#define RC_CPU_FILE_NOT_EXIST 0x6A83
+#define RC_CPU_NOMAC 0x9406
+
+#define CARD_STATUS_OK 0
+
+uint8 sp_card_request(sp_card_t* cardpcd);
+int8 sp_check_cpu_exist(void);
+int8 sp_card_rf_reset(void);
+uint16 sp_card_read(sp_card_t* card);
+
+#endif
diff --git a/supwisdom/sp_communicate.c b/supwisdom/sp_communicate.c
new file mode 100644
index 0000000..7e3ac69
--- /dev/null
+++ b/supwisdom/sp_communicate.c
@@ -0,0 +1,590 @@
+#include "sp_communicate.h"
+#include "sp_util.h"
+#include "sp_flash.h"
+#include "sp_constant.h"
+#include "sp_data.h"
+#include "sp_msgpack.h"
+#include "sp_display.h"
+#include "../sys_hw/drv_usart.h"
+
+static void sp_usart_send(sp_pos_t* pos, sp_protocol_request_t* req)
+{
+ uint8 sendBuff[264];
+ MEMCLEAR(sendBuff, sizeof(sendBuff));
+
+ pos->last_comm_status.command = req->excmd;
+ pos->last_comm_status.sendtime = sp_get_ticker();
+
+ sp_protocol_crc((uint8*)req +2, req->datalen, (uint8*)req +2 +req->datalen);
+ req->datalen += 2;
+ MEMCPY(sendBuff, req, req->datalen+2);
+ usart_send(sendBuff, req->datalen+2);
+}
+
+static uint8 sp_usart_recv(sp_pos_t* pos, sp_protocol_response_t* resp, int32 timeout_ms)
+{
+ uint32 tick = 0;
+ tick = sp_get_ticker();
+ while(1)
+ {
+ MEMCLEAR(resp, sizeof(sp_protocol_response_t));
+ usart_read((u8*)resp, sizeof(sp_protocol_response_t));
+ if(pos->last_comm_status.command == resp->excmd)
+ {
+ MEMCLEAR(&(pos->last_comm_status), sizeof(sp_comm_status_t));
+ return resp->retcode;
+ }
+ if((sp_get_ticker() - tick) >= timeout_ms)
+ {
+ return 1;
+ }
+ }
+}
+uint8 sp_comm_call(sp_pos_t* pos, sp_protocol_request_t* req,
+ sp_protocol_response_t* resp, int32 timeout_ms)
+{
+ sp_usart_send(pos, req);
+ return sp_usart_recv(pos, resp, timeout_ms);
+}
+
+void sp_protocol_req_init(sp_protocol_request_t* req, uint8 command)
+{
+ MEMCLEAR(req,sizeof(sp_protocol_request_t));
+ req->command = PROTOCOL_COMMAND_V2;
+ req->excmd = command;
+ req->flag = PROTOCOL_FLAG_PACK(req->flag);
+ req->flag = PROTOCOL_WITHOUT_MAC(req->flag);
+ req->datalen = 3;
+}
+
+static uint16 sp_confirm_card_authentication(sp_pos_t* pos, sp_card_t* card)
+{
+ uint8 size;
+ uint16 ret;
+ int32 timeout_ms = COMM_WAIT_TIME;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+ sp_protocol_response_t resp;
+
+ disp_hint_info(pos,"ÕýÔÚÉí·ÝÈÏÖ¤ÖÐ",DELAY_TIME2s);
+ ret = sp_usart_recv(pos, &resp, timeout_ms);
+ if(ret)
+ {
+ ret = RC_CARD_AUTHENTICATION;
+ return ret;
+ }
+
+ sp_unpack_init(&unpack,resp.data,resp.datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_INT_WATERLIMIT,field.key))
+ {
+ card->waterlimit = field.val.intval;
+ }
+ else if(IS_KEY(PK_BIN_BILLNO,field.key))
+ {
+ MEMCPY(card->billno, field.val.binval, field.strlen);
+ }
+ else if(IS_KEY(PK_INT_FEEAMOUNT,field.key))
+ {
+ card->feepara.fee_amt = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_FEEUNIT, field.key))
+ {
+ card->feepara.fee_unit = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_FEESTART, field.key))
+ {
+ card->feepara.fee_start = field.val.intval;
+ }
+ }
+ disp_hint_info(pos,"Éí·ÝÈÏÖ¤³É¹¦",DELAY_TIME1s);
+ return 0;
+}
+
+//ºǫ́¶Ô¿¨µÄÉí·ÝÈÏÖ¤
+uint16 sp_card_authentication(sp_pos_t* pos, sp_card_t* card)
+{
+ uint8 ctime[6];
+ sp_protocol_request_t req;
+ cw_pack_context pack;
+ MEMCLEAR(&req, sizeof(req));
+ MEMCLEAR(&pack, sizeof(req));
+ MEMCLEAR(ctime, sizeof ctime);
+
+ sp_get_bcdtime(ctime);
+ sp_protocol_req_init(&req, SP_CMD_CARD_AUTHENTICATION);
+ sp_pack_init(&pack, req.data, sizeof(req.data));
+ cw_pack_map_size(&pack,4);
+
+ sp_pack_put_bin(&pack, PK_BIN_CARDPHYID, card->cardphyid, 4);
+ sp_pack_put_bin(&pack, PK_BIN_CITIZEN_CARDNO, card->citizen_cardno, 12);
+ sp_pack_put_bin(&pack, PK_BIN_DEVPHYID, pos->devphyid, 4);
+ sp_pack_put_bin(&pack, PK_BIN_DEVTIME, ctime, 6);
+
+ req.datalen += sp_pack_length(&pack);
+ sp_usart_send(pos, &req);
+ return sp_confirm_card_authentication(pos, card);
+}
+
+//É豸ǩµ½
+uint16 sp_async_equipment_login(sp_pos_t* pos)
+{
+ sp_protocol_request_t req;
+ cw_pack_context pack;
+ uint8 ctime[6];
+ MEMCLEAR(ctime, sizeof(ctime));
+ pos->heartbeat.heart_status = HEART_SEND;
+
+ sp_get_bcdtime(ctime);
+ sp_protocol_req_init(&req, SP_CMD_LOGIN);
+ sp_pack_init(&pack, req.data, sizeof(req.data));
+ cw_pack_map_size(&pack, 5);
+
+ sp_pack_put_bin(&pack, PK_BIN_DEVPHYID, pos->devphyid, 4);
+ sp_pack_put_bin(&pack, PK_BIN_DEVTIME, ctime, 6);
+ sp_pack_put_str(&pack, PK_STR_DEVTYPE, DEV_TYPE);
+ sp_pack_put_str(&pack, PK_STR_VERSION, PRO_VERSION);
+ sp_pack_put_bin(&pack, PK_BIN_DEVICEKEY, (pos->sysconf.deviceKey), 8);
+
+ req.datalen += sp_pack_length(&pack);
+ sp_usart_send(pos, &req);
+ return 0;
+}
+
+//ÐÄÌøÈ·ÈÏ£¬¼ì²âÍøÂçÊÇ·ñÕý³£
+uint16 sp_async_heartbeat(sp_pos_t* pos)
+{
+ uint8 ctime[6];
+ uint8 unconfirm_transnum = 0;
+ sp_protocol_request_t req;
+ cw_pack_context pack;
+
+ pos->heartbeat.heart_status = HEART_SEND;
+ if(pos->unconfirm_transdtl.transaddr <= pos->last_transdtl.transaddr)
+ {
+ unconfirm_transnum = ((pos->last_transdtl.transaddr - pos->unconfirm_transdtl.transaddr) /
+ sizeof(sp_transdtl_t)) + 1;
+ }
+ else
+ {
+ unconfirm_transnum = 0;
+ }
+ sp_protocol_req_init(&req, SP_CMD_HEARTBEAT);
+ sp_pack_init(&pack, req.data, sizeof(req.data));
+ cw_pack_map_size(&pack, 6);
+
+ sp_get_bcdtime(ctime);
+ sp_pack_put_bin(&pack, PK_BIN_DEVPHYID, pos->devphyid, 4);
+ sp_pack_put_bin(&pack, PK_BIN_DEVTIME, ctime, 6);
+ sp_pack_put_str(&pack, PK_STR_DEVTYPE, DEV_TYPE);
+ sp_pack_put_str(&pack, PK_STR_VERSION, PRO_VERSION);
+ sp_pack_put_int(&pack, PK_INT_UNTRANSCONST, unconfirm_transnum);
+ sp_pack_put_int(&pack, PK_INT_WORKMODE, pos->sysconf.work_mode);
+
+ req.datalen += sp_pack_length(&pack);
+ sp_usart_send(pos, &req);
+ return 0;
+}
+
+static uint16 sp_confirm_qrcode_init(sp_pos_t* pos, sp_card_t* card)
+{
+ uint8 size;
+ uint16 ret;
+ int32 timeout_ms = COMM_WAIT_TIME;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+ sp_protocol_response_t resp;
+
+ ret = sp_usart_recv(pos, &resp, timeout_ms);
+ if(ret)
+ {
+ ret = RC_QRCODE_FAILURE;
+ return ret;
+ }
+
+ sp_unpack_init(&unpack,resp.data,resp.datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_STR_SHORT_URL, field.key))
+ {
+ MEMCPY(card->qrcode.qrcode_url, field.val.strval, field.strlen);
+ }
+ else if(IS_KEY(PK_BIN_BILLNO, field.key))
+ {
+ MEMCPY(card->billno, field.val.binval, field.strlen);
+ }
+ else if(IS_KEY(PK_INT_VAILDTIME, field.key))
+ {
+ card->qrcode.validtime = field.val.intval;
+ }
+ }
+ card->qrcode.starttime = sp_get_ticker();
+ return 0;
+}
+
+//¶þάÂë»ñÈ¡
+uint16 sp_qrcode_init(sp_pos_t* pos, sp_card_t* card)
+{
+ uint8 ctime[6];
+ sp_protocol_request_t req;
+ cw_pack_context pack;
+
+ sp_get_bcdtime(ctime);
+ sp_protocol_req_init(&req, SP_CMD_SHORTURL);
+ sp_pack_init(&pack, req.data, sizeof(req.data));
+ cw_pack_map_size(&pack, 2);
+
+ sp_pack_put_bin(&pack, PK_BIN_DEVPHYID, pos->devphyid, 4);
+ sp_pack_put_bin(&pack, PK_BIN_DEVTIME, ctime, 6);
+
+ req.datalen += sp_pack_length(&pack);
+ sp_usart_send(pos, &req);
+ return sp_confirm_qrcode_init(pos, card);
+}
+
+//¶þάÂëÈ·ÈÏ£¬»ñÈ¡Ö§¸¶×´Ì¬
+static uint16 sp_confirm_qrcode_query(sp_pos_t* pos, sp_card_t* card)
+{
+ uint8 size;
+ uint16 ret;
+ int32 timeout_ms = COMM_WAIT_TIME;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+ sp_protocol_response_t resp;
+
+ ret = sp_usart_recv(pos, &resp, timeout_ms);
+ if(ret)
+ {
+ ret = RC_QRCODE_QUERY_FAIL;
+ return ret;
+ }
+
+ sp_unpack_init(&unpack,resp.data,resp.datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_BIN_BILLNO, field.key))
+ {
+ MEMCPY(card->billno, field.val.binval, field.strlen);
+ }
+ else if(IS_KEY(PK_INT_AUTHSTATUS, field.key))
+ {
+ card->qrcode.authstatus = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_PAYSTATUS, field.key))
+ {
+ card->qrcode.paystatus = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_PAYAMT, field.key))
+ {
+ card->qrcode.paidAmount = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_FEEAMOUNT,field.key))
+ {
+ card->feepara.fee_amt = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_FEEUNIT, field.key))
+ {
+ card->feepara.fee_unit = field.val.intval;
+ }
+ }
+ return resp.retcode;
+}
+
+uint16 sp_qrcode_query(sp_pos_t* pos, sp_card_t* card)
+{
+ uint8 ctime[6];
+ sp_protocol_request_t req;
+ cw_pack_context pack;
+
+ sp_get_bcdtime(ctime);
+ sp_protocol_req_init(&req, SP_CMD_QRCODE_PAY_QUERY);
+ sp_pack_init(&pack, req.data, sizeof(req.data));
+ cw_pack_map_size(&pack, 2);
+
+ sp_pack_put_bin(&pack, PK_BIN_DEVPHYID, pos->devphyid, 4);
+ sp_pack_put_bin(&pack, PK_BIN_BILLNO, card->billno, sizeof(card->billno));
+
+ req.datalen += sp_pack_length(&pack);
+ sp_usart_send(pos, &req);
+ return sp_confirm_qrcode_query(pos, card);
+}
+
+//Á÷Ë®ÉÏ´«
+static uint8 transdtl_account_bilLno[10];
+static uint16 sp_async_upload_transdtl(sp_pos_t* pos, sp_transdtl_t* transdtl)
+{
+ uint8 crc[2];
+ cw_pack_context pack;
+ sp_protocol_request_t req;
+
+ MEMCPY(transdtl_account_bilLno, transdtl->billno, sizeof(transdtl->billno));
+ sp_protocol_req_init(&req, SP_CMD_TRANSDTL_ACCOUNT);
+ sp_pack_init(&pack,req.data,sizeof(req.data));
+ cw_pack_map_size(&pack,10);
+
+ sp_pack_put_bin(&pack, PK_BIN_DEVPHYID, transdtl->devphyid,4);
+ sp_pack_put_bin(&pack, PK_BIN_TRANSDATE, transdtl->transdate,3);
+ sp_pack_put_bin(&pack, PK_BIN_TRANSTIME, transdtl->transtime,3);
+ sp_pack_put_bin(&pack, PK_BIN_BILLNO, transdtl->billno, sizeof(transdtl->billno));
+ sp_pack_put_bin(&pack, PK_BIN_CARDPHYID, transdtl->cardphyid,
+ sizeof(transdtl->cardphyid));
+ sp_pack_put_int(&pack, PK_INT_TRANSWAY, transdtl->transway);
+ sp_pack_put_int(&pack, PK_INT_AMOUNT, transdtl->amount);
+ sp_pack_put_int(&pack, PK_INT_PAYAMT, transdtl->paidAmount);
+ sp_pack_put_int(&pack, PK_INT_FLOWSENSORS, transdtl->flowsensors);
+ sp_pack_put_int(&pack, PK_INT_FLAG, transdtl->transtatus);
+
+ sp_protocol_crc((uint8*)transdtl, sizeof(sp_transdtl_t)-2,crc);
+ req.datalen += sp_pack_length(&pack);
+ sp_usart_send(pos, &req);
+ return 0;
+}
+
+//È·ÈÏÁ÷ˮ״̬
+static uint8 sp_confirm_transdtl_account(sp_protocol_response_t* resp, sp_pos_t* pos)
+{
+ uint8 size;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+
+ if(!resp->retcode)
+ {
+ sp_unpack_init(&unpack, resp->data, resp->datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_BIN_BILLNO,field.key))
+ {
+ if(MEMCMP(field.val.binval, transdtl_account_bilLno,
+ sizeof(transdtl_account_bilLno)) == 0)
+ {
+ pos->unconfirm_transdtl.transaddr+= sizeof(sp_transdtl_t);
+ if(ADDR_TRANSDTL_END <= pos->unconfirm_transdtl.transaddr)
+ {
+ pos->unconfirm_transdtl.transaddr= ADDR_TRANSDTL_BEGIN;
+ }
+ return sp_write_unconfirm_record(pos);
+ }
+ }
+ }
+ }
+ return resp->retcode;
+
+}
+
+static uint8 sp_confirm_heartbeat(sp_protocol_response_t* resp, sp_pos_t* pos)
+{
+ uint8 size;
+ uint8 ctime[6];
+ uint8 systime[7];
+ uint8 login_flag = 0;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+
+ if(resp->retcode)
+ {
+ return resp->retcode;
+ }
+ pos->heartbeat.heart_status = HEART_RECV;
+
+ sp_unpack_init(&unpack,resp->data,resp->datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_BIN_SYSTIME, field.key))
+ {
+ if(field.strlen == 7)
+ {
+ MEMCPY(systime,field.val.binval,7);
+ sp_get_bcdtime(ctime);
+ if(MEMCMP(ctime,systime +1,5) != 0)
+ {
+ if(!sp_check_time_valid(systime +1))
+ {
+ sp_set_bcdtime(systime +1);
+ }
+ }
+ }
+ }
+ else if(IS_KEY(PK_STR_STATUS, field.key))
+ {
+ if(MEMCMP(field.val.strval, "normal", field.strlen) == 0)
+ {
+ login_flag = 1;
+ }
+ else if(MEMCMP(field.val.strval, "logout", field.strlen) == 0)
+ {
+ login_flag = 0;
+ }
+ else if(MEMCMP(field.val.strval, "closed", field.strlen) == 0)
+ {
+ login_flag = 2;
+ }
+ }
+ }
+ sp_save_heartbeat_info(pos, login_flag);
+ return resp->retcode;
+}
+
+uint8 sp_confirm_login(sp_protocol_response_t* resp, sp_pos_t* pos)
+{
+ uint8 size;
+ uint8 ctime[6];
+ uint8 systime[7];
+ uint8 login_flag = 0;
+ uint8 unit = 0;
+ uint8 offline_maxhour = 0;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+
+ MEMCLEAR(ctime, sizeof(ctime));
+ MEMCLEAR(systime, sizeof(systime));
+ if(resp->retcode)
+ {
+ return resp->retcode;
+ }
+ pos->heartbeat.heart_status = HEART_RECV;
+
+ sp_unpack_init(&unpack,resp->data,resp->datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_INT_OFFLINEMAXHOUR, field.key))
+ {
+ offline_maxhour = field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_PULSEINHML, field.key))
+ {
+ unit = field.val.intval;
+ }
+ else if(IS_KEY(PK_BIN_SYSTIME, field.key))
+ {
+ if(field.strlen == 7)
+ {
+ MEMCPY(systime,field.val.binval,7);
+ sp_get_bcdtime(ctime);
+ if(MEMCMP(ctime,systime +1,5) != 0)
+ {
+ if(!sp_check_time_valid(systime +1))
+ {
+ sp_set_bcdtime(systime +1);
+ }
+ }
+ }
+ }
+ }
+
+ login_flag = 1;
+ sp_save_login_info(pos, login_flag, unit, offline_maxhour);
+ return resp->retcode;
+}
+
+static protocol_cmd_t protocol_cmds[] =
+{
+ {SP_CMD_TRANSDTL_ACCOUNT, sp_confirm_transdtl_account},
+ {SP_CMD_HEARTBEAT, sp_confirm_heartbeat},
+ {SP_CMD_LOGIN, sp_confirm_login},
+ {0, NULL}
+};
+
+static uint16 sp_async_confirm_process(sp_pos_t* pos)
+{
+ uint8 ret = 0;
+ uint8 i = 0;
+ int32 timeout_ms = COMM_WAIT_TIME;
+ sp_protocol_response_t resp;
+
+ ret = sp_usart_recv(pos, &resp, timeout_ms);
+ if(ret)
+ {
+ return ret;
+ }
+ while(protocol_cmds[i].func != NULL && protocol_cmds[i].cmd != 0)
+ {
+ if(protocol_cmds[i].cmd == resp.excmd)
+ {
+ return protocol_cmds[i].func(&resp, pos);
+ }
+ ++i;
+ }
+ return 1;
+}
+
+//¼ì²âÉ豸ͨѶ״̬£¬¿ÕÏÐʱ¼ä½øÐÐÁ÷Ë®´¦ÀíµÈ¹¤×÷
+static void sp_check_and_switch_linkstat(sp_pos_t* pos)
+{
+ if(pos->heartbeat.heart_status == HEART_SEND)
+ {
+ //ÒÑ·¢ËÍÐÄÌø£¬Î´ÊÕµ½Ó¦´ð
+ pos->link_stat = 0;
+ pos->heartbeat.heart_status = HEART_INIT;
+ }
+ else if(pos->heartbeat.heart_status == HEART_RECV)
+ {
+ //ÒÑ·¢ËÍÐÄÌø£¬ÊÕµ½Ó¦´ð
+ pos->link_stat = 1;
+ pos->heartbeat.heart_status = HEART_INIT;
+ }
+}
+
+void sp_communicate(sp_pos_t* pos)
+{
+ uint16 ret = 0;
+ uint32 ticker = 0;
+ sp_transdtl_t transdtl;
+
+ if(pos->deviceno == 0)
+ {
+ return;
+ }
+ ticker = sp_get_ticker();
+ if(ticker - pos->last_comm_status.sendtime > COMM_WAIT_TIME)
+ {
+ if(pos->devlogin.last_login_ticker == 0 || pos->devlogin.login_flag == 0
+ || (ticker - pos->devlogin.last_login_ticker) > DELAY_TIME60s*60*24)
+ {
+ pos->devlogin.last_login_ticker = ticker;
+ sp_async_equipment_login(pos);
+ }
+ else if(ticker < pos->heartbeat.last_heartbeat_ticker
+ || pos->heartbeat.last_heartbeat_ticker == 0
+ || (ticker - pos->heartbeat.last_heartbeat_ticker) > DELAY_TIME60s*2)
+ {
+ pos->heartbeat.last_heartbeat_ticker = ticker;
+ sp_async_heartbeat(pos);
+ }
+ else
+ {
+ sp_check_and_switch_linkstat(pos);
+ if(pos->link_stat)
+ {
+ //¼ì²âµ±Ç°ÊÇ·ñÓÐδÉÏ´«µÄÁ÷Ë®
+ if(pos->unconfirm_transdtl.transaddr <= pos->last_transdtl.transaddr)
+ {
+ ret = sp_flash_read((uint32)pos->unconfirm_transdtl.transaddr, (uint8*)&transdtl,
+ sizeof(transdtl));
+ if(!ret)
+ {
+ if(!pos->sysconf.work_mode)
+ {
+ pos->heartbeat.last_heartbeat_ticker = ticker;
+ sp_async_upload_transdtl(pos, &transdtl);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ sp_async_confirm_process(pos);
+}
diff --git a/supwisdom/sp_communicate.h b/supwisdom/sp_communicate.h
new file mode 100644
index 0000000..b8daf77
--- /dev/null
+++ b/supwisdom/sp_communicate.h
@@ -0,0 +1,139 @@
+#ifndef _SP_COMMUNICATE_H_
+#define _SP_COMMUNICATE_H_
+
+#include "sp_config.h"
+
+#define PROTOCOL_COMMAND_V2 0x80
+#define PROTOCOL_WITH_MAC(x) ((x) | 0x80)
+#define PROTOCOL_WITHOUT_MAC(x) ((x) & 0x7F)
+#define PROTOCOL_FLAG_PACK(x) ((x) | 0x01)
+#define PROTOCOL_FLAG_DES_PACK(x) ((x) & 0xFE)
+
+#define PK_BIN_DEVPHYID "a"
+#define PK_INT_CARDNO "b"
+#define PK_BIN_CARDVERNO "c"
+#define PK_INT_DEVSEQNO "d"
+#define PK_STR_VERSION "e"
+#define PK_INT_BLKINDEX "f"
+#define PK_BIN_TRANSDATE "g"
+#define PK_BIN_TRANSTIME "h"
+#define PK_INT_PAYAMT "i"
+#define PK_INT_AMOUNT "j"
+#define PK_INT_FLAG "k"
+#define PK_STR_AVAIABLE "l"
+#define PK_BIN_SYSTIME "m"
+#define PK_STR_UPGRADE "n"
+#define PK_BIN_BLKBITMAP "o"
+#define PK_BIN_FILECRC "p"
+#define PK_INT_FILESIZE "q"
+#define PK_INT_SEQNO "r"
+#define PK_BIN_FILEDATA "s"
+#define PK_INT_MAXSEQNO "t"
+#define PK_INT_SECONDS "u"
+#define PK_INT_CREDIT_TOTAL "v"
+#define PK_INT_CREDIT_PAYCNT "w"
+#define PK_INT_CREDIT_AVAILABAL "x"
+#define PK_INT_CREDIT_NO "y"
+#define PK_BIN_EXPIRE "z"
+#define PK_INT_FEETYPE "A"
+#define PK_BIN_CARDPHYID "B"
+#define PK_STR_STATUS "C"
+#define PK_INT_BALANCE "D"
+#define PK_INT_OFFLINE_FORBID_FLAG "E"
+#define PK_INT_CREDIT_PAYCNT_LACK "F"
+#define PK_INT_ONCETIME_LIMIT "G"
+#define PK_INT_DAYTOTAL_LIMIT "H"
+#define PK_INT_COUNT "J"
+#define PK_BIN_BLKLIST "K"
+#define PK_INT_CREDIT_NEXT_NO "L"
+#define PK_BIN_RANDOM "M"
+#define PK_INT_DEVICENO "N"
+#define PK_BIN_DEVTIME "O"
+#define PK_STR_DEVTYPE "P"
+#define PK_BIN_SAMNO "Q"
+#define PK_INT_PARAVERNO "R"
+#define PK_INT_PARA_GROUPID "S"
+#define PK_INT_FEEVERNO "T"
+#define PK_INT_FEE_CFGID "U"
+#define PK_BIN_WSCLIENT_ID "V"
+#define PK_INT_WSCLIENT_STATUS "W"
+#define PK_INT_FLOWSENSORS "X"
+#define PK_BIN_SOFT_MD5 "Y"
+#define PK_INT_CUSTID "Z"
+#define PK_STR_SHORT_URL "0"
+#define PK_INT_WATERSTATUS "1"
+#define PK_INT_WATERMUCH "2"
+
+#define PK_BIN_BILLNO "3"
+#define PK_INT_TRANSWAY "4"
+#define PK_INT_UNTRANSCONST "5"
+#define PK_BIN_DEVICEKEY "6"
+#define PK_INT_WORKMODE "7"
+#define PK_INT_OFFLINEMAXHOUR "8"
+#define PK_INT_PULSEINHML "9"
+#define PK_BIN_CITIZEN_CARDNO "10"
+#define PK_INT_WATERLIMIT "11"
+#define PK_INT_FEEAMOUNT "12"
+#define PK_INT_FEEUNIT "13"
+#define PK_INT_VAILDTIME "14"
+#define PK_INT_AUTHSTATUS "15"
+#define PK_INT_PAYSTATUS "16"
+#define PK_INT_FEESTART "17"
+
+#define SP_CMD_UPGRADE 0x20 //ÔÚÏßÉý¼¶
+#define SP_CMD_TRANSDTL_ACCOUNT 0x22 //¼ÇÕËÁ÷Ë®
+#define SP_CMD_HEARTBEAT 0x24 //ÐÄÌø
+#define SP_CMD_CARD_AUTHENTICATION 0x26 //¿¨ÔÚÏßÈÏÖ¤
+#define SP_CMD_LOGIN 0x2C //怬
+#define SP_CMD_FACTORY_LINK_TEST 0x2E //¹¤³§Á´Â·²âÊÔ
+#define SP_CMD_SHORTURL 0x28 //»ñÈ¡¶þάÂë¶ÌµØÖ·
+#define SP_CMD_QRCODE_PAY_QUERY 0x2A //¶þάÂëÏû·ÑÈ·ÈÏ
+
+#define IS_PUSH_FLOW(cmd) (0x1&(cmd))
+
+#pragma pack(push)
+#pragma pack(1)
+
+typedef struct
+{
+ uint16 datalen;
+ uint8 command;
+ uint8 excmd; // ÇëÇóÃüÁîÒªÇóżÊý
+ uint8 flag;
+ uint8 data[256];
+} sp_protocol_request_t;
+
+typedef struct
+{
+ uint16 datalen;
+ uint8 command;
+ uint8 excmd; // ÇëÇóÃüÁîÒªÇóżÊý
+ uint8 flag;
+ uint8 retcode;
+ uint8 data[256];
+} sp_protocol_response_t;
+
+#pragma pack(pop)
+
+typedef uint8(* protocol_cmd_func_t)(sp_protocol_response_t* resp, sp_pos_t* pos);
+
+typedef struct
+{
+ uint8 cmd;
+ protocol_cmd_func_t func;
+} protocol_cmd_t;
+
+void sp_communicate(sp_pos_t* pos);
+uint16 sp_card_authentication(sp_pos_t* pos, sp_card_t* card);
+uint16 sp_async_equipment_login(sp_pos_t* pos);
+uint16 sp_async_heartbeat(sp_pos_t* pos);
+uint16 sp_async_upload_transdtl(sp_pos_t* pos, sp_transdtl_t* dtl);
+uint16 sp_qrcode_init(sp_pos_t* pos, sp_card_t* card);
+uint16 sp_qrcode_query(sp_pos_t* pos, sp_card_t* card);
+
+//ͨѶ
+uint8 sp_comm_call(sp_pos_t* pos, sp_protocol_request_t* req,
+ sp_protocol_response_t* resp, int32 timeout_ms);
+void sp_protocol_req_init(sp_protocol_request_t* req, uint8 command);
+#endif
+
diff --git a/supwisdom/sp_config.h b/supwisdom/sp_config.h
new file mode 100644
index 0000000..81f4140
--- /dev/null
+++ b/supwisdom/sp_config.h
@@ -0,0 +1,280 @@
+#ifndef _SP_CONFIG_H
+#define _SP_CONFIG_H
+
+#include "sp_version.h"
+#include "../nec_hardware.h"
+
+#ifndef int8
+#define int8 signed char
+#endif
+
+#ifndef uint8
+#define uint8 unsigned char
+#endif
+
+#ifndef int16
+#define int16 signed short
+#endif
+
+#ifndef uint16
+#define uint16 unsigned short
+#endif
+
+#ifndef int32
+#define int32 signed int
+#endif
+
+#ifndef uint32
+#define uint32 unsigned int
+#endif
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#define DEV_TYPE "G401302"
+#define DEV_OFFLINE_DEFAULT_HOUR 168
+#define DEV_BLKBITMAP_DONE 1984
+#define DEV_MAX_DEVICENO 99
+
+#define PRO_VERSION GIT_VERSION
+#define BUILD_DATE __DATE__ // " " __TIME__
+#ifdef FLOWSENSOR
+#define PURCHASE_FLOWSENSOR 1
+#else
+#define PURCHASE_FLOWSENSOR 0
+#endif
+
+enum
+{
+ SP_KEY_NONE = 0xFF,
+ SP_KEY_0 = 0,
+ SP_KEY_1 = 1,
+ SP_KEY_2 = 2,
+ SP_KEY_3 = 3,
+ SP_KEY_4 = 4,
+ SP_KEY_5 = 5,
+ SP_KEY_6 = 6,
+ SP_KEY_7 = 7,
+ SP_KEY_8 = 8,
+ SP_KEY_9 = 9,
+ SP_KEY_ENTER = 12,
+ SP_KEY_CLEAR = 11
+};
+
+typedef enum
+{
+ PAYMODE_INIT = 0,
+ PAYMODE_CARD = 1,
+ PAYMODE_QRCODE = 2,
+} sp_paymode_e;
+
+#pragma pack(push)
+#pragma pack(1)
+
+typedef struct
+{
+ uint8 command;
+ uint32 sendtime;
+} sp_comm_status_t;
+
+typedef struct
+{
+ uint32 last_heartbeat_ticker;
+ uint8 hwVer[16]; //É豸°æ±¾ºÅ
+ uint8 offlineRecordCount; //δÉÏ´«Á÷Ë®ÊýÁ¿
+ uint8 workMode; //µ±Ç°×´Ì¬£¬0-¿ÕÏУ¬1-ÕýÔÚʹÓã¬9-ÒÉËƹÊÕÏ
+ uint8 heart_status; //ÐÄÌø״̬£¬0-³õʼ»¯£¬1-·¢ËÍ£¬2-½ÓÊÕ
+} sp_heartbeat_t;
+
+typedef struct
+{
+ uint32 last_login_ticker;
+ uint8 login_flag; //0-δǩµ½£¬1-ÒÑÇ©µ½£¬2-×¢Ïú
+ uint8 hwVer[16]; //É豸°æ±¾ºÅ
+ uint8 deviceKey; //É豸¹¤×÷ÃÜÔ¿
+} sp_login_t;
+
+//Ïû·ÑÁ÷Ë®ÐÅÏ¢½á¹¹
+typedef struct
+{
+ uint8 devphyid[4]; //É豸±àºÅ
+ uint8 transdate[3]; //YYDDMM¸ñʽÈÕÆÚ
+ uint8 transtime[3];
+ uint8 billno[10]; //½»Ò׶©µ¥±àºÅ
+ uint8 cardphyid[4]; //¿¨ÎïÀíid
+ uint8 transway; //½»Ò×·½Ê½£¬0-³õʼ£¬1-Ë¢¿¨£¬2-ɨÂë
+ uint8 amount; //ʵ¼ÊÖ§¸¶½ð¶î
+ uint8 paidAmount; //ÒÑÖ§¸¶½ð¶î£¬µ±ÊÇÏÈ¿Û·ÑģʽÏ£¬¼Ç¼ÒÑÖ§¸¶µÄ½ð¶î
+ uint8 flowsensors; //ʵ¼ÊʹÓüÆÁ¿£¨µ¥Î»£º°ÙºÁÉý£©
+ uint8 transtatus; //Á÷ˮ״̬£¬0-³õʼ£¬1-³É¹¦£¬2-ʧ°Ü
+ uint8 reverse[1]; //ռλ·û
+ uint8 crc[2]; //len=32
+} sp_transdtl_t;
+
+typedef struct
+{
+ uint8 offline_work_hour; //ÔÊÐíÍÑ»ú¹¤×÷×î´óСʱ 0 ~ 168 Сʱ£¬0 ±íʾ²»ÏÞÖÆ
+ uint8 deviceno; //»úºÅ
+ uint8 devphyid[4]; //ÎïÀíID
+ uint8 flowsensor_unit; // 100ml¶ÔÓ¦Âö³åÊý
+ uint8 unused[54];
+ uint8 login_flag; //0-δǩµ½£¬1-ÒÑÇ©µ½£¬2-ÒÑ×¢Ïú
+ uint8 crc[2];
+} sp_config_t;
+
+typedef struct
+{
+ uint32 transaddr; //µØÖ·
+ uint16 this_offset; //ҳƫÒÆλ
+ uint8 crc[2]; //len=8
+} sp_last_transdtl_t;
+
+typedef struct
+{
+ uint32 transaddr; //µØÖ·
+ uint16 this_offset; //ҳƫÒÆλ
+ uint8 crc[2]; //len=8
+} sp_unconfirm_transdtl_t;
+
+//Ïû·ÑÐÅÏ¢
+typedef struct
+{
+ uint32 free_used_num; //ÒÑÃâ·ÑʹÓüÆÁ¿(µ¥Î»:100ml)
+
+ uint8 starttime[6]; //Ë¢¿¨Ê±¼ä
+ /*ÏÈ¿Û¿îºó³öË®*/
+ uint16 prepaid_num; //µ¥´Î¿ÉÓüÆÁ¿(µ¥Î»:100ml)
+ uint16 prepaid_amt; //µ¥´ÎÔ¤¸¶½ðÇ®
+
+ uint16 paid_num; //ÀۼƿÉÓüÆÁ¿(µ¥Î»:100ml)
+ uint16 paid_sum; //ÀÛ¼ÆÖ§¸¶½ð¶î
+ uint16 used_num; //ÒÑʹÓüÆÁ¿(µ¥Î»:100ml)
+} sp_purchase_t;
+
+//¶þάÂëÐÅÏ¢
+typedef struct
+{
+ char qrcode_url[32]; ///¶þάÂë¶ÌÂë
+ uint32 starttime; //¶þάÂ뿪ʼʱ¼ä
+ uint32 nowtime; //¶þάÂ뵱ǰʱ¼ä
+ uint32 validtime; //¶þάÂëÓÐЧʱ¼ä
+ uint8 authstatus; //Óû§È·ÈÏ״̬£¨0-δȷÈÏ£¬1-ÒÑÈ·ÈÏ£©
+ uint8 paystatus; //Ö§¸¶×´Ì¬£¨0-´ýÖ§¸¶£¬ 1-ÒÑÖ§¸¶£¬ 2-´ú¿Û£¬3 - ¹Ø±Õ£©
+ uint8 paidAmount; //µ±¶©µ¥ÊÇÒÑÖ§¸¶×´Ì¬£¬·µ»ØÖ§¸¶³É¹¦½ð¶î £¬ ·ñÔòÊÇ 0
+} sp_qrcode_t;
+
+//É豸²ÎÊý
+typedef struct
+{
+ uint8 dev_offline_maxhour; //É豸ÍÑ»ú×î´ó¹¤×÷ʱ¼ä(Сʱ),0-²»ÏÞÖÆ,168-ĬÈÏʱ¼ä
+ uint8 flowsensor_unit; //100ml¶ÔÓ¦Âö³åÊý
+ uint8 hwVer[16]; //É豸°æ±¾ºÅ
+ uint8 deviceKey[8]; //É豸¹¤×÷ÃØÔ¿
+ uint8 work_mode; //É豸¹¤×÷״̬
+} sp_sysconf_t;
+
+
+typedef struct
+{
+ uint8 tag_type;
+ uint8 cur_state;
+ uint8 snr[8];
+ uint32 firsttick; //Ê״ζÁ¿¨Ê±¼ä
+ uint32 lasttick; //×îºó¶Á¿¨Ê±¼ä
+} sp_cardstate_t;
+
+typedef struct
+{
+ uint8 current_state; //µ±Ç°¹¤×÷״̬
+ uint16 errcode;
+ uint32 tick;
+ uint8 last_state; //ÉÏÒ»´Î״̬
+
+ uint8 pause_status; //Óû§Ê¹ÓÃ״̬£¬0--ʹÓÃÖУ¬!0--ÔÝÍ£
+ uint32 pause_tick; //ÔÝͣʱµÄʱ¼ä
+} sp_cardworkstate_t;
+
+//Ë®¿ØÆ÷É豸ÐÅÏ¢
+typedef struct
+{
+ uint8 link_stat; //0--Á´Â·¹¤×÷ÖУ¬1---Á´Â·¿ÉÓÃ
+ uint8 load_para_status; //0--Õý³££¬!0--´íÎó
+ uint8 deviceno;
+ uint8 local_deviceno;
+ uint8 devphyid[4];
+
+ sp_cardstate_t cardState;
+ sp_sysconf_t sysconf;
+ sp_comm_status_t last_comm_status;
+ sp_heartbeat_t heartbeat;
+ sp_login_t devlogin;
+ sp_last_transdtl_t last_transdtl;
+ sp_unconfirm_transdtl_t unconfirm_transdtl;
+
+ sp_paymode_e paymode;
+ sp_purchase_t purchase;
+} sp_pos_t;
+
+//·ÑÂÊÐÅÏ¢
+typedef struct
+{
+ uint8 fee_start; //T°ÙºÁÉý¿ªÊ¼;
+ uint8 fee_unit; //µ¥´Î¿Û·Ñ¿ÉÓÃÁ÷Á¿£¨µ¥Î»:100ml£©
+ uint8 fee_amt; //µ¥´Î¿Û·Ñ½ð¶î£¬ÒÔ·ÖΪµ¥Î»
+} sp_feepara_t;
+
+//¿¨½á¹¹ÐÅÏ¢
+typedef struct
+{
+ uint8 cardphyid[4];
+ uint8 citizen_cardno[12]; //ÊÐÃñºÅ
+ uint8 cardtype;
+ uint8 expiredate[4];
+
+ uint8 waterlimit; //µ¥´Î³öË®ÉÏÏÞ£¨100ml£©
+ uint8 billno[10]; //½»Ò׶©µ¥±àºÅ,BCDÂë
+ sp_qrcode_t qrcode; //¶þάÂë
+ sp_feepara_t feepara;
+} sp_card_t;
+
+#pragma pack(pop)
+
+typedef enum
+{
+ HEART_INIT = 0,
+ HEART_SEND = 1,
+ HEART_RECV = 2
+} sp_heart_status_t;
+
+typedef enum
+{
+ TAG_TYPE_UNKONWN = 0, //δ֪¿¨ÀàÐÍ
+ TAG_TYPE_M1, //M1¿¨
+ TAG_TYPE_CPU //CPU¿¨
+} sp_cardTag_type;
+
+typedef enum
+{
+ STATE_NONE = 0,
+ STATE_EXIST,
+ STATE_ERROR=0xFF
+} sp_cardState_type;
+
+typedef enum
+{
+ CARDWORKSTATUS_NONE = 0,
+ CARDWORKSTATUS_READY,
+ CARDWORKSTATUS_WORKING,
+ CARDWORKSTATUS_WORKING_WITHOUTCARD,
+ CARDWORKSTATUS_PAUSE,
+ CARDWORKSTATUS_STOPPING,
+ CARDWORKSTATUS_STOPPED,
+ CARDWORKSTATUS_TAKEOFF,
+ CARDWORKSTATUS_WORKERROR,
+ CARDWORKSTATUS_FEECARD_WORKING,
+ CARDWORKSTATUS_SET_DEV,
+ CARDWORKSTATUS_ERROR=0xff
+} sp_cardWorkState_type;
+
+#endif
diff --git a/supwisdom/sp_constant.h b/supwisdom/sp_constant.h
new file mode 100644
index 0000000..3081fc0
--- /dev/null
+++ b/supwisdom/sp_constant.h
@@ -0,0 +1,58 @@
+#ifndef _SP_CONSTANT_H_
+#define _SP_CONSTANT_H_
+
+///////////////////////////////////////////////////////////////////////////////
+#define RC_CPU_FILENOTFOUND 0x6A82
+#define RC_CPU_RECORDNOTFOUND 0x6A83
+#define RC_CPU_NOMAC 0x9406
+
+////////////////////////////////////////////////////////////////////////////////
+#define RC_SUCCESS 0 // ³É¹¦
+#define RC_PSAM_ERR 1 //SAM¸´Î»Ê§°Ü
+#define RC_CARD_LOGIN 2 //ÑéÖ¤ÃÜԿʧ°Ü
+#define RC_CARD_READ 3 //¶Á¿¨Ê§°Ü
+#define RC_CARD_WRITE 4 //д¿¨Ê§°Ü
+#define RC_FLASH_ERR 5 //FLASH´íÎó
+#define RC_HARDWARE_ERR 6 //Ó²¼þ¼ÓÔØ´íÎó
+#define RC_FLASH_NO_RIGHT 7 //·Ç¿Éдflash
+
+#define RC_CARD_NORIGHT 11 //¿¨ÎÞȨÏÞ
+#define RC_CARD_EXPIRED 12 //¹ýÆÚ¿¨
+#define RC_CARD_AUTHENTICATION 13 //¿¨ÈÏ֤ʧ°Ü
+#define RC_CARD_LOST 14 //ºÚÃûµ¥¿¨
+#define RC_CARDNO_EXCEPT 17 //¿¨ºÅÒì³£
+#define RC_CARD_TIMEOUT 18 //ʹÓÃʱ¼äÌ«³¤
+#define RC_CARDBAL_EXCEPT 19 //¿¨Óà¶îÒì³£
+#define RC_CARDBAL_LACK 20 //¿¨Óà¶î²»×ã
+
+#define RC_DEVPHYID_NOTSET 21 //É豸µØַδÉèÖÃ
+#define RC_FEERATE_NOTSET 22 //·ÑÂÊδ³õʼ»¯
+#define RC_DEV_OFFLINE_ERROR 23 // É豸ÍÑ»ú¹¤×÷Ì«³¤
+#define RC_FILE09_CRC_ERR 25 ////¼Ç¼CRC´íÎó
+#define RC_FILE10_CRC_ERR 26 //Ë®¿ØÇ®°üCRC´íÎó
+#define RC_CARD_INVALID 27 //ÎÞЧ¿¨
+#define RC_FEENUM_ERROR 28 //·ÑÂʸöÊý´íÎó
+#define RC_NOTSUPPORT 29 //²»Ö§³Ö
+#define RC_NOT_SAME_CARD 30 //²»Í¬¿¨
+
+#define RC_MODE_NOT_SUPPORT 42 //Ïû·Ñģʽ²»Ö§³Ö
+#define RC_UPDPROG_ERR 43 //Éý¼¶Ê§°Ü
+
+#define RC_CONFPARA_CRC_ERR 55 //ÅäÖòÎÊýcrc´íÎó
+#define RC_TRANSDTL_FULL 58 // Á÷Ë®ÒÑÂú
+#define RC_TRANSDTL_NO_ERR 59 //Á÷Ë®ºÅÒì³£
+#define RC_DEVICENO_OUT 60 // »úºÅ¹ý´ó
+
+#define RC_QRCODE_FAILURE 61 //¶þάÂë»ñȡʧ°Ü
+#define RC_QRCODE_TIMEOUT 62 //¶þάÂ볬ʱ
+#define RC_QRCODE_QUERY_FAIL 63 //¶þάÂëÈÏ֤ʧ°Ü
+
+#define RC_DEV_LOGIN_FAIL 64 //É豸µÇ¼ʧ°Ü
+#define RC_DEV_NOT_LOGIN 65 //É豸δǩµ½
+#define RC_DEV_FAULT 66 //É豸ÒÉËƹÊÕÏ
+#define RC_DEV_NOSET_FLOWSENSOR_UNIT 67 //É豸Á÷Á¿¼ÆË㵥λδÉèÖÃ
+#define STATUS_KEEPOPEN 1 //³£¿ª¿¨
+#define STATUS_CLOSED 0 //È¡Ïû³£¿ª¿¨
+
+#endif
+
diff --git a/supwisdom/sp_consume.c b/supwisdom/sp_consume.c
new file mode 100644
index 0000000..587e2a4
--- /dev/null
+++ b/supwisdom/sp_consume.c
@@ -0,0 +1,729 @@
+#include "sp_util.h"
+#include "sp_constant.h"
+#include "sp_display.h"
+#include "sp_flash.h"
+#include "sp_card.h"
+#include "sp_des.h"
+#include "sp_msgpack.h"
+#include "sp_menu.h"
+#include "sp_data.h"
+#include "sp_consume.h"
+#include "sp_communicate.h"
+
+static int count = 0;
+static uint16 sp_calc_payamt_by_flowsensor(sp_pos_t* pos, sp_card_t* card)
+{
+ uint32 usedcount = 0;
+
+ if(pos->purchase.paid_num < 1)
+ {
+ //Ê×ÏÈÔ¤¿ÛÒ»±Ê
+ if(card->feepara.fee_start > 0)
+ {
+ //Ç°nË®Ãâ·Ñ
+ pos->purchase.prepaid_num = card->feepara.fee_start;
+ pos->purchase.prepaid_amt = 0;
+ }
+ else
+ {
+ pos->purchase.prepaid_num = card->feepara.fee_unit;
+ pos->purchase.prepaid_amt = card->feepara.fee_amt;
+ }
+ pos->purchase.used_num = 0;
+ return 0;
+ }
+ //usedcount = sp_flowsensor_get_count()/pos->sysconf.flowsensor_uint;
+ usedcount = count/pos->sysconf.flowsensor_unit;
+ count++;
+ if(usedcount < pos->purchase.paid_num)
+ {
+ //ûÓдﵽ¿Û·ÑÁ÷Á¿
+ return 0;
+ }
+ pos->purchase.used_num = pos->purchase.paid_num;
+ pos->purchase.prepaid_num = card->feepara.fee_unit;
+ pos->purchase.prepaid_amt = card->feepara.fee_amt;
+ return 0;
+}
+
+//¼ÇÕËģʽÏû·Ñ
+uint16 sp_account_purchase(uint16 amount)
+{
+ return 0;
+}
+
+static uint8 gPICC_SNR[4]; /* ¿¨Æ¬SNºÅ */
+
+void sp_test_card_state(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState, uint32 tick)
+{
+ uint8 ret = 0;
+ sp_card_t cardpcd;
+ switch(pos->cardState.cur_state)
+ {
+ case STATE_NONE:
+ MEMCLEAR(&cardpcd, sizeof(cardpcd));
+ if(sp_card_request(&cardpcd) == 0)
+ {
+ MEMCPY(pos->cardState.snr, cardpcd.cardphyid, sizeof(cardpcd.cardphyid));
+ MEMCPY(gPICC_SNR, cardpcd.cardphyid, sizeof(cardpcd.cardphyid));
+ pos->cardState.tag_type = cardpcd.cardtype;
+ pos->cardState.cur_state = STATE_EXIST;
+ pos->cardState.firsttick = tick;
+ pos->cardState.lasttick = tick;
+ }
+ else
+ {
+ cardWorkState->errcode = RC_CARD_INVALID;
+ }
+ break;
+ case STATE_EXIST:
+ //¼ì²â¿¨ÊÇ·ñ¼ÌÐø´æÔÚ
+ if(pos->cardState.tag_type == TAG_TYPE_CPU)
+ {
+ ret = sp_check_cpu_exist();
+ if(ret)
+ {
+ pos->cardState.cur_state = STATE_NONE;
+ break;
+ }
+ else
+ {
+ memcpy(pos->cardState.snr, gPICC_SNR, 8);
+ pos->cardState.lasttick = tick;
+ }
+ }
+ break;
+ default:
+ pos->cardState.cur_state = STATE_NONE;
+ break;
+ }
+}
+
+static uint16 sp_dev_config_check(const sp_pos_t* pos)
+{
+ uint8 devphyid[4];
+ MEMCLEAR(devphyid, sizeof(devphyid));
+ if(MEMCMP(pos->devphyid, devphyid, sizeof(devphyid)) == 0)
+ {
+ return RC_DEVPHYID_NOTSET;
+ }
+ if(pos->devlogin.login_flag != 1)
+ {
+ return RC_DEV_NOT_LOGIN;
+ }
+ if(pos->sysconf.work_mode == 9)
+ {
+ return RC_DEV_FAULT;
+ }
+ if(pos->sysconf.flowsensor_unit == 0)
+ {
+ return RC_DEV_NOSET_FLOWSENSOR_UNIT;
+ }
+ return 0;
+}
+
+//¶ÁÈ¡µÚÒ»±ÊδÉÏ´«Á÷Ë®Ïû·ÑÈÕÆÚʱ¼ä
+static uint8 sp_read_unconfirm_first_record(uint8 termtime[6])
+{
+ return 1;
+}
+
+static uint16 sp_dev_offline_check(const sp_pos_t* pos)
+{
+ uint8 ret;
+ uint8 record_termtime[6];
+ uint8 ctime[6];
+ int32 nowtime;
+ int32 dtltime;
+
+ if(pos->sysconf.dev_offline_maxhour == 0)
+ {
+ return 0;
+ }
+ memset(record_termtime,0,sizeof(record_termtime));
+ ret = sp_read_unconfirm_first_record(record_termtime);
+ if(ret)
+ {
+ return 0;
+ }
+ sp_get_bcdtime(ctime);
+ nowtime = format_time_covert_secs(ctime);
+ dtltime = format_time_covert_secs(record_termtime);
+
+ /**
+ *Á÷ˮʱ¼ä´óÓÚÉ豸ʱÖÓÇÒ³¬¹ý24Сʱ
+ **/
+ if((dtltime > nowtime) &&
+ ((dtltime - nowtime) > (24*60*DELAY_TIME60s)))
+ {
+ if(sp_valve_state())
+ {
+ sp_valve_off();
+ }
+ return RC_DEV_OFFLINE_ERROR;
+ }
+ /**
+ *Á÷ˮʱ¼äСÓÚÉ豸ʱÖÓÇÒ³¬¹ýãÐÖµ
+ **/
+ if((dtltime < nowtime) &&
+ ((nowtime - dtltime) > (pos->sysconf.dev_offline_maxhour*3600)))
+ {
+ if(sp_valve_state())
+ {
+ sp_valve_off();
+ }
+ return RC_DEV_OFFLINE_ERROR;
+ }
+ return 0;
+}
+
+static uint16 sp_card_valid_check(const sp_card_t* card)
+{
+ uint8 ctime[6];
+ /*
+ if(card->cardno < 1)
+ {
+ return RC_CARDNO_EXCEPT;
+ }
+ */
+ sp_get_bcdtime(ctime);
+ if(memcmp(card->expiredate +1, ctime, 3) < 0)
+ {
+ return RC_CARD_EXPIRED;
+ }
+ return 0;
+}
+
+static uint16 sp_check_dev(const sp_pos_t* pos)
+{
+ uint16 ret = 0;
+ uint8 ctime[6];
+ MEMCLEAR(ctime, sizeof(ctime));
+ sp_get_bcdtime(ctime);
+ if(pos->load_para_status)
+ {
+ return pos->load_para_status;
+ }
+ ret = sp_dev_config_check(pos);
+ if(ret)
+ {
+ return ret;
+ }
+ ret = sp_dev_offline_check(pos);
+ if(ret)
+ {
+ return ret;
+ }
+
+ return 0;
+}
+
+static uint16 do_idle(sp_pos_t* pos)
+{
+ uint8 ctime[6];
+ MEMCLEAR(ctime, sizeof(ctime));
+ sp_get_bcdtime(ctime);
+ show_home(pos);
+ return 0;
+}
+
+static uint16 do_new(sp_pos_t* pos, sp_card_t* card)
+{
+ uint16 ret = 0;
+ sp_transdtl_t record;
+ MEMCLEAR(&record, sizeof(record));
+ card->cardtype = pos->cardState.tag_type;
+ MEMCPY(card->cardphyid, pos->cardState.snr, 4);
+ ret = sp_card_read(card);
+ if(ret)
+ {
+ ret = RC_CARD_INVALID;
+ return ret;
+ }
+ ret = sp_card_authentication(pos, card);
+ if(ret)
+ {
+ ret = RC_CARD_AUTHENTICATION;
+ return ret;
+ }
+ if(pos->load_para_status)
+ {
+ return pos->load_para_status;
+ }
+ ret = sp_dev_config_check(pos);
+ if(ret)
+ {
+ return ret;
+ }
+ ret = sp_dev_offline_check(pos);
+ if(ret)
+ {
+ return ret;
+ }
+
+ ret = sp_card_valid_check(card);
+ if(ret)
+ {
+ return ret;
+ }
+ ret = sp_prepare_behalf_transdtl(pos, card, &record);
+ if(ret)
+ {
+ return ret;
+ }
+ pos->sysconf.work_mode = 1;
+ pos->paymode = PAYMODE_CARD;
+ return 0;
+}
+
+static uint16 do_start(sp_pos_t* pos)
+{
+ MEMCLEAR(&pos->purchase,sizeof(sp_purchase_t));
+ sp_flowsensor_count_clear();
+ sp_get_bcdtime(pos->purchase.starttime);
+ sp_valve_on();
+ show_money(pos, pos->purchase.paid_sum);
+ return 0;
+}
+
+static uint16 do_work_check(const sp_pos_t* pos)
+{
+ //ÅжÏÏû·Ñ½ð¶îÈç¹û´óÓÚ20»òÕßÁ¬ÐøÏû·Ñ³¬¹ý2Сʱ£¬ÔòÍ£Ö¹³öË®
+ if(pos->purchase.used_num >= 1000 || pos->purchase.paid_sum >= 1000)
+ {
+ return RC_CARD_TIMEOUT;
+ }
+ return 0;
+}
+
+static uint16 do_work(sp_pos_t* pos, sp_card_t* card)
+{
+ uint16 ret = 0;
+ sp_valve_on();
+ ret = do_work_check(pos);
+ if(ret)
+ {
+ return ret;
+ }
+ //¼ÆËãÏû·Ñ½ð¶î
+ ret = sp_calc_payamt_by_flowsensor(pos, card);
+ if(ret)
+ {
+ return ret;
+ }
+ if(pos->purchase.prepaid_amt > 0)
+ {
+ //ĬÈϼÇÕËģʽ
+ ret = sp_account_purchase(pos->purchase.prepaid_amt);
+ if(ret)
+ {
+ return ret;
+ }
+ }
+
+ if(pos->purchase.prepaid_num > 0)
+ {
+ pos->purchase.paid_num += pos->purchase.prepaid_num;
+ pos->purchase.paid_sum += pos->purchase.prepaid_amt;
+ pos->purchase.prepaid_num = 0;
+ pos->purchase.prepaid_amt = 0;
+ }
+ show_money(pos, pos->purchase.paid_sum);
+ return 0;
+}
+
+static uint16 do_stop(sp_pos_t* pos, sp_card_t* card)
+{
+ uint16 ret;
+ sp_transdtl_t record;
+ sp_valve_off();
+
+ if(pos->purchase.paid_num > 0)
+ {
+ MEMCLEAR(&record, sizeof(record));
+ ret = sp_prepare_below_transdtl(pos, card, &record);
+ if(ret)
+ {
+ return ret;
+ }
+ }
+ pos->paymode = PAYMODE_INIT;
+ pos->sysconf.work_mode = 0;
+ count = 0;
+ MEMCLEAR(&pos->purchase, sizeof(sp_purchase_t));
+ MEMCLEAR(card, sizeof(sp_card_t));
+ return 0;
+}
+
+static void do_pause(sp_pos_t* pos)
+{
+ char msg[17];
+ MEMCLEAR(msg, sizeof(msg));
+ sp_valve_off();
+ if(pos->purchase.paid_sum > 0)
+ {
+ sprintf(msg,"¹²¼Æ %0.2fÔª",pos->purchase.paid_sum/100.0f);
+ disp_hint_info_two(pos,"½áÊø¼Æ·Ñ",msg,DELAY_TIME2s);
+ }
+ else
+ {
+ disp_hint_info_two(pos,"½áÊø¼Æ·Ñ","Ãâ·ÑʹÓÃ",DELAY_TIME2s);
+ }
+}
+
+static void do_error(sp_pos_t* pos, uint16 errcode)
+{
+ if(errcode)
+ {
+ show_error(pos,"²Ù×÷ʧ°Ü:",errcode);
+ pos->paymode = PAYMODE_INIT;
+ pos->sysconf.work_mode = 0;
+ count = 0;
+ MEMCLEAR(&pos->purchase, sizeof(sp_purchase_t));
+ }
+}
+
+static uint16 sp_card_exist_handle(sp_pos_t* pos, sp_card_t* card,
+ sp_cardworkstate_t* cardWorkState)
+{
+ uint16 ret = 0;
+ uint16 err = 0;
+ sp_card_t cardpcd;
+ switch(cardWorkState->current_state)
+ {
+ case CARDWORKSTATUS_NONE:
+ if(timer_get_ticker() - pos->cardState.firsttick < 1500)
+ {
+ break;
+ }
+ ret = do_new(pos, card);
+ if(ret)
+ {
+ if(0x1018 == ret || 0x2001 == ret||
+ 0x1014 == ret || 0x1030 == ret)
+ {
+ if(0 == sp_card_request(&cardpcd))
+ {
+ break;
+ }
+ }
+ cardWorkState->errcode = ret;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_READY;
+ break;
+ case CARDWORKSTATUS_READY:
+ if(MEMCMP(pos->cardState.snr, card->cardphyid, 4) != 0)
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ }
+ ret = do_start(pos);
+ if(ret)
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_WORKING;
+ break;
+ case CARDWORKSTATUS_PAUSE:
+ cardWorkState->current_state = CARDWORKSTATUS_WORKING;
+ break;
+ case CARDWORKSTATUS_WORKING:
+ if(MEMCMP(pos->cardState.snr, card->cardphyid, 4) != 0)
+ {
+ ret = RC_NOT_SAME_CARD;
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPING;
+ break;
+ }
+ cardWorkState->pause_status = 0;
+ ret = do_work(pos, card);
+ if(ret)
+ {
+ show_error(pos,"Ïû·Ñʧ°Ü",ret);
+ err = do_stop(pos, card);
+ if(err != 0)
+ {
+ ret = err;
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ if(pos->purchase.paid_num > card->waterlimit)
+ {
+ disp_hint_info(pos,"ÒÑ´ïµ¥´Î³öË®ÉÏÏÞ",DELAY_TIME2s);
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPING;
+ }
+ cardWorkState->pause_tick = timer_get_ticker();
+ break;
+ case CARDWORKSTATUS_STOPPING:
+ ret = do_stop(pos, card);
+ if(ret)
+ {
+ cardWorkState->errcode = ret;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPED;
+ break;
+ case CARDWORKSTATUS_STOPPED:
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ case CARDWORKSTATUS_FEECARD_WORKING:
+ if(MEMCMP(pos->cardState.snr, card->cardphyid, 4) != 0)
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ }
+ //show_menu_options();
+ break;
+ case CARDWORKSTATUS_ERROR:
+ do_error(pos, cardWorkState->errcode);
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ default:
+ Delay_ms(DELAY_TIME200ms);
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ }
+ cardWorkState->errcode = ret;
+ return ret;
+}
+
+static uint16 sp_card_noexist_handle(sp_pos_t* pos, sp_card_t* card,
+ sp_cardworkstate_t* cardWorkState)
+{
+ //Óп¨µ½ÎÞ¿¨
+ uint16 ret = 0;
+ switch(cardWorkState->current_state)
+ {
+ case CARDWORKSTATUS_NONE:
+ do_idle(pos);
+ break;
+ case CARDWORKSTATUS_READY:
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ case CARDWORKSTATUS_WORKING:
+ cardWorkState->current_state = CARDWORKSTATUS_PAUSE;
+ break;
+ case CARDWORKSTATUS_PAUSE:
+ if(MEMCMP(pos->cardState.snr, card->cardphyid, 4) == 0)
+ {
+ //¿¨ÄÃ×ßÒ»·ÖÖÓÖ®ÄÚĬÈÏÔÝͣʹÓÃ
+ if((timer_get_ticker() - cardWorkState->pause_tick) <= DELAY_TIME60s)
+ {
+ if(!cardWorkState->pause_status)
+ {
+ do_pause(pos);
+ show_home(pos);
+ }
+ show_home(pos);
+ cardWorkState->pause_status = 1;
+ }
+ else
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPING;
+ cardWorkState->pause_status = 0;
+ }
+ }
+ else
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPING;
+ cardWorkState->pause_status = 0;
+ }
+ cardWorkState->last_state = CARDWORKSTATUS_PAUSE;
+ break;
+ case CARDWORKSTATUS_STOPPING:
+ ret = do_stop(pos, card);
+ if(ret)
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPED;
+ cardWorkState->tick = timer_get_ticker();
+ break;
+ case CARDWORKSTATUS_STOPPED:
+ if(timer_get_ticker() - cardWorkState->tick > DELAY_TIME3s)
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ cardWorkState->last_state = cardWorkState->current_state;
+ cardWorkState->tick = 0;
+ }
+ break;
+ case CARDWORKSTATUS_SET_DEV:
+ if(sp_check_passwd(pos, "É豸¹ÜÀíÃÜÂë", "\x9\x1\x4\x3\x8\x7") == 0)
+ {
+ sp_menu_options(pos);
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ case CARDWORKSTATUS_ERROR:
+ do_error(pos,cardWorkState->errcode);
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ default:
+ Delay_ms(DELAY_TIME200ms);
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ break;
+ }
+ cardWorkState->errcode = ret;
+ return ret;
+}
+
+static sp_card_t CARD;
+void sp_card_handle(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState)
+{
+ if(pos->cardState.cur_state)
+ {
+ sp_card_exist_handle(pos, &CARD, cardWorkState);
+ }
+ else
+ {
+ sp_card_noexist_handle(pos, &CARD, cardWorkState);
+ }
+}
+
+void sp_confirm_paymode(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState)
+{
+ uint8 keycode = SP_KEY_NONE;
+ keycode = sp_get_key();
+ //ÔÚ¿¨Ïû·ÑÔÝÍ£Çé¿öÏ°´ÈÎÒâ¼üΪ½áÊøµ±Ç°Ïû·Ñ״̬
+ if(keycode >= SP_KEY_0 && keycode <= SP_KEY_ENTER && pos->cardState.cur_state == STATE_NONE
+ && cardWorkState->current_state == CARDWORKSTATUS_PAUSE && pos->paymode == PAYMODE_CARD)
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPING;
+ return;
+ }
+ //Ïû·Ñģʽ³õʼ»¯×´Ì¬Ï°´È·ÈϼüÑ¡Ôñ¶þάÂëÏû·Ñ
+ if((keycode == SP_KEY_ENTER) && (pos->paymode == PAYMODE_INIT))
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ pos->paymode = PAYMODE_QRCODE;
+ return;
+ }
+ //¶þάÂëģʽÏ°´È¡Ïû¼üΪֹͣ¹¤×÷
+ if((pos->paymode == PAYMODE_QRCODE) && (keycode == SP_KEY_CLEAR))
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_STOPPING;
+ return;
+ }
+ //°´0¼ü½øÈëÉ豸²Ù×÷½çÃæ
+ if(keycode == SP_KEY_0 && (pos->paymode == PAYMODE_INIT))
+ {
+ cardWorkState->current_state = CARDWORKSTATUS_SET_DEV;
+ return;
+ }
+}
+
+//¶þάÂëÏû·Ñ´¦Àí
+uint32 tick = 0;
+void sp_qrcode_handle(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState)
+{
+ uint16 ret = 0;
+ sp_transdtl_t record;
+ MEMCLEAR(&record, sizeof(record));
+ switch(cardWorkState->current_state)
+ {
+ case CARDWORKSTATUS_NONE:
+ ret = sp_check_dev(pos);
+ if(ret)
+ {
+ cardWorkState->errcode = ret;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ ret = sp_qrcode_init(pos, &CARD);
+ if(ret)
+ {
+ cardWorkState->errcode = ret;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ ret = sp_prepare_behalf_transdtl(pos, &CARD, &record);
+ if(ret)
+ {
+ cardWorkState->errcode = RC_QRCODE_TIMEOUT;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ pos->sysconf.work_mode = 1;
+ CARD.qrcode.starttime = sp_get_ticker();
+ disp_hint_info(pos, "ÕýÔÚÉú³É¶þάÂë", DELAY_TIME2s);
+ cardWorkState->last_state = cardWorkState->current_state;
+ cardWorkState->current_state = CARDWORKSTATUS_READY;
+ break;
+ case CARDWORKSTATUS_READY:
+ CARD.qrcode.nowtime = sp_get_ticker();
+ if((CARD.qrcode.nowtime - CARD.qrcode.starttime) > CARD.qrcode.validtime)
+ {
+ show_home(pos);
+ show_home_qrcode(CARD.qrcode.qrcode_url);
+ if(CARD.qrcode.nowtime - tick > DELAY_TIME3s)
+ {
+ tick = CARD.qrcode.nowtime;
+ ret = sp_qrcode_query(pos, &CARD);
+ if(!ret && CARD.qrcode.authstatus)
+ {
+ do_start(pos);
+ cardWorkState->last_state = cardWorkState->current_state;
+ cardWorkState->current_state = CARDWORKSTATUS_WORKING;
+ }
+ }
+ }
+ else
+ {
+ cardWorkState->errcode = RC_QRCODE_TIMEOUT;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ }
+ break;
+ case CARDWORKSTATUS_WORKING:
+ ret = do_work(pos, &CARD);
+ if(ret)
+ {
+ show_error(pos,"Ïû·Ñʧ°Ü",ret);
+ ret = do_stop(pos, &CARD);
+ if(ret)
+ {
+ cardWorkState->errcode = ret;
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ cardWorkState->last_state = cardWorkState->current_state;
+ cardWorkState->pause_tick = sp_get_ticker();
+ break;
+ case CARDWORKSTATUS_STOPPING:
+ if(cardWorkState->last_state == CARDWORKSTATUS_NONE
+ || cardWorkState->last_state == CARDWORKSTATUS_READY)
+ {
+ disp_hint_info(pos,"È¡ÏûË¢Âë!", DELAY_TIME2s);
+ pos->paymode = PAYMODE_INIT;
+ pos->sysconf.work_mode = 0;
+ }
+ else
+ {
+ if(cardWorkState->last_state != CARDWORKSTATUS_PAUSE)
+ do_pause(pos);
+ ret = do_stop(pos, &CARD);
+ if(ret)
+ {
+ cardWorkState->errcode = ret;
+ cardWorkState->current_state = CARDWORKSTATUS_ERROR;
+ break;
+ }
+ }
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ cardWorkState->last_state = cardWorkState->current_state;
+ break;
+ case CARDWORKSTATUS_ERROR:
+ do_error(pos,cardWorkState->errcode);
+ cardWorkState->current_state = CARDWORKSTATUS_NONE;
+ cardWorkState->last_state = cardWorkState->current_state;
+ break;
+ default:
+ Delay_ms(DELAY_TIME200ms);
+ break;
+ }
+}
diff --git a/supwisdom/sp_consume.h b/supwisdom/sp_consume.h
new file mode 100644
index 0000000..e6ba62c
--- /dev/null
+++ b/supwisdom/sp_consume.h
@@ -0,0 +1,12 @@
+#ifndef CONSUME_H_
+#define CONSUME_H_
+
+#include "sp_config.h"
+
+void sp_card_handle(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState);
+void sp_test_card_state(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState, uint32 tick);
+void sp_qrcode_handle(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState);
+void sp_confirm_paymode(sp_pos_t* pos, sp_cardworkstate_t* cardWorkState);
+
+#endif
+
diff --git a/supwisdom/sp_data.c b/supwisdom/sp_data.c
new file mode 100644
index 0000000..020b476
--- /dev/null
+++ b/supwisdom/sp_data.c
@@ -0,0 +1,366 @@
+#include "sp_data.h"
+#include "sp_util.h"
+#include "sp_flash.h"
+#include "sp_constant.h"
+#include "sp_display.h"
+
+#define record_behalf_len 25
+#define record_below_len 7
+
+//Ñ»·¼Ç¼ÿһ±ÊÁ÷Ë®¼Ç¼µÄµØÖ·
+static uint16 sp_write_last_record(sp_pos_t* pos)
+{
+ uint8 crc[2];
+ uint8 buff[sizeof(sp_last_transdtl_t)];
+ MEMCLEAR(buff, sizeof(buff));
+
+ pos->last_transdtl.this_offset += sizeof(sp_last_transdtl_t);
+ if(pos->last_transdtl.this_offset >= DEF_FLASH_PageSize)
+ {
+ sp_flash_erase(ADDR_LAST_TRANSNO);
+ pos->last_transdtl.this_offset = 0;
+ }
+ sp_protocol_crc((uint8*)&pos->last_transdtl, sizeof(buff)-2, pos->last_transdtl.crc);
+ sp_flash_write(pos->last_transdtl.this_offset+ADDR_LAST_TRANSNO,
+ (uint8*)&pos->last_transdtl, sizeof(buff));
+
+ sp_flash_read(pos->last_transdtl.this_offset+ADDR_LAST_TRANSNO, buff, sizeof(buff));
+ sp_protocol_crc(buff, sizeof(buff)-2, crc);
+ if(MEMCMP(pos->last_transdtl.crc,crc,2)!=0)
+ {
+ pos->load_para_status = RC_FLASH_ERR;
+ return RC_FLASH_ERR;
+ }
+ return 0;
+}
+
+static uint16 sp_write_behalf_record(sp_pos_t* pos, sp_transdtl_t* record)
+{
+ uint8 buf[record_behalf_len];
+ MEMCLEAR(buf, sizeof(buf));
+
+ pos->last_transdtl.transaddr += sizeof(sp_transdtl_t);
+ if(pos->last_transdtl.transaddr % DEF_FLASH_PageSize == 0)
+ {
+ if(pos->last_transdtl.transaddr >= ADDR_TRANSDTL_END)
+ {
+ pos->last_transdtl.transaddr = ADDR_TRANSDTL_BEGIN;
+ }
+ sp_flash_erase(pos->last_transdtl.transaddr);
+ }
+ sp_flash_write(pos->last_transdtl.transaddr, (uint8*)record, sizeof(buf));
+ return 0;
+}
+
+static uint16 sp_write_below_record(sp_pos_t* pos, sp_transdtl_t* record)
+{
+ uint8 crc[2];
+ uint8 buff[sizeof(sp_transdtl_t)];
+ MEMCLEAR(crc, sizeof(crc));
+ MEMCLEAR(buff, sizeof(buff));
+
+ sp_protocol_crc((uint8*)record, sizeof(buff)-2, record->crc);
+ sp_flash_write(pos->last_transdtl.transaddr+record_behalf_len,
+ (uint8*)record+record_behalf_len, record_below_len);
+ sp_flash_read(pos->last_transdtl.transaddr, buff, sizeof(buff));
+ sp_protocol_crc(buff, sizeof(buff)-2, crc);
+ if(MEMCMP(record->crc, crc, 2) != 0)
+ {
+ pos->load_para_status = RC_FLASH_ERR;
+ return RC_FLASH_ERR;
+ }
+ return 0;
+}
+
+//Ïû·Ñ³õʼ»¯ºó´æ´¢Éϰ벿·ÖÁ÷Ë®£¬·ÀÖ¹Ïû·Ñʧ°ÜÎÞÁ÷Ë®ÐÅÏ¢
+uint16 sp_prepare_behalf_transdtl(sp_pos_t* pos, sp_card_t* card, sp_transdtl_t* record)
+{
+ uint8 ret = 0;
+ uint8 ctime[6];
+ MEMCLEAR(ctime, sizeof(ctime));
+
+ sp_get_bcdtime(ctime);
+ memcpy(record->devphyid, pos->devphyid, sizeof(pos->devphyid));
+ memcpy(record->transdate, ctime, 3);
+ memcpy(record->transtime, ctime+3, 3);
+ memcpy(record->billno, card->billno, sizeof(card->billno));
+ memcpy(record->cardphyid, card->cardphyid, sizeof(card->cardphyid));
+ if(pos->paymode == PAYMODE_QRCODE)
+ {
+ record->transway = 2;
+ }
+ else
+ {
+ record->transway = 1;
+ }
+ ret = sp_write_behalf_record(pos, record);
+ if(ret)
+ return ret;
+ return sp_write_last_record(pos);
+}
+
+//ÈôÏû·Ñ³É¹¦£¬´æ´¢Ï°벿·ÖÁ÷Ë®ÐÅÏ¢
+uint16 sp_prepare_below_transdtl(sp_pos_t* pos, sp_card_t* card, sp_transdtl_t* record)
+{
+ uint8 buff[record_behalf_len];
+ MEMCLEAR(buff, sizeof(buff));
+
+ record->amount = pos->purchase.paid_sum;
+ if(pos->paymode == PAYMODE_QRCODE)
+ {
+ record->paidAmount = card->qrcode.paidAmount;
+ }
+ else
+ {
+ record->paidAmount = 0;
+ }
+ record->flowsensors = pos->purchase.paid_num;
+ record->transtatus = 1;
+ sp_flash_read(pos->last_transdtl.transaddr, buff, sizeof(buff));
+ MEMCPY(record, buff, sizeof(buff));
+ return sp_write_below_record(pos, record);
+}
+
+//Ñ»·´æ´¢Ã¿Ò»±ÊδÉÏ´«Á÷Ë®¼Ç¼µÄµØÖ·
+uint16 sp_write_unconfirm_record(sp_pos_t* pos)
+{
+ uint8 crc[2];
+ uint8 buff[sizeof(sp_unconfirm_transdtl_t)];
+ MEMCLEAR(buff, sizeof(buff));
+
+ pos->unconfirm_transdtl.this_offset += sizeof(buff);
+ if(pos->unconfirm_transdtl.this_offset >= DEF_FLASH_PageSize)
+ {
+ sp_flash_erase(ADDR_UNCONFIRM_TRANSNO);
+ pos->unconfirm_transdtl.this_offset = 0;
+ }
+ sp_protocol_crc((uint8*)&pos->unconfirm_transdtl, sizeof(buff)-2,
+ pos->unconfirm_transdtl.crc);
+ sp_flash_write(pos->unconfirm_transdtl.this_offset+ADDR_UNCONFIRM_TRANSNO,
+ (uint8*)&pos->unconfirm_transdtl, sizeof(buff));
+
+ sp_flash_read(pos->unconfirm_transdtl.this_offset+ADDR_UNCONFIRM_TRANSNO, buff,
+ sizeof(buff));
+ sp_protocol_crc(buff, sizeof(buff)-2, crc);
+ if(MEMCMP(pos->unconfirm_transdtl.crc, crc, 2) !=0)
+ {
+ pos->load_para_status = RC_FLASH_ERR;
+ return RC_FLASH_ERR;
+ }
+ return 0;
+}
+
+static uint16 sp_init_last_transdtl_ptr(sp_last_transdtl_t* record)
+{
+ record->transaddr = ADDR_TRANSDTL_BEGIN -sizeof(sp_transdtl_t);
+ record->this_offset = 0;
+ sp_protocol_crc((uint8*)record,sizeof(sp_last_transdtl_t) -2,record->crc);
+ return sp_flash_page_write(ADDR_LAST_TRANSNO,(uint8*)record,sizeof(sp_last_transdtl_t));
+}
+
+static uint16 sp_init_unconfirm_transdtl_ptr(sp_unconfirm_transdtl_t* record)
+{
+ record->transaddr = ADDR_TRANSDTL_BEGIN;
+ record->this_offset = 0;
+ sp_protocol_crc((uint8*)record,sizeof(sp_unconfirm_transdtl_t) -2,record->crc);
+ return sp_flash_page_write(ADDR_UNCONFIRM_TRANSNO,(uint8*)record,
+ sizeof(sp_unconfirm_transdtl_t));
+}
+
+static uint8 sp_load_last_transdtl_ptr(sp_pos_t* pos)
+{
+ uint8 crc[2];
+ sp_flash_page_read(ADDR_LAST_TRANSNO,(uint8*)&pos->last_transdtl,
+ sizeof(sp_last_transdtl_t));
+ sp_protocol_crc((uint8*)&pos->last_transdtl,sizeof(sp_last_transdtl_t) -2,crc);
+ if(MEMCMP(pos->last_transdtl.crc,crc,2) != 0)
+ {
+ sp_init_last_transdtl_ptr(&pos->last_transdtl);
+ }
+ return 0;
+}
+static uint8 sp_load_unconfirm_transdtl_ptr(sp_pos_t* pos)
+{
+ uint8 crc[2];
+ sp_flash_page_read(ADDR_UNCONFIRM_TRANSNO,(uint8*)&pos->unconfirm_transdtl,
+ sizeof(sp_unconfirm_transdtl_t));
+ sp_protocol_crc((uint8*)&pos->unconfirm_transdtl,sizeof(sp_unconfirm_transdtl_t) -2,crc);
+ if(MEMCMP(pos->unconfirm_transdtl.crc,crc,2) != 0)
+ {
+ sp_init_unconfirm_transdtl_ptr(&pos->unconfirm_transdtl);
+ }
+ return 0;
+}
+
+static uint16 sp_parse_config(sp_pos_t* pos, sp_config_t* config)
+{
+ pos->sysconf.dev_offline_maxhour = config->offline_work_hour;
+ if(pos->sysconf.dev_offline_maxhour == 0)
+ {
+ pos->sysconf.dev_offline_maxhour = DEV_OFFLINE_DEFAULT_HOUR;
+ }
+ pos->sysconf.flowsensor_unit = config->flowsensor_unit;
+ pos->deviceno = config->deviceno;
+ pos->devlogin.login_flag = config->login_flag;
+ MEMCPY(pos->devphyid,config->devphyid,4);
+ return 0;
+}
+static uint16 sp_read_config(sp_pos_t* pos, sp_config_t* config)
+{
+ uint8 crc[2];
+ sp_flash_read(ADDR_CONFIG_PARA,(uint8*)config,sizeof(sp_config_t));
+ sp_protocol_crc((uint8*)config,sizeof(sp_config_t) -2,crc);
+ if(memcmp(config->crc,crc,2) != 0)
+ {
+ return RC_CONFPARA_CRC_ERR;
+ }
+ sp_parse_config(pos, config);
+ return 0;
+}
+
+uint16 sp_clear_transdtl(sp_pos_t* pos)
+{
+ uint32 i;
+ uint16 ret = sp_flash_erase(ADDR_LAST_TRANSNO);
+ ret |= sp_flash_erase(ADDR_UNCONFIRM_TRANSNO);
+ for(i = ADDR_TRANSDTL_BEGIN; i < ADDR_TRANSDTL_END; i += DEF_FLASH_PageSize)
+ {
+ ret |= sp_flash_erase(i);
+ }
+ return ret;
+}
+
+static uint16 sp_init_device(sp_pos_t* pos)
+{
+ uint16 ret;
+ disp_hint_info_two(pos,"É豸³õʼ»¯","Çå¿ÕÁ÷Ë®",0);
+ ret |= sp_clear_transdtl(pos);
+ return ret;
+}
+
+void sp_reset_factory(sp_pos_t* pos)
+{
+ uint16 ret;
+ disp_hint_info_two(pos,"»Ö¸´³ö³§ÖÐ","ÇëÉÔµÈ...",0);
+ ret = sp_flash_erase(ADDR_CONFIG_PARA);
+ ret |=sp_clear_transdtl(pos);
+ if(!ret)
+ {
+ disp_hint_info_two(pos,"³õʼ»¯³É¹¦","µÈ´ýÖØÆô",0);
+ }
+ else
+ {
+ disp_hint_info_two(pos,"³õʼ»¯Ê§°Ü","µÈ´ýÖØÆô",0);
+ }
+ sp_reset();
+}
+
+uint16 sp_load_config(sp_pos_t* pos)
+{
+ uint16 ret;
+ sp_config_t config;
+ MEMCLEAR(&config,sizeof config);
+ ret |= sp_read_config(pos, &config);
+ if(ret)
+ {
+ sp_config_init(pos);
+ sp_init_device(pos);
+ }
+ ret |= sp_load_last_transdtl_ptr(pos);
+ ret |= sp_load_unconfirm_transdtl_ptr(pos);
+ return ret;
+}
+
+uint16 sp_save_config(sp_pos_t* pos, sp_config_t* config)
+{
+ uint8 buffer[sizeof(sp_config_t)];
+ uint8 crc[2];
+ sp_protocol_crc((uint8*)config,sizeof(sp_config_t)-2,config->crc);
+ sp_flash_erase(ADDR_CONFIG_PARA);
+ sp_flash_write(ADDR_CONFIG_PARA,(uint8*)config,sizeof(sp_config_t));
+ sp_flash_read(ADDR_CONFIG_PARA,buffer,sizeof buffer);
+ sp_protocol_crc(buffer,sizeof(buffer)-2,crc);
+ if(memcmp(config->crc,crc,2) != 0)
+ {
+ return RC_CONFPARA_CRC_ERR;
+ }
+ sp_parse_config(pos, config);
+ return 0;
+}
+
+uint16 sp_save_deviceno(sp_pos_t* pos, uint8 deviceno)
+{
+ uint16 ret;
+ sp_config_t config;
+ MEMCLEAR(&config, sizeof config);
+ ret = sp_read_config(pos, &config);
+ if(ret)
+ {
+ return ret;
+ }
+ config.deviceno = deviceno;
+ return sp_save_config(pos, &config);
+}
+uint16 sp_save_devphyid(sp_pos_t* pos, uint8 devphyid[4])
+{
+ uint16 ret;
+ sp_config_t config;
+ MEMCLEAR(&config, sizeof config);
+ ret = sp_read_config(pos, &config);
+ if(ret)
+ {
+ return ret;
+ }
+ MEMCPY(config.devphyid,devphyid,4);
+ return sp_save_config(pos, &config);
+}
+uint16 sp_save_login_info(sp_pos_t* pos, uint8 flag, uint8 unit, uint8 offline_maxhour)
+{
+ uint16 ret;
+ sp_config_t config;
+ MEMCLEAR(&config, sizeof config);
+ ret = sp_read_config(pos, &config);
+ if(ret)
+ {
+ return ret;
+ }
+ config.login_flag = flag;
+ config.flowsensor_unit = unit;
+ config.offline_work_hour = offline_maxhour;
+ return sp_save_config(pos, &config);
+}
+
+uint16 sp_save_heartbeat_info(sp_pos_t* pos, uint8 flag)
+{
+ uint16 ret;
+ sp_config_t config;
+ MEMCLEAR(&config, sizeof config);
+ ret = sp_read_config(pos, &config);
+ if(ret)
+ {
+ return ret;
+ }
+ config.login_flag = flag;
+ return sp_save_config(pos, &config);
+
+}
+
+uint16 sp_config_init(sp_pos_t* pos)
+{
+ uint16 ret = 0;
+ uint8 crc[2];
+ sp_config_t config;
+ MEMCLEAR(&config, sizeof(config));
+ disp_hint_info(pos,"É豸²ÎÊý³õʼ»¯", DELAY_TIME2s);
+ sp_protocol_crc((uint8*)&config,sizeof(sp_config_t)-2,config.crc);
+ sp_flash_erase(ADDR_CONFIG_PARA);
+ sp_flash_write(ADDR_CONFIG_PARA,(uint8*)&config,sizeof(sp_config_t));
+ sp_flash_read(ADDR_CONFIG_PARA,(uint8*)&config,sizeof(config));
+ sp_protocol_crc((uint8*)&config,sizeof(sp_config_t)-2,crc);
+ if(memcmp(config.crc,crc,2) != 0)
+ {
+ return RC_CONFPARA_CRC_ERR;
+ }
+ ret = sp_flash_erase(ADDR_CONFIG_PARA);
+ return ret;
+}
diff --git a/supwisdom/sp_data.h b/supwisdom/sp_data.h
new file mode 100644
index 0000000..1ed4942
--- /dev/null
+++ b/supwisdom/sp_data.h
@@ -0,0 +1,30 @@
+#ifndef _SP_DATA_H_
+#define _SP_DATA_H_
+
+#include "sp_config.h"
+#include "sp_communicate.h"
+
+//Á÷Ë®´¦Àí
+uint16 sp_prepare_behalf_transdtl(sp_pos_t* pos, sp_card_t* card, sp_transdtl_t* record);
+uint16 sp_prepare_below_transdtl(sp_pos_t* pos, sp_card_t* card, sp_transdtl_t* record);
+uint16 sp_read_lastrecord(const sp_pos_t* pos, sp_transdtl_t* dtl);
+uint16 sp_confirm_record(const sp_pos_t* pos, sp_transdtl_t* dtl);
+uint16 sp_query_record(const sp_pos_t* pos, uint8 refno[16], sp_transdtl_t* dtl);
+uint16 sp_clear_transdtl(sp_pos_t* pos);
+uint16 sp_write_unconfirm_record(sp_pos_t* pos);
+
+//ϵͳ²ÎÊýÉèÖÃ
+void sp_reset_factory(sp_pos_t* pos);
+uint16 sp_load_config(sp_pos_t* pos);
+uint16 sp_save_config(sp_pos_t* pos, sp_config_t* config);
+uint16 sp_save_deviceno(sp_pos_t* pos, uint8 deviceno);
+uint16 sp_save_devphyid(sp_pos_t* pos, uint8 devphyid[4]);
+uint16 sp_config_init(sp_pos_t* pos);
+uint16 sp_save_login_info(sp_pos_t* pos, uint8 flag, uint8 unit, uint8 offline_maxhour);
+uint16 sp_save_heartbeat_info(sp_pos_t* pos, uint8 flag);
+
+//É豸ÊÖ¶¯²Ù×÷½Ó¿Ú
+uint8 sp_confirm_login(sp_protocol_response_t* resp, sp_pos_t* pos);
+
+#endif
+
diff --git a/supwisdom/sp_des.c b/supwisdom/sp_des.c
new file mode 100644
index 0000000..5d19916
--- /dev/null
+++ b/supwisdom/sp_des.c
@@ -0,0 +1,39 @@
+#include "string.h"
+#include "../icc_apdu_lib/des.h"
+
+#include "sp_des.h"
+
+static des_context desctx;
+static des3_context des3ctx;
+
+uint8 single_des_set_keys(uint8 key[8])
+{
+ return des_set_key(&desctx, key);
+}
+
+void single_des_encrypt(uint8 src[8], uint8 dest[8])
+{
+ des_encrypt(&desctx, src, dest);
+}
+
+void single_des_decrypt(uint8 src[8], uint8 dest[8])
+{
+ des_decrypt(&desctx, src, dest);
+}
+
+uint8 triple_des_set_keys(uint8 key[16])
+{
+ return des3_set_2keys(&des3ctx, key, key+8);
+}
+
+void triple_des_encrypt(uint8 src[8], uint8 dest[8])
+{
+ des3_encrypt(&des3ctx, src, dest);
+}
+
+void triple_des_decrypt(uint8 src[8], uint8 dest[8])
+{
+ des3_decrypt(&des3ctx, src, dest);
+}
+
+
diff --git a/supwisdom/sp_des.h b/supwisdom/sp_des.h
new file mode 100644
index 0000000..bc8a7c7
--- /dev/null
+++ b/supwisdom/sp_des.h
@@ -0,0 +1,27 @@
+#ifndef _SP_DES_H_
+#define _SP_DES_H_
+
+#include "../config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint8 single_des_set_keys(uint8 key[8]);
+
+void single_des_encrypt(uint8 src[8], uint8 dest[8]);
+
+void single_des_decrypt(uint8 src[8], uint8 dest[8]);
+
+uint8 triple_des_set_keys(uint8 key[16]);
+
+void triple_des_encrypt(uint8 src[8], uint8 dest[8]);
+
+void triple_des_decrypt(uint8 src[8], uint8 dest[8]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/supwisdom/sp_display.c b/supwisdom/sp_display.c
new file mode 100644
index 0000000..fb0417c
--- /dev/null
+++ b/supwisdom/sp_display.c
@@ -0,0 +1,356 @@
+#include "glcd.h"
+#include "../zk/gb2312_16.h"
+#include "../libqr/qrencode.h"
+#include "sp_util.h"
+#include "sp_constant.h"
+#include "sp_display.h"
+
+#define GLCD_TITLE_X 0
+#define GLCD_TITLE_Y 0
+#define GLCD_TITLE_LINE 8
+#define GLCD_CONTENT_Y_ONE 0x10
+#define GLCD_CONTENT_Y_TWO 0x20
+#define GLCD_CONTENT_Y_THREE 0x30
+#define GLCD_BUTTOM_Y 56
+#define GLCD_LINE_LENGTH 0x10
+
+static char line_buff[17];
+
+/********************************************************************************************************
+* º¯Êý(Name) : void Show_Money(uint32 money)
+* ¹¦ÄÜ(Function) : ÏÔʾ½ð¶î
+* ²ÎÊý(Parameter) : money--¿¨Óà¶î(µ¥Î»:Ôª)
+* ·µ»Ø(Return) : ÎÞ
+**********************************************************************************************************/
+void show_money(sp_pos_t* pos, uint32 money)
+{
+ char msg[32];
+ sprintf(msg," %.02f Ԫ",money/100.0f);
+ disp_hint_info_two(pos,"ÀÛ¼ÆË®·Ñ:",msg,0);
+}
+
+void glcd_tiny_init(void)
+{
+ uint8 retry;
+ glcd_tiny_set_font(Font5x7,5,7,32,127);
+ glcd_clear_buffer();
+ glcd_write();
+ for(retry=0; retry<3; retry++)
+ {
+ if(gb2312_16_verify() == 0)
+ {
+ break;
+ }
+ }
+ glcd_write();
+}
+static void show_title(void)
+{
+ uint8 ctime[7];
+ glcd_tiny_set_font(Font5x7,5,7,32,127);
+ glcd_clear_buffer();
+ sp_get_bcdtime(ctime);
+ sprintf(line_buff, "%02x-%02x-%02x %02x:%02x:%02x",
+ ctime[0],ctime[1],ctime[2],
+ ctime[3],ctime[4],ctime[5]);
+ glcd_draw_string_xy(0, 0, line_buff);
+ glcd_draw_line(0, GLCD_TITLE_LINE, 127, 8, BLACK);
+}
+
+static void show_bottom(sp_pos_t* pos)
+{
+ sprintf(line_buff,"%02d:%02x%02x%02x%02x",pos->deviceno, pos->devphyid[0],
+ pos->devphyid[1], pos->devphyid[2], pos->devphyid[3]);
+ glcd_draw_string_xy(0, GLCD_BUTTOM_Y, line_buff);
+}
+
+static char last_qrcode_url[32]= {0};
+void show_home_qrcode(char* qrcode_url)
+{
+ uint8 i,j;
+ if(MEMCMP(qrcode_url,last_qrcode_url,(int)strlen(qrcode_url)) != 0)
+ {
+ sprintf(last_qrcode_url,"%s",qrcode_url);
+ //¶þάÂëÉú³ÉµãÕó
+ QRencode(last_qrcode_url, NULL);
+ }
+ //¶þάÂëµãÕóÏÔʾ
+ for(i=0; i<MAX_MODULESIZE*2; i++)
+ {
+ for(j=0; j<MAX_MODULESIZE*2; j++)
+ {
+ uint8_t pixel = m_byModuleData[i/2][j/2];
+
+ glcd_set_pixel(j+70, 12+i, pixel);
+ glcd_set_pixel(j+70, 12+i+1, pixel);
+ j ++;
+ glcd_set_pixel(j+70, 12+i, pixel);
+ glcd_set_pixel(j+70, 12+i+1, pixel);
+ }
+ i ++;
+ }
+ glcd_write();
+
+}
+static uint8 last_ctime[6];
+void show_home(sp_pos_t* pos)
+{
+ uint8 ctime[6];
+ sp_get_bcdtime(ctime);
+ if(MEMCMP(ctime,last_ctime,6) != 0)
+ {
+ MEMCPY(last_ctime,ctime,6);
+ disp_hint_info_two(pos,"F°æ±¾",PRO_VERSION,0);
+ /*
+ if(pos->sysconf.register_flag)
+ {
+ if(pos->dynamic.ws_client_stat)
+ {
+ show_home_qrcode(pos->dynamic.qrcode_url);
+ }
+ }
+ */
+ }
+}
+
+void show_set_devno(sp_pos_t* pos, uint8 devno)
+{
+ char msg[32];
+ sprintf(msg,"»úºÅ=%d",devno);
+ disp_hint_info_two(pos, "ÉèÖûúºÅ³É¹¦",msg,DELAY_TIME1s);
+}
+void show_set_devphyid(sp_pos_t* pos, uint8 devphyid[4])
+{
+ char msg[32];
+ sprintf(msg,"ID=%02x%02x%02x%02x",
+ devphyid[0],devphyid[1],devphyid[2],devphyid[3]);
+ disp_hint_info_two(pos,"ÉèÖÃÎïÀíID³É¹¦",msg,DELAY_TIME1s);
+}
+void show_set_dev_offline_maxhour(sp_pos_t* pos, uint16 maxhour)
+{
+ char msg[32];
+ sprintf(msg,"ÍÑ»ú¹¤×÷ʱ¼ä=%d",maxhour);
+ disp_hint_info_two(pos, "ÉèÖÃÍÑ»ú¹¤×÷ʱ¼ä³É¹¦",msg,DELAY_TIME1s);
+}
+
+void show_manage_passwd(sp_pos_t* pos, const char* hint,uint8 passwd[],uint8 len)
+{
+ char msg[32];
+ switch(len)
+ {
+ case 0:
+ sprintf(msg,"");
+ break;
+ case 1:
+ sprintf(msg,"%d",passwd[0]);
+ break;
+ case 2:
+ sprintf(msg,"%d%d",passwd[0],passwd[1]);
+ break;
+ case 3:
+ sprintf(msg,"%d%d%d",passwd[0],passwd[1],passwd[2]);
+ break;
+ case 4:
+ sprintf(msg,"%d%d%d%d",passwd[0],passwd[1],passwd[2],passwd[3]);
+ break;
+ case 5:
+ sprintf(msg,"%d%d%d%d%d",passwd[0],passwd[1],passwd[2],passwd[3],passwd[4]);
+ break;
+ case 6:
+ sprintf(msg,"%d%d%d%d%d%d",passwd[0],passwd[1],passwd[2],passwd[3],passwd[4],passwd[5]);
+ break;
+ default:
+ sprintf(msg,"");
+ }
+ disp_hint_info_two(pos,hint,msg,0);
+}
+
+void show_error(sp_pos_t* pos, const char* hint, uint16 errcode)
+{
+ char msg[32];
+ switch(errcode)
+ {
+ case RC_PSAM_ERR:
+ sprintf(msg,"%s", "SAM¸´Î»Ê§°Ü");
+ break;
+ case RC_CARD_LOGIN:
+ sprintf(msg,"%s", "ÑéÖ¤ÃØԿʧ°Ü");
+ break;
+ case RC_CARD_READ:
+ sprintf(msg,"%s", "¶Á¿¨Ê§°Ü");
+ break;
+ case RC_CARD_WRITE:
+ sprintf(msg,"%s", "д¿¨Ê§°Ü");
+ break;
+ case RC_FLASH_ERR:
+ sprintf(msg,"%s", "FLASHÒì³£");
+ break;
+ case RC_HARDWARE_ERR:
+ sprintf(msg,"%s", "¹Ì¼þÒì³£");
+ break;
+ case RC_FLASH_NO_RIGHT:
+ sprintf(msg,"%s", "FLASHÏÞÖÆ");
+ break;
+ case RC_CARD_NORIGHT:
+ sprintf(msg,"%s", "¿¨ÎÞȨÏÞ");
+ break;
+ case RC_CARD_EXPIRED:
+ sprintf(msg,"%s", "¿¨ÒѹýÆÚ");
+ break;
+ case RC_CARD_LOST:
+ sprintf(msg,"%s", "¿¨ÒÑËø¶¨");
+ break;
+ case RC_CARDNO_EXCEPT:
+ sprintf(msg,"%s", "¿¨Òì³£");
+ break;
+ case RC_CARD_TIMEOUT:
+ sprintf(msg,"%s", "ʹÓÃÌ«¾Ã");
+ break;
+ case RC_CARDBAL_EXCEPT:
+ sprintf(msg,"%s", "Óà¶îÒì³£");
+ break;
+ case RC_CARDBAL_LACK:
+ sprintf(msg,"%s", "ÇëÁª»úÏû·Ñ");
+ break;
+ case RC_DEVPHYID_NOTSET:
+ sprintf(msg,"%s", "δÉèÖûúºÅ");
+ break;
+ case RC_FEERATE_NOTSET:
+ sprintf(msg,"%s", "δÉèÖ÷ÑÂÊ");
+ break;
+ case RC_DEV_OFFLINE_ERROR:
+ sprintf(msg,"%s", "É豸ÍÑ»úÌ«¾Ã");
+ break;
+ case RC_TRANSDTL_FULL:
+ sprintf(msg,"%s", "Á÷Ë®ÒÑÂú");
+ break;
+ case RC_FILE09_CRC_ERR:
+ sprintf(msg,"%s", "09CRC´íÎó");
+ break;
+ case RC_FILE10_CRC_ERR:
+ sprintf(msg,"%s", "10CRC´íÎó");
+ break;
+ case RC_CARD_INVALID:
+ sprintf(msg,"%s", "ÎÞЧ¿¨");
+ break;
+ case RC_FEENUM_ERROR:
+ sprintf(msg,"%s", "·ÑÂʸöÊý´íÎó");
+ break;
+ case RC_NOTSUPPORT:
+ sprintf(msg,"%s", "²»Ö§³Ö");
+ break;
+ case RC_NOT_SAME_CARD:
+ sprintf(msg,"%s", "²»Í¬¿¨");
+ break;
+ case RC_MODE_NOT_SUPPORT:
+ sprintf(msg,"%s", "ģʽ²»Ö§³Ö");
+ break;
+ case RC_UPDPROG_ERR:
+ sprintf(msg,"%s", "Éý¼¶Ê§°Ü");
+ break;
+ case RC_CONFPARA_CRC_ERR:
+ sprintf(msg,"%s", "ÅäÖÃCRC´íÎó");
+ break;
+ case RC_TRANSDTL_NO_ERR:
+ sprintf(msg,"%s", "Á÷Ë®ºÅÒì³£");
+ break;
+ case RC_DEVICENO_OUT:
+ sprintf(msg,"%s", "»úºÅ¹ý´ó");
+ break;
+ case RC_QRCODE_FAILURE:
+ sprintf(msg,"%s", "¶þάÂë»ñȡʧ°Ü");
+ break;
+ case RC_QRCODE_TIMEOUT:
+ sprintf(msg,"%s", "¶þάÂ볬ʱ");
+ break;
+ case RC_QRCODE_QUERY_FAIL:
+ sprintf(msg,"%s", "¶þάÂëÈÏ֤ʧ°Ü");
+ break;
+ case RC_DEV_NOT_LOGIN:
+ sprintf(msg,"%s", "É豸δǩµ½");
+ break;
+ case RC_DEV_FAULT:
+ sprintf(msg,"%s", "É豸ÒÉËƹÊÕÏ");
+ break;
+ case RC_DEV_NOSET_FLOWSENSOR_UNIT:
+ sprintf(msg,"%s", "Á÷Á¿¼ÆË㵥λδÉèÖÃ");
+ break;
+ case RC_CARD_AUTHENTICATION:
+ sprintf(msg,"%s", "¿¨ÈÏ֤ʧ°Ü");
+ break;
+ default:
+ sprintf(msg,"´íÎóÂë=0x%04x",errcode);
+ }
+ disp_hint_info_two(pos,hint,msg,DELAY_TIME3s);
+}
+
+void disp_hint_info_three(sp_pos_t* pos,const char* msg1,const char* msg2,const char* msg3,uint32 ms)
+{
+ show_title();
+ show_bottom(pos);
+
+ snprintf(line_buff,sizeof line_buff,"%s ",msg1);
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_ONE, line_buff);
+ snprintf(line_buff,sizeof line_buff,"%s ",msg2);
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_TWO, line_buff);
+ snprintf(line_buff,sizeof line_buff,"%s ",msg3);
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_THREE, line_buff);
+
+ glcd_write();
+ if(ms > 0)
+ {
+ Delay_ms(ms);
+ }
+}
+
+void disp_hint_info_two(sp_pos_t* pos,const char* msg1,const char* msg2,uint32 ms)
+{
+ show_title();
+ show_bottom(pos);
+
+ snprintf(line_buff,sizeof line_buff,"%s ",msg1);
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_ONE, line_buff);
+ snprintf(line_buff,sizeof line_buff,"%s ",msg2);
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_TWO, line_buff);
+
+ glcd_write();
+ if(ms > 0)
+ {
+ Delay_ms(ms);
+ }
+}
+void disp_hint_info(sp_pos_t* pos,const char* msg1,uint32 ms)
+{
+ show_title();
+ show_bottom(pos);
+
+ snprintf(line_buff,sizeof line_buff,"%s ",msg1);
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_ONE, line_buff);
+ snprintf(line_buff,sizeof line_buff," ");
+ gb2312_16_draw_str(0, GLCD_CONTENT_Y_TWO, line_buff);
+
+ glcd_write();
+ if(ms > 0)
+ {
+ Delay_ms(ms);
+ }
+}
+void disp_server_errmsg(sp_pos_t* pos,const char* hint,uint8 data[],uint16 len)
+{
+ uint8 strlen;
+ char errmsg[64];
+ strlen = data[0];
+ //command+canid+excmd+flag+retcode+len+crc
+ if((strlen +8) != len)
+ {
+ disp_hint_info_two(pos,hint,"ÇëÇó³¬Ê±",DELAY_TIME3s);
+ return;
+ }
+ if(strlen > 32)
+ {
+ strlen = 32;
+ }
+ snprintf(errmsg,strlen+1,"%s",data +1);
+ disp_hint_info_two(pos,hint,errmsg,DELAY_TIME3s);
+}
+
diff --git a/supwisdom/sp_display.h b/supwisdom/sp_display.h
new file mode 100644
index 0000000..3160248
--- /dev/null
+++ b/supwisdom/sp_display.h
@@ -0,0 +1,36 @@
+#ifndef _SP_DISPLAY_H_
+#define _SP_DISPLAY_H_
+
+#include "sp_config.h"
+
+/*******************************************************************************************************
+* º¯Êý(Name) : void Show_Error(uint32 errcode)
+* ¹¦ÄÜ(Function) : ÏÔʾ´íÎó´úÂë
+* ²ÎÊý(Parameter) : errcode -- ´íÎó´úºÅ
+* ·µ»Ø(Return) : ÎÞ
+********************************************************************************************************/
+void glcd_tiny_init(void);
+
+/*******************************************************************************************************
+* º¯Êý(Name) : void Show_Pass(void)
+* ¹¦ÄÜ(Function) : ÏÔʾPASS
+* ²ÎÊý(Parameter) : NULL
+* ·µ»Ø(Return) : ÎÞ
+********************************************************************************************************/
+ void show_set_devno(sp_pos_t* pos, uint8 devno);
+ void show_set_devphyid(sp_pos_t* pos, uint8 devphyid[4]);
+ void show_set_dev_offline_maxhour(sp_pos_t* pos, uint16 maxhour);
+ void show_error(sp_pos_t* pos, const char* hint,uint16 code);
+ void show_home(sp_pos_t* pos);
+ void show_money(sp_pos_t* pos, uint32 money);
+ void show_manage_passwd(sp_pos_t* pos, const char* hint,uint8 passwd[],uint8 len);
+ void show_home_qrcode(char* qrcode_url);
+
+ void disp_hint_info(sp_pos_t* pos, const char* msg1,uint32 ms);
+ void disp_hint_info_two(sp_pos_t* pos, const char* msg1,const char* msg2,uint32 ms);
+ void disp_hint_info_three(sp_pos_t* pos, const char* msg1,const char* msg2,
+ const char* msg3,uint32 ms);
+ void disp_server_errmsg(sp_pos_t* pos, const char* hint,uint8 data[],uint16 len);
+
+
+#endif
diff --git a/supwisdom/sp_flash.c b/supwisdom/sp_flash.c
new file mode 100644
index 0000000..0788aed
--- /dev/null
+++ b/supwisdom/sp_flash.c
@@ -0,0 +1,123 @@
+#include "sp_constant.h"
+#include "sp_util.h"
+
+#include "sp_flash.h"
+
+uint16 sp_flash_read(uint32 addr,uint8 buf[],uint32 len)
+{
+ return HW_Flash_Read(addr,len,buf);
+}
+uint16 sp_flash_write(uint32 addr,uint8 buf[],uint32 len)
+{
+ if(addr < DEF_IAP_BASE_ADDR)
+ {
+ return RC_FLASH_NO_RIGHT;
+ }
+ return HW_Flash_NotEraseWrite(addr,len,buf);
+}
+uint16 sp_flash_erase(uint32 addr)
+{
+ if(addr < DEF_IAP_BASE_ADDR)
+ {
+ return RC_FLASH_NO_RIGHT;
+ }
+ return HW_Flash_PageErase(addr / FLASH_PAGE_SIZE);
+}
+
+/**
+**¶ÁÈ¡Ò»Ò³Êý¾Ý,È«FF±íʾÎÞÊý¾Ý
+**@param len > 128 error
+**@return ·µ»Ø0±íʾ²éÕÒÊý¾Ý³É¹¦
+**@return ·µ»Ø·Ç0±íʾÎÞÓÐЧÊý¾Ý
+**/
+uint16 sp_flash_page_read(uint32 addr,uint8 buf[],uint32 len)
+{
+ uint32 i;
+ uint32 offset = 0;
+ uint8 temp[128];
+
+ if(len > sizeof(temp))
+ {
+ return 1;
+ }
+
+ while(1)
+ {
+ i = 0;
+ sp_flash_read(addr +offset,temp, len);
+ while(i < len)
+ {
+ if(0xFF == temp[i])
+ {
+ ++i;
+ }
+ else
+ {
+ break;
+ }
+ }
+ if(len == i)
+ {
+ if(0 == offset)
+ {
+ //ÎÞÊý¾Ý
+ return 1;
+ }
+ else
+ {
+ sp_flash_read(addr +offset -len,buf, len);
+ return 0;
+ }
+ }
+ offset += len;
+ if(DEF_FLASH_PageSize < (offset +len)) // ³¬¹ýµ±Ò³Î´ÕÒµ½·µ»Ø1
+ {
+ return 1;
+ }
+ }
+}
+/**
+**дһҳÊý¾Ý
+**@param len > 32 error
+**@return ·µ»Ø0±íʾ¼Ç¼Êý¾Ý³É¹¦
+**@return ·µ»Ø·Ç0±íʾдFLASHʧ°Ü
+**/
+uint16 sp_flash_page_write(uint32 addr,uint8 buf[],uint32 len)
+{
+ uint32 i;
+ uint32 offset = 0;
+ uint8 temp[64];
+
+ if(len > 64)
+ {
+ return 1;
+ }
+ while(1)
+ {
+ i = 0;
+ sp_flash_read(addr +offset,temp, len);
+ while(i < len)
+ {
+ if(0xFF == temp[i])
+ {
+ ++i;
+ }
+ else
+ {
+ break;
+ }
+ }
+ if(DEF_FLASH_PageSize < (offset +len)) // ³¬¹ýµ±Ò³±íʾÒÑдÂú,²Á³ýÖØд
+ {
+ sp_flash_erase(addr);
+ return sp_flash_write(addr,buf, len);
+ }
+ if(len == i)
+ {
+ //ÎÞÊý¾Ý
+ return sp_flash_write(addr +offset,buf, len);
+ }
+ offset += len;
+ }
+}
+
diff --git a/supwisdom/sp_flash.h b/supwisdom/sp_flash.h
new file mode 100644
index 0000000..f01517d
--- /dev/null
+++ b/supwisdom/sp_flash.h
@@ -0,0 +1,63 @@
+#ifndef _SP_FLASH_H_
+#define _SP_FLASH_H_
+
+#include "../sys_hw/Prj_FlashCfg.H"
+#include "sp_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///////////////////EEPROM ¿Õ¼ä/////////////////////////////
+///////////////////FLASH ¿Õ¼ä////////////////////////////////////////////////////
+
+#if 0
+#define ADDR_FLASH_BEGIN 0x17000 // base addr
+#define ADDR_CONFIG_PARA 0x17000 //ÅäÖòÎÊý
+
+#define ADDR_TRANSDTL_PTR 0x18000 //Á÷ˮָÕë
+#define ADDR_TRANSDTL_BEGIN 0x200000 //Á÷Ë®Æðʼ
+#define ADDR_TRANSDTL_END 0x350000 //Á÷Ë®½áÊø
+#define ADDR_MAX 0x400000
+#endif
+//###############################################################
+/*********Ô¶³ÌÉý¼¶Îļþ´æ´¢100Ò³*********************/
+/*********×¢ÒâÉý¼¶µØÖ·ÓëBOOTÉý¼¶µØÖ·±£³ÖÒ»ÖÂ**/
+#define DEF_IAP_BASE_ADDR (DEF_FLASH_IAP_AppCodeStartAdd)
+#define DEF_IapMarkAddr ( DEF_IAP_BASE_ADDR + 1 * DEF_FLASH_PageSize ) //IAPÉý¼¶±ê¼ÇµØÖ·
+#define DEF_EraMarkAddr ( DEF_IAP_BASE_ADDR + 2 * DEF_FLASH_PageSize ) //²Á³ýFLASH±ê¼Ç
+#define DEF_IapDataAddr ( DEF_IAP_BASE_ADDR + 3 * DEF_FLASH_PageSize ) //IAPÊý¾ÝÇøÆðʼµØÖ·
+
+#define DEF_FLASH_codeStartAdd (DEF_IapDataAddr)
+
+#define ADDR_UPGRADE_UPINFO (ADDR_FLASH_END + DEF_FLASH_PageSize *1)
+#define ADDR_KEY_PARA (ADDR_UPGRADE_UPINFO + DEF_FLASH_PageSize *1)
+
+#define ADDR_UPGRADE_BEGIN (DEF_FLASH_codeStartAdd)
+#define ADDR_UPGRADE_END (DEF_FLASH_IAP_AppCodeEndAdd -DEF_FLASH_PageSize)
+
+#define ADDR_APPLICATION_BASE 0x130000 //base addr
+#define ADDR_APP_VERSION (ADDR_APPLICATION_BASE) //°æ±¾±êʶ
+
+#define ADDR_CONFIG_PARA (ADDR_APP_VERSION +DEF_FLASH_PageSize *1)//ÅäÖòÎÊý
+
+#define ADDR_LAST_TRANSNO (ADDR_CONFIG_PARA +DEF_FLASH_PageSize *10)
+#define ADDR_UNCONFIRM_TRANSNO (ADDR_LAST_TRANSNO +DEF_FLASH_PageSize *1)
+#define ADDR_TRANSDTL_BEGIN (ADDR_UNCONFIRM_TRANSNO +DEF_FLASH_PageSize *1)
+#define ADDR_TRANSDTL_END (ADDR_TRANSDTL_BEGIN +DEF_FLASH_PageSize *100)
+#define ADDR_FLASH_END (ADDR_TRANSDTL_END)
+#define ADDR_MAX 0x400000
+
+//#########################################
+
+uint16 sp_flash_read(uint32 addr,uint8 buf[],uint32 len);
+uint16 sp_flash_write(uint32 addr,uint8 buf[],uint32 len);
+uint16 sp_flash_erase(uint32 addr);
+uint16 sp_flash_page_read(uint32 addr,uint8 buf[],uint32 len);
+uint16 sp_flash_page_write(uint32 addr,uint8 buf[],uint32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/supwisdom/sp_menu.c b/supwisdom/sp_menu.c
new file mode 100644
index 0000000..4447d52
--- /dev/null
+++ b/supwisdom/sp_menu.c
@@ -0,0 +1,655 @@
+#include "sp_menu.h"
+#include "sp_util.h"
+#include "sp_data.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "sp_constant.h"
+#include "sp_communicate.h"
+#include "sp_display.h"
+#include "sp_upgrade.h"
+#include "../nec_hardware.h"
+
+typedef void(*menu_func_t)(sp_pos_t* pos);
+typedef struct
+{
+ char* hit;
+ menu_func_t func;
+} menu_t;
+
+static void sp_show_syspara(sp_pos_t* pos)
+{
+ uint32 ticker;
+ uint8 keycode;
+ uint8 key_press = 1;
+ uint8 max_cnt = 0;
+ uint8 offset = 0;
+ uint8 unconfirm_transnum;
+ char syspara[9][17];
+
+ MEMCLEAR(syspara, sizeof(syspara));
+ sprintf(syspara[offset++], "É豸״̬:");
+ if(pos->devlogin.login_flag == 1)
+ {
+ sprintf(syspara[offset++], "ÒÑÇ©µ½");
+ }
+ else if(pos->devlogin.login_flag == 0)
+ {
+ sprintf(syspara[offset++], "δǩµ½");
+ }
+ else if(pos->devlogin.login_flag == 2)
+ {
+ sprintf(syspara[offset++], "ÒÑ×¢Ïú");
+ }
+ sprintf(syspara[offset++], "Á´Â·×´Ì¬:");
+ if(pos->link_stat)
+ {
+ sprintf(syspara[offset++], "ÁªÍø");
+ }
+ else
+ {
+ sprintf(syspara[offset++], "ÖжÏ");
+ }
+ sprintf(syspara[offset++], "δÉÏ´«Á÷Ë®:");
+ if(pos->unconfirm_transdtl.transaddr <= pos->last_transdtl.transaddr)
+ {
+ if(pos->unconfirm_transdtl.transaddr == pos->last_transdtl.transaddr)
+ {
+ unconfirm_transnum = 1;
+ }
+ else
+ {
+ unconfirm_transnum = ((pos->last_transdtl.transaddr -
+ pos->unconfirm_transdtl.transaddr)/sizeof(sp_transdtl_t));
+ }
+ }
+ else
+ {
+ unconfirm_transnum = 0;
+ }
+ sprintf(syspara[offset++], "%d±Ê", unconfirm_transnum);
+ sprintf(syspara[offset++], "Ïû·ÑÀàÐÍ:");
+ sprintf(syspara[offset++], "¼ÇÕËÏû·Ñ");
+
+ max_cnt = sizeof(syspara)/sizeof(syspara[0])/2;
+ offset = 0;
+ ticker = sp_get_ticker();
+ while(sp_get_ticker()-ticker <= DELAY_TIME60s)
+ {
+ keycode = sp_get_key();
+ if(keycode != SP_KEY_NONE)
+ {
+ key_press = 1;
+ switch(keycode)
+ {
+ case SP_KEY_0:
+ if(offset < max_cnt-1)
+ {
+ offset++;
+ }
+ break;
+ case SP_KEY_1:
+ case SP_KEY_2:
+ case SP_KEY_3:
+ case SP_KEY_4:
+ case SP_KEY_5:
+ case SP_KEY_6:
+ case SP_KEY_7:
+ case SP_KEY_8:
+ case SP_KEY_9:
+ offset = keycode -SP_KEY_0;
+ if(offset >= max_cnt)
+ {
+ offset = max_cnt -1;
+ }
+ break;
+ case SP_KEY_CLEAR:
+ return;
+ }
+ }
+ if(key_press)
+ {
+ disp_hint_info_two(pos, syspara[2*offset],syspara[2*offset+1],0);
+ key_press = 0;
+ ticker = sp_get_ticker();
+ }
+ }
+}
+
+static uint8 sp_link_test(sp_pos_t* pos)
+{
+ uint8 ret;
+ sp_protocol_request_t req;
+ sp_protocol_response_t resp;
+ MEMCLEAR(&req, sizeof(req));
+ MEMCLEAR(&resp, sizeof(resp));
+
+ disp_hint_info_two(pos, "ÕýÔÚÁ´Â·¼ì²â", "ÇëÉÔµÈ.....", 0);
+ sp_protocol_req_init(&req, SP_CMD_FACTORY_LINK_TEST);
+ req.data[0] = 0;
+ req.data[1] = 0x55;
+ req.data[2] = 0xAA;
+ req.datalen += 3;
+ ret = sp_comm_call(pos, &req, &resp, DELAY_TIME3s);
+ if(!ret)
+ {
+ if(resp.data[0] == 0x55 && resp.data[1] == 0xAA)
+ {
+ if(sp_check_time_valid(resp.data +2))
+ {
+ disp_hint_info_two(pos, "Á´Â·¼ì²â³É¹¦","ʱÖÓ²»ºÏ·¨", DELAY_TIME3s);
+ return ret;
+ }
+ sp_set_bcdtime(resp.data +2);
+ disp_hint_info_two(pos, "Á´Â·¼ì²â³É¹¦","ÒÑͬ²½Ê±ÖÓ", DELAY_TIME3s);
+ return ret;
+ }
+ disp_hint_info_two(pos, "Á´Â·¼ì²âʧ°Ü","ÊÕµ½´íÎó°ü", DELAY_TIME3s);
+ return 1;
+ }
+ disp_hint_info_two(pos, "Á´Â·¼ì²âʧ°Ü","Çë¼ì²âÏß·", DELAY_TIME3s);
+ return ret;
+}
+
+static void show_keyboard_test(sp_pos_t* pos, uint8 offset)
+{
+ char msg[]= {"0123456789C"};
+ char temp[17];
+ snprintf(temp,offset+1,"%s",msg);
+ disp_hint_info_three(pos, "¼üÅÌÒÀ´ÎÊäÈë","0123456789C",temp,0);
+}
+
+static uint8 sp_keyboard_test(sp_pos_t* pos)
+{
+ uint8 kcode;
+ uint32 tick;
+ uint8 offset = 0;
+ uint8 keybuf[12]= {SP_KEY_0,SP_KEY_1,SP_KEY_2,SP_KEY_3,
+ SP_KEY_4,SP_KEY_5,SP_KEY_6,SP_KEY_7,
+ SP_KEY_8,SP_KEY_9,SP_KEY_CLEAR,SP_KEY_ENTER
+ };
+ show_keyboard_test(pos, offset);
+ tick = sp_get_ticker();
+ while((sp_get_ticker()-tick) < DELAY_TIME60s)
+ {
+ sp_feed_dog();
+ kcode = sp_get_key();
+ if(kcode != SP_KEY_NONE)
+ {
+ tick = sp_get_ticker();
+ switch(kcode)
+ {
+ case SP_KEY_0:
+ if(keybuf[offset] == SP_KEY_0)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_1:
+ if(keybuf[offset] == SP_KEY_1)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_2:
+ if(keybuf[offset] == SP_KEY_2)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_3:
+ if(keybuf[offset] == SP_KEY_3)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_4:
+ if(keybuf[offset] == SP_KEY_4)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_5:
+ if(keybuf[offset] == SP_KEY_5)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_6:
+ if(keybuf[offset] == SP_KEY_6)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_7:
+ if(keybuf[offset] == SP_KEY_7)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_8:
+ if(keybuf[offset] == SP_KEY_8)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_9:
+ if(keybuf[offset] == SP_KEY_9)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_CLEAR:
+ if(offset == 0)
+ {
+ disp_hint_info(pos, "È¡Ïû°´¼ü¼ì²â",DELAY_TIME2s);
+ return 1;
+ }
+ if(keybuf[offset] == SP_KEY_CLEAR)
+ {
+ ++offset;
+ show_keyboard_test(pos, offset);
+ }
+ break;
+ case SP_KEY_ENTER:
+ if(keybuf[offset] == SP_KEY_ENTER)
+ {
+ disp_hint_info_two(pos, "¼üÅ̼ì²âÕýÈ·","¼üÅÌУ׼Õý³£",DELAY_TIME3s);
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ return 1;
+
+}
+
+static void sp_factory_check(sp_pos_t* pos)
+{
+ sp_link_test(pos);
+ sp_keyboard_test(pos);
+}
+
+static void sp_set_devtime(sp_pos_t* pos)
+{
+ uint32 ticker;
+ uint8 kcode;
+ uint8 key_press = 1;
+ uint8 ctime[6];
+ uint8 offset;
+ char str[13];
+ char msg[17];
+
+ MEMCLEAR(str,sizeof str);
+ sp_get_bcdtime(ctime);
+ offset = 10;
+ sp_hex_to_str(ctime,5,str);
+ ticker = sp_get_ticker();
+ while(sp_get_ticker() -ticker < DELAY_TIME60s)
+ {
+ kcode = sp_get_key();
+ if(kcode != SP_KEY_NONE)
+ {
+ key_press = 1;
+ switch(kcode)
+ {
+ case SP_KEY_0:
+ case SP_KEY_1:
+ case SP_KEY_2:
+ case SP_KEY_3:
+ case SP_KEY_4:
+ case SP_KEY_5:
+ case SP_KEY_6:
+ case SP_KEY_7:
+ case SP_KEY_8:
+ case SP_KEY_9:
+ if(offset < 10)
+ {
+ str[offset++] = '0' + (kcode- SP_KEY_0);
+ }
+ break;
+ case SP_KEY_ENTER:
+ if(offset >= 10)
+ {
+ MEMCLEAR(ctime,sizeof ctime);
+ sp_str_to_bcd(str,10,ctime);
+ if(sp_check_time_valid(ctime))
+ {
+ disp_hint_info_two(pos,"ÉèÖÃʱ¼äʧ°Ü","ʱ¼ä²»ºÏ·¨", DELAY_TIME3s);
+ }
+ else
+ {
+ sp_set_bcdtime(ctime);
+ disp_hint_info_two(pos,"ÉèÖÃʱ¼ä³É¹¦"," ", DELAY_TIME2s);
+ return;
+ }
+ }
+ break;
+ case SP_KEY_CLEAR:
+ if(offset == 0)
+ {
+ return;
+ }
+ offset--;
+ str[offset] = 0;
+ break;
+ }
+ }
+ if(key_press)
+ {
+ sprintf(msg,"%s",str);
+ disp_hint_info_two(pos,"ÉèÖÃʱ¼ä(ymdHm)",msg,0);
+ ticker = sp_get_ticker();
+ key_press = 0;
+ }
+ }
+}
+
+static void sp_manual_login(sp_pos_t* pos)
+{
+ uint16 ret;
+ uint32 tick;
+ sp_protocol_response_t resp;
+ MEMCLEAR(&resp, sizeof(resp));
+ disp_hint_info_two(pos,"ÕýÔڵǼ","ÇëÉÔµÈ...",0);
+ sp_async_equipment_login(pos);
+ tick = sp_get_ticker();
+ while(sp_get_ticker() - tick < DELAY_TIME3s*2)
+ {
+ MEMCLEAR(&resp, sizeof(resp));
+ usart_read((u8*)&resp, sizeof(resp));
+ if(resp.excmd == SP_CMD_LOGIN)
+ {
+ ret = sp_confirm_login(&resp, pos);
+ break;
+ }
+ else
+ {
+ ret = RC_DEV_LOGIN_FAIL;
+ }
+ }
+ if(ret)
+ {
+ char msg[32];
+ sprintf(msg,"´íÎóÂë=%d",ret);
+ disp_hint_info_two(pos,"Ç©µ½Ê§°Ü",msg,DELAY_TIME3s);
+ }
+ else
+ {
+ disp_hint_info(pos,"Ç©µ½³É¹¦",DELAY_TIME3s);
+ }
+}
+
+static void sp_set_devphyid(sp_pos_t* pos)
+{
+ uint32 ticker;
+ uint8 kcode;
+ uint16 ret = 0;
+ uint8 key_press = 1;
+ char msg[17];
+ uint8 devphyid[4];
+ uint8 offset;
+ char str[9];
+ MEMCPY(devphyid,pos->devphyid,sizeof(pos->devphyid));
+ MEMCLEAR(str,sizeof str);
+
+ ticker = sp_get_ticker();
+ offset = 8;
+ sp_hex_to_str(devphyid,4,str);
+ while(sp_get_ticker() -ticker < DELAY_TIME60s)
+ {
+ kcode = sp_get_key();
+ if(kcode != SP_KEY_NONE)
+ {
+ key_press = 1;
+ switch(kcode)
+ {
+ case SP_KEY_0:
+ case SP_KEY_1:
+ case SP_KEY_2:
+ case SP_KEY_3:
+ case SP_KEY_4:
+ case SP_KEY_5:
+ case SP_KEY_6:
+ case SP_KEY_7:
+ case SP_KEY_8:
+ case SP_KEY_9:
+ if(offset < 8)
+ {
+ str[offset++] = '0' +(kcode -SP_KEY_0);
+ }
+ break;
+ case SP_KEY_ENTER:
+ if(offset >= 8)
+ {
+ sp_str_to_hex(str,8,devphyid);
+ if(0 != MEMCMP(pos->devphyid,devphyid,4))
+ {
+ ret = sp_save_devphyid(pos, devphyid);
+ }
+ if(!ret)
+ {
+ MEMCPY(pos->devphyid,devphyid,4);
+ sprintf(msg,"ID: %02x%02x%02x%02x",devphyid[0],devphyid[1],devphyid[2],devphyid[3]);
+ disp_hint_info_two(pos,"ÉèÖÃÎïÀíID³É¹¦",msg, DELAY_TIME2s);
+ }
+ else
+ {
+ show_error(pos,"±£´æÎïÀíIDʧ°Ü",ret);
+ }
+ return;
+ }
+ break;
+ case SP_KEY_CLEAR:
+ if(offset > 0)
+ {
+ offset--;
+ str[offset] = 0;
+ }
+ else
+ {
+ return;
+ }
+ break;
+ }
+ }
+ if(key_press)
+ {
+ sprintf(msg,"%s",str);
+ disp_hint_info_two(pos,"ÉèÖÃÎïÀíID:",msg,0);
+ ticker = sp_get_ticker();
+ key_press = 0;
+ }
+ }
+ return;
+}
+static void sp_set_deviceno(sp_pos_t* pos)
+{
+ uint32 ticker;
+ uint8 kcode;
+ uint16 ret = 0;
+ uint8 key_press = 1;
+ uint16 tempno;
+ uint8 deviceno = pos->deviceno;
+ char msg[17];
+ char temp[17];
+ ticker = sp_get_ticker();
+ while(sp_get_ticker() -ticker < DELAY_TIME60s)
+ {
+ kcode = sp_get_key();
+ if(kcode != SP_KEY_NONE)
+ {
+ key_press = 1;
+ switch(kcode)
+ {
+ case SP_KEY_0:
+ case SP_KEY_1:
+ case SP_KEY_2:
+ case SP_KEY_3:
+ case SP_KEY_4:
+ case SP_KEY_5:
+ case SP_KEY_6:
+ case SP_KEY_7:
+ case SP_KEY_8:
+ case SP_KEY_9:
+ tempno = (uint16)deviceno;
+ tempno *=10;
+ tempno += (kcode-SP_KEY_0);
+ if(tempno > 0 && tempno < DEV_MAX_DEVICENO)
+ {
+ deviceno = (uint8)tempno;
+ }
+ break;
+ case SP_KEY_ENTER:
+ if(deviceno > 0 && deviceno <= DEV_MAX_DEVICENO)
+ {
+ if(pos->deviceno != deviceno)
+ {
+ ret = sp_save_deviceno(pos,deviceno);
+ }
+ if(!ret)
+ {
+ pos->deviceno = deviceno;
+ sprintf(msg,"»úºÅ: %d",deviceno);
+ disp_hint_info_two(pos,"ÉèÖûúºÅ³É¹¦",msg, DELAY_TIME2s);
+ }
+ else
+ {
+ show_error(pos,"±£´æ»úºÅʧ°Ü",ret);
+ }
+ return;
+ }
+ else
+ {
+ sprintf(msg,"·¶Î§(1-%d)",DEV_MAX_DEVICENO);
+ disp_hint_info_two(pos,"»úºÅ´íÎó",msg, DELAY_TIME3s);
+ }
+ case SP_KEY_CLEAR:
+ if(deviceno == 0)
+ {
+ return;
+ }
+ deviceno = 0;
+ break;
+ }
+ }
+ if(key_press)
+ {
+ sprintf(temp,"ÉèÖûúºÅ(1-%d)",DEV_MAX_DEVICENO);
+ sprintf(msg,"%d",deviceno);
+ disp_hint_info_two(pos,temp,msg,0);
+ ticker = sp_get_ticker();
+ key_press = 0;
+ }
+ }
+ return;
+}
+
+static void clear_transdtl(sp_pos_t* pos)
+{
+ if(0 == sp_check_passwd(pos,"Çå¿ÕÁ÷Ë®ÃÜÂë:","\x9\x1\x4\x3\x8\x7"))
+ {
+ disp_hint_info_two(pos,"Çå¿ÕÁ÷Ë®","ÇëÉÔµÈ...",0);
+ sp_clear_transdtl(pos);
+ }
+}
+
+static void manual_upgrade(sp_pos_t* pos)
+{
+ if(0 == sp_check_passwd(pos, "ÔÚÏßÉý¼¶ÃÜÂë:","\x9\x1\x4\x3\x8\x7"))
+ {
+ sp_manual_upgrade(pos);
+ }
+}
+
+static void reset_factory(sp_pos_t* pos)
+{
+ if(0 == sp_check_passwd(pos, "»Ö¸´³ö³§ÃÜÂë:","\x9\x1\x4\x3\x8\x7"))
+ {
+ sp_reset_factory(pos);
+ }
+}
+
+void sp_menu_options(sp_pos_t* pos)
+{
+ uint32 ticker = 0;
+ uint8 keycode;
+ uint8 page;
+ uint8 max_cnt;
+ uint8 key_press = 1;
+
+ menu_t menus[] =
+ {
+ {"1.²é¿´²ÎÊý", sp_show_syspara},
+ {"2.¹¤³§²âÊÔ", sp_factory_check},
+ {"3.ÉèÖÃʱ¼ä", sp_set_devtime},
+ {"4.ÊÖ¶¯µÇ¼", sp_manual_login},
+ {"5.ÉèÖÃÎïÀíid", sp_set_devphyid},
+ {"6.ÉèÖûúºÅ", sp_set_deviceno},
+ {"7.Çå¿ÕÁ÷Ë®", clear_transdtl},
+ {"8.ÔÚÏßÉý¼¶", manual_upgrade},
+ {"9.»Ö¸´³ö³§", reset_factory}
+ };
+ max_cnt = sizeof(menus)/sizeof(menu_t)/3;
+ page = 0;
+ ticker = sp_get_ticker();
+ while(sp_get_ticker()-ticker <= DELAY_TIME60s*5)
+ {
+ sp_feed_dog();
+ keycode = sp_get_key();
+ if(keycode != SP_KEY_NONE)
+ {
+ key_press = 1;
+ switch(keycode)
+ {
+ case SP_KEY_0:
+ if(page < (max_cnt-1))
+ {
+ page++;
+ }
+ break;
+ case SP_KEY_1:
+ case SP_KEY_2:
+ case SP_KEY_3:
+ case SP_KEY_4:
+ case SP_KEY_5:
+ case SP_KEY_6:
+ case SP_KEY_7:
+ case SP_KEY_8:
+ case SP_KEY_9:
+ if(menus[keycode-SP_KEY_1].func != NULL)
+ {
+ menus[keycode-SP_KEY_1].func(pos);
+ }
+ break;
+ case SP_KEY_CLEAR:
+ if(page == 0)
+ {
+ return;
+ }
+ page--;
+ break;
+ default:
+ break;
+ }
+ }
+ if(key_press)
+ {
+ disp_hint_info_three(pos, menus[page*3].hit, menus[page*3+1].hit, menus[page*3+2].hit, 0);
+ key_press = 0;
+ ticker = sp_get_ticker();
+ }
+ }
+}
diff --git a/supwisdom/sp_menu.h b/supwisdom/sp_menu.h
new file mode 100644
index 0000000..75f8f32
--- /dev/null
+++ b/supwisdom/sp_menu.h
@@ -0,0 +1,8 @@
+#ifdef _SP_MENU_H_
+#define _SP_MENU_H_
+
+#include "sp_config.h"
+
+void sp_menu_options(sp_pos_t* pos);
+
+#endif
diff --git a/supwisdom/sp_msgpack.c b/supwisdom/sp_msgpack.c
new file mode 100644
index 0000000..d1258a9
--- /dev/null
+++ b/supwisdom/sp_msgpack.c
@@ -0,0 +1,87 @@
+#include "string.h"
+#include "sp_msgpack.h"
+
+int32 sp_pack_init(cw_pack_context* pack,uint8* buf,uint16 len)
+{
+ memset(buf,0,len);
+ return cw_pack_context_init(pack,buf,len,0);
+}
+
+uint16 sp_pack_length(cw_pack_context* pack)
+{
+ if(pack->current != NULL && pack->start != NULL)
+ {
+ return (pack->current -pack->start);
+ }
+ return 256;
+}
+void sp_pack_put_str(cw_pack_context* pack,const char* parakey,const char* paraval)
+{
+ cw_pack_str(pack,parakey,strlen(parakey));
+ cw_pack_str(pack,paraval,strlen(paraval));
+}
+void sp_pack_put_int(cw_pack_context* pack,const char* parakey,const int paraval)
+{
+ cw_pack_str(pack,parakey,strlen(parakey));
+ cw_pack_signed(pack,paraval);
+}
+void sp_pack_put_bin(cw_pack_context* pack,const char* parakey,const uint8* paraval,
+ const uint16 len)
+{
+ cw_pack_str(pack,parakey,strlen(parakey));
+ cw_pack_bin(pack,paraval,len);
+}
+int32 sp_unpack_init(cw_unpack_context* unpack,uint8* buf,uint16 len)
+{
+ cw_unpack_context_init(unpack,buf,len,0);
+ return unpack->return_code;
+}
+
+uint8 sp_unpack_map_size(cw_unpack_context* unpack)
+{
+ cw_unpack_next(unpack);
+ if(unpack->item.type == CWP_ITEM_MAP)
+ {
+ return (uint8)unpack->item.as.map.size;
+ }
+ return 0;
+}
+
+uint8 sp_unpack_value(cw_unpack_context* unpack,unpack_field_t* field)
+{
+ cw_unpack_next(unpack);
+ if(unpack->item.type == CWP_ITEM_STR)
+ {
+ field->key = unpack->item.as.str.start;
+ cw_unpack_next(unpack);
+ if(unpack->item.type == CWP_ITEM_STR)
+ {
+ field->val.strval = unpack->item.as.str.start;
+ field->strlen = unpack->item.as.str.length;
+ return 0;
+ }
+ else if(unpack->item.type == CWP_ITEM_POSITIVE_INTEGER)
+ {
+ field->val.intval= (int32)unpack->item.as.i64;
+ field->strlen = 0;
+ return 0;
+ }
+ else if(unpack->item.type == CWP_ITEM_BIN)
+ {
+ field->val.binval = unpack->item.as.str.start;
+ field->strlen = unpack->item.as.str.length;
+ return 0;
+ }
+ else
+ {
+ field->strlen = 0;
+ field->val.intval = 0;
+ return 1;
+ }
+ }
+ return 1;
+}
+
+
+
+
diff --git a/supwisdom/sp_msgpack.h b/supwisdom/sp_msgpack.h
new file mode 100644
index 0000000..c07a021
--- /dev/null
+++ b/supwisdom/sp_msgpack.h
@@ -0,0 +1,40 @@
+#ifndef _SP_MSGPACK_H_
+#define _SP_MSGPACK_H_
+
+
+#include "../msgpack/cwpack.h"
+#include "sp_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+ const char* key;
+ union
+ {
+ int32 intval;
+ const char* strval;
+ const uint8* binval;
+ } val;
+ int32 strlen;
+} unpack_field_t;
+
+int32 sp_pack_init(cw_pack_context* pack,uint8* buf,uint16 len);
+void sp_pack_put_str(cw_pack_context* pack,const char* parakey,const char* paraval);
+void sp_pack_put_int(cw_pack_context* pack,const char* parakey,const int paraval);
+void sp_pack_put_bin(cw_pack_context* pack,const char* parakey,const uint8* paraval,
+ const uint16 len);
+uint16 sp_pack_length(cw_pack_context* pack);
+
+int32 sp_unpack_init(cw_unpack_context* unpack,uint8* buf,uint16 len);
+uint8 sp_unpack_map_size(cw_unpack_context* unpack);
+uint8 sp_unpack_value(cw_unpack_context* unpack,unpack_field_t* field);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/supwisdom/sp_upgrade.c b/supwisdom/sp_upgrade.c
new file mode 100644
index 0000000..6f2fdb8
--- /dev/null
+++ b/supwisdom/sp_upgrade.c
@@ -0,0 +1,416 @@
+#include "sp_msgpack.h"
+#include "sp_flash.h"
+#include "sp_util.h"
+#include "sp_display.h"
+#include "sp_communicate.h"
+#include "sp_upgrade.h"
+
+extern uint16 crc_table[];
+
+#pragma pack(push)
+#pragma pack(1)
+typedef struct
+{
+ uint32 file_size;
+ uint8 file_crc[2];
+ uint8 file_md5[16];
+} sp_upgrade_info_t;
+#pragma pack(pop)
+
+/*
+**************************************************************************************************************
+* CRC У Ñé
+* Ãè Êö: УÑéÒ»´®charÊý¾ÝµÄCRC
+*
+* Êä Èë: CPU_CHAR *str - ҪУÑéÊý¾ÝµÄÖ¸Õë
+* CPU_INT16U size - ҪУÑéÊý¾ÝµÄ³¤¶È
+* CPU_INT08U mode - УÑéµÄģʽ
+* 1: Ϊ¸Ã´®Êý¾ÝÔö¼ÓCRCУÑé ͬʱ·µ»ØУÑéµÄCRCÖµ
+* 0: ¸Ã´®Êý¾ÝÊÇ·ñͨ¹ýУÑé ·µ»ØУÑéµÄCRCÖµ
+* ᵠȯ:
+*
+* ×¢ Òâ:
+*
+**************************************************************************************************************
+*/
+//CRCʹÓÃ
+typedef struct
+{
+ uint8 L;
+ uint8 H;
+} INT_08BIT_2;
+
+typedef union
+{
+ uint16 Int16Bit;
+ INT_08BIT_2 Int08Bit;
+} INT_16BIT_08BIT;
+
+uint16 AH_CRC_Verify(uint8 str[], uint16 size, uint8 mode)
+{
+ uint32 i;
+ INT_16BIT_08BIT crc;
+ INT_16BIT_08BIT y;
+
+ crc.Int16Bit = 0;
+ for(i = 0 ; i < size ; i++)
+ {
+ y.Int16Bit = crc_table[ str[ i ] ^ crc.Int08Bit.H ];
+ y.Int08Bit.H ^= crc.Int08Bit.L;
+ crc.Int16Bit = y.Int16Bit;
+ }
+ if(mode == 1)
+ {
+ str[ i++ ] = y.Int08Bit.H ;
+ str[ i ] = y.Int08Bit.L ;
+ }
+ return(crc.Int16Bit);
+}
+
+static uint16 update_upgrade_mark(uint32 CheckSum, uint32 size)
+{
+ uint16 ret,i;
+ uint8 buff[18] = { 0x5a,0x4b,0x3c,0x2d,0x1e,0x0f } ;
+
+ //дÉý¼¶Êý¾Ý³É¹¦Ð´ÈëFLASH±ê¼Ç, ºÍУÑéÂë, ÓÐЧ´úÂ볤¶ÈдÈëÊý¾ÝFLASH
+ memcpy(buff+6, (unsigned char*)&(CheckSum), 4) ; //УÑéºÍ
+ memcpy(buff+10,(unsigned char*)&(size) ,4) ; //Êý¾Ý³¤¶È
+ AH_CRC_Verify(buff, 14, 1);
+
+ for(i = 0; i<5; i++)
+ {
+ ret = sp_flash_erase(DEF_IapMarkAddr);
+ if(ret)
+ {
+ continue;
+ }
+ ret = sp_flash_write(DEF_IapMarkAddr, buff, 16);
+ if(!ret)
+ {
+ break;
+ }
+ }
+ if(i >= 5)
+ {
+ return 1;
+ }
+ return 0;
+}
+/**********************************************************************************************
+º¯ÊýÃû³Æ: U32 APP_IapDataSumCheck( U32 staaddr, U32 len, U08 mode )
+º¯Êý×÷ÓÃ: ¶Á³öFLASHÖеÄÊý¾Ý£¬²¢ÐγÉУÑé
+º¯ÊýÊäÈë: staaddr - ¿ªÊ¼µØÖ·
+ len - Êý¾Ý³¤¶È
+ mode - УÑéģʽ 0 È¡·´ºÍУÑé 1 ÆÕͨºÍУÑé
+º¯ÊýÊä³ö: ÎÞ
+º¯Êý·µ»ØÖµ: 0 ³É¹¦ ÆäËûʧ°Ü
+**********************************************************************************************/
+uint32 do_APP_IapDataSumCheck(uint32 staaddr, uint32 len, uint8 mode)
+{
+ uint32 Sum;
+ uint32 app_len, checksize, size;
+ uint16 rcode, i;
+ uint8 buffer[1024];//IAP_MAXLEN
+
+ app_len = len;
+ checksize = 0;
+ Sum = 0;
+ while(checksize < app_len)
+ {
+ if(len < 1024)
+ {
+ size = len;
+ }
+ else
+ {
+ size = 1024;
+ }
+
+ for(i=0; i<5; i++)
+ {
+ rcode = sp_flash_read((staaddr + checksize), buffer, size);
+ if(!rcode)
+ {
+ break;
+ }
+ }
+
+ if(mode == 0)
+ {
+ for(i = 0; i < size; i++)
+ {
+ Sum += ((~buffer[i]) & 0xFF); //еÄÊÇÈ¡·´ºÍ
+ }
+ }
+ else
+ {
+ for(i = 0; i < size; i++)
+ {
+ Sum += buffer[i]; //ÀϵÄÊÇÖ±½ÓºÍ
+ }
+ }
+ checksize += size;
+ len -= size;
+ }
+
+ return (Sum);
+}
+static uint8 get_file_info(sp_pos_t* pos, sp_upgrade_info_t* upgradeinfo)
+{
+ uint8 ret;
+ uint8 size;
+ char temp[32];
+ sp_protocol_request_t req;
+ sp_protocol_response_t resp;
+ cw_pack_context pack;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+
+ sp_flash_read(ADDR_UPGRADE_UPINFO,(uint8*)upgradeinfo,sizeof(sp_upgrade_info_t));
+
+ /*¶ÁÈ¡Îļþ³¤¶ÈºÍCRC*/
+ sp_protocol_req_init(&req,SP_CMD_UPGRADE);
+ sp_pack_init(&pack,req.data,sizeof(req.data));
+ cw_pack_map_size(&pack,5);
+
+ sp_pack_put_bin(&pack,PK_BIN_DEVPHYID, pos->devphyid, sizeof(pos->devphyid));
+ sp_pack_put_int(&pack,PK_INT_SEQNO ,0xFFFF);
+ sp_pack_put_str(&pack,PK_STR_DEVTYPE, DEV_TYPE);
+ sp_pack_put_str(&pack,PK_STR_VERSION, PRO_VERSION);
+ sp_pack_put_bin(&pack,PK_BIN_SOFT_MD5,upgradeinfo->file_md5,16);
+
+ req.datalen += sp_pack_length(&pack);
+ ret = sp_comm_call(pos, &req, &resp, COMM_WAIT_TIME);
+ if(!ret)
+ {
+ sp_unpack_init(&unpack,resp.data,resp.datalen);
+ //erase
+ sp_flash_erase(ADDR_UPGRADE_UPINFO);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ // 4 byte file_length,2 crc
+ if(IS_KEY(PK_INT_FILESIZE,field.key))
+ {
+ upgradeinfo->file_size = (uint32)field.val.intval;
+ }
+ else if(IS_KEY(PK_BIN_FILECRC,field.key))
+ {
+ if(field.strlen != 2)
+ {
+ sprintf(temp,"CRC³¤¶È=%d",field.strlen);
+ disp_hint_info_two(pos, "Éý¼¶Ê§°Ü",temp,DELAY_TIME3s);
+ return 1;
+ }
+ MEMCPY(upgradeinfo->file_crc,field.val.binval,field.strlen);
+ }
+ else if(IS_KEY(PK_BIN_SOFT_MD5,field.key))
+ {
+ MEMCPY(upgradeinfo->file_md5,field.val.binval,field.strlen);
+ }
+ }
+ }
+ else
+ {
+ disp_server_errmsg(pos, "Éý¼¶Ê§°Ü",resp.data,resp.datalen);
+ }
+ return ret;
+}
+static uint8 download_file(sp_pos_t* pos)
+{
+ uint8 ret;
+ uint8 timeout_trycnt = 0;
+ uint8 sameseq_trycnt = 0;
+ uint8 data_len = 0;
+ uint16 seqno = 0;
+ uint16 resp_seqno = 0;
+ uint32 offset = 0;
+ uint8 endflag = 0;
+ uint8 size;
+ char temp[32];
+ uint8 buf[128];
+ sp_protocol_request_t req;
+ sp_protocol_response_t resp;
+ cw_pack_context pack;
+ cw_unpack_context unpack;
+ unpack_field_t field;
+
+ for(offset = ADDR_UPGRADE_BEGIN; offset < ADDR_UPGRADE_END; offset +=DEF_FLASH_PageSize)
+ {
+ sp_flash_erase(offset);
+ }
+ offset = 0;
+ while(1)
+ {
+ sp_feed_dog();
+ sp_protocol_req_init(&req,SP_CMD_UPGRADE);
+ sp_pack_init(&pack,req.data,sizeof(req.data));
+ cw_pack_map_size(&pack,2);
+
+ sp_pack_put_bin(&pack,PK_BIN_DEVPHYID, pos->devphyid, sizeof(pos->devphyid));
+ sp_pack_put_int(&pack,PK_INT_SEQNO,seqno);
+
+ req.datalen += sp_pack_length(&pack);
+ ret = sp_comm_call(pos, &req,&resp, COMM_WAIT_TIME);
+ if(!ret)
+ {
+ timeout_trycnt = 0;//success reset
+ sp_unpack_init(&unpack,resp.data,resp.datalen);
+ size = sp_unpack_map_size(&unpack);
+ while(size-- > 0)
+ {
+ sp_unpack_value(&unpack,&field);
+ if(IS_KEY(PK_INT_SEQNO,field.key))
+ {
+ resp_seqno = (uint32)field.val.intval;
+ }
+ else if(IS_KEY(PK_INT_FLAG,field.key))
+ {
+ if(0 == MEMCMP("end",field.val.strval,field.strlen))
+ {
+ // ÎļþÏÂÔØÍê³É
+ endflag = 1;
+ }
+ }
+ else if(IS_KEY(PK_BIN_FILEDATA,field.key))
+ {
+ data_len = field.strlen;
+ if(data_len > sizeof(buf))
+ {
+ sprintf(temp,"´íÎ󳤶È=%d",data_len);
+ disp_hint_info_two(pos, "Éý¼¶Ê§°Ü",temp,DELAY_TIME3s);
+ return 1;
+ }
+ MEMCLEAR(buf,sizeof buf);
+ MEMCPY(buf,field.val.binval,data_len);
+ }
+ }
+
+ if(resp_seqno != seqno +1)
+ {
+ if(10 < sameseq_trycnt)
+ {
+ return 1;
+ }
+ ++sameseq_trycnt;
+ continue;
+ }
+ sameseq_trycnt = 0;
+
+ ++seqno;
+ snprintf(temp,sizeof temp,"seqno = %04d",seqno);
+ disp_hint_info_two(pos, "ÕýÔÚÉý¼¶...",temp,0);
+
+ sp_flash_write(ADDR_UPGRADE_BEGIN+offset,buf,data_len);
+ if(endflag)
+ {
+ return 0;
+ }
+
+ offset += (uint32)data_len;
+ if(ADDR_UPGRADE_BEGIN + offset >= ADDR_UPGRADE_END)
+ {
+ disp_hint_info(pos, "ÏÂÔØÎļþ¹ý´ó",DELAY_TIME3s);
+ return 1;
+ }
+ }
+ else
+ {
+ if(3 < timeout_trycnt)
+ {
+ disp_hint_info(pos, "ÏÂÔØÎļþ³¬Ê±",DELAY_TIME3s);
+ return 1;
+ }
+ Delay_ms(DELAY_TIME1s);
+ ++timeout_trycnt;
+ }
+ }
+}
+static uint8 check_file_and_upgrade(sp_pos_t* pos, sp_upgrade_info_t* upgradeinfo)
+{
+ uint16 ret;
+ uint8 crc[2];
+ uint8 temp_crc[2];
+ uint8 buf[128];
+ uint32 sumcrc;
+
+ uint32 page_index = 0;
+ uint32 page_num = (upgradeinfo->file_size-1)/sizeof(buf) + 1;
+ while(1)
+ {
+ if(page_num == page_index +1)
+ {
+ sp_flash_read(ADDR_UPGRADE_BEGIN +page_index*sizeof(buf),buf,
+ sizeof buf);
+ memcpy(temp_crc,crc,2);
+ if(upgradeinfo->file_size%sizeof(buf) == 0)
+ {
+ sp_protocol_crc_init(buf,sizeof(buf),temp_crc,crc);
+ }
+ else
+ {
+ sp_protocol_crc_init(buf,upgradeinfo->file_size%sizeof(buf),temp_crc,crc);
+ }
+ if(0 == MEMCMP(upgradeinfo->file_crc,crc,2))
+ {
+ sp_flash_write(ADDR_UPGRADE_UPINFO,(uint8*)upgradeinfo,sizeof(sp_upgrade_info_t));
+
+ sumcrc = do_APP_IapDataSumCheck(ADDR_UPGRADE_BEGIN,upgradeinfo->file_size,0);
+ /*Éý¼¶ºó,boot »á²Á³ý¸ÃÒ³¼Ç¼ */
+ //¸üбê־λÖÃλ
+ ret = update_upgrade_mark(sumcrc,upgradeinfo->file_size);
+ if(ret)
+ {
+ disp_hint_info_two(pos, "Éý¼¶Ê§°Ü","¸üбê־ʧ°Ü",DELAY_TIME2s);
+ return 1;
+ }
+ else
+ {
+ disp_hint_info_two(pos, "ÕýÔÚÉý¼¶","ÇëÎð¶Ïµç",DELAY_TIME2s);
+ sp_reset();
+ return 0;
+ }
+ }
+ else
+ {
+ disp_hint_info(pos, "ÎļþУÑé´íÎó",DELAY_TIME3s);
+ return 1;
+ }
+ }
+ else
+ {
+ sp_flash_read(ADDR_UPGRADE_BEGIN+page_index*sizeof(buf),buf,sizeof buf);
+ if(0 == page_index)
+ {
+ sp_protocol_crc(buf,sizeof buf,crc);
+ }
+ else
+ {
+ memcpy(temp_crc,crc,2);
+ sp_protocol_crc_init(buf,sizeof buf,temp_crc,crc);
+ }
+ ++page_index;
+ }
+ }
+}
+void sp_manual_upgrade(sp_pos_t* pos)
+{
+ uint8 ret;
+ sp_upgrade_info_t upgradeinfo;
+
+ disp_hint_info_two(pos, "ÕýÔÚÉý¼¶..","Îð¶Ïµç!!",0);
+ MEMCLEAR(&upgradeinfo,sizeof upgradeinfo);
+ ret = get_file_info(pos, &upgradeinfo);
+ if(ret)
+ {
+ return;
+ }
+ ret = download_file(pos);
+ if(ret)
+ {
+ return;
+ }
+ check_file_and_upgrade(pos, &upgradeinfo);
+}
+
diff --git a/supwisdom/sp_upgrade.h b/supwisdom/sp_upgrade.h
new file mode 100644
index 0000000..2cd8160
--- /dev/null
+++ b/supwisdom/sp_upgrade.h
@@ -0,0 +1,14 @@
+#ifndef _SP_UPGRADE_H_
+#define _SP_UPGRADE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void sp_manual_upgrade(sp_pos_t* pos);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/supwisdom/sp_util.c b/supwisdom/sp_util.c
new file mode 100644
index 0000000..df70b13
--- /dev/null
+++ b/supwisdom/sp_util.c
@@ -0,0 +1,530 @@
+#include "../sys_hw/keypad.h"
+#include "../sys_hw/drv_adc.h"
+#include "sp_display.h"
+
+#include "sp_util.h"
+
+uint16 crc_table[] =
+{
+ 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+ 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+ 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+ 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+ 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+ 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+ 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+ 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+ 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+ 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+ 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+ 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+ 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+ 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+ 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+ 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+ 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+ 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+ 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+ 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+ 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+ 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+ 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+ 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+ 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+ 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
+};
+
+void sp_protocol_crc(const uint8* buf, uint16 len, uint8 crc[2])
+{
+ //uint16 accnum = 0xc78c;
+ uint8 temp_crc[2];
+ temp_crc[0] = 0xc7;
+ temp_crc[1] = 0x8c;
+ sp_protocol_crc_init(buf,len,temp_crc,crc);
+}
+
+void sp_protocol_crc_init(const uint8* buf, uint16 len,uint8 init[2], uint8 crc[2])
+{
+ uint16 accnum = (uint16)init[0]<<8 |(uint16)init[1];
+ uint16 i;
+ for(i = 0; i < len; ++i)
+ {
+ accnum = (accnum << 8) ^ crc_table[((accnum >> 8)
+ ^ buf[i]) & 0xFF];
+ }
+ crc[0] = (uint8)((accnum >> 8) & 0xFF);
+ crc[1] = (uint8)(accnum & 0xFF);
+}
+
+void sp_key_calibrate(void)
+{
+ calibrate_key(0);
+}
+
+uint8 sp_key_init(void)
+{
+ adc_init();
+ return keypad_init();
+}
+uint8 sp_get_key(void)
+{
+ uint8 key = keypad_get_key();
+ switch(key)
+ {
+ case KEY_NONE:
+ return SP_KEY_NONE;
+ case KEY_DIG0:
+ return SP_KEY_0;
+ case KEY_DIG1:
+ return SP_KEY_1;
+ case KEY_DIG2:
+ return SP_KEY_2;
+ case KEY_DIG3:
+ return SP_KEY_3;
+ case KEY_DIG4:
+ return SP_KEY_4;
+ case KEY_DIG5:
+ return SP_KEY_5;
+ case KEY_DIG6:
+ return SP_KEY_6;
+ case KEY_DIG7:
+ return SP_KEY_7;
+ case KEY_DIG8:
+ return SP_KEY_8;
+ case KEY_DIG9:
+ return SP_KEY_9;
+ case KEY_ENTER:
+ return SP_KEY_ENTER;
+ case KEY_CANCEL:
+ return SP_KEY_CLEAR;
+ default:
+ return SP_KEY_NONE;
+ }
+}
+void sp_reset(void)
+{
+ while(1);
+}
+void sp_bcd_to_str(const uint8* bcd, uint8 bcd_len, char* str)
+{
+ uint8 i;
+ uint16 j;
+ for(i = 0; i < bcd_len; ++i)
+ {
+ j = i << 1;
+ str[j] = ((bcd[i] >> 4) & 0x0F) + 0x30;
+ str[j + 1] = (bcd[i] & 0x0F) + 0x30;
+ }
+ str[i << 1] = 0;
+}
+void sp_str_to_bcd(const char* str, uint8 str_len, uint8* bcd)
+{
+ uint8 i,j;
+ for(i = 0; i < str_len; i += 2)
+ {
+ j = i/2;
+ bcd[j] = (((str[i]-0x30) & 0x0F) <<4) | ((str[i+1]-0x30) & 0x0F);
+ }
+}
+static uint8 charTohex(char ch)
+{
+ if(ch >= '0' && ch <= '9')
+ {
+ return (ch -'0');
+ }
+ if(ch >= 'a' && ch <= 'f')
+ {
+ return (ch -'a' +10);
+ }
+ if(ch >= 'A' && ch <= 'F')
+ {
+ return (ch -'A' +10);
+ }
+ return 0;
+}
+void sp_str_to_hex(const char* str,const uint16 len,uint8* hex)
+{
+ uint8 t,temp;
+ uint16 i;
+ for(i = 0; i < len; i += 2)
+ {
+ temp = charTohex(str[i]);
+ t = temp << 4;
+ temp = charTohex(str[i+1]);
+ t += temp;
+ hex[i/2] = t;
+ }
+}
+
+static char hexToCharTable[]= {"0123456789ABCDEF"};
+void sp_hex_to_str(const uint8* hex,const uint8 len,char* str)
+{
+ uint8 i,j;
+ for(i = 0; i < len; i++)
+ {
+ j = i << 1;
+ str[j] = hexToCharTable[(hex[i] >> 4) &0x0F];
+ str[j +1] = hexToCharTable[hex[i] &0x0F];
+ }
+ str[i << 1] = 0;
+}
+
+void sp_get_bcdtime(uint8 ctime[6])
+{
+ _SystemTime time;
+ memset(&time,0,sizeof time);
+ rtc_get_time(&time); //bcd
+ ctime[0] = time.year;
+ ctime[1] = time.month;
+ ctime[2] = time.day;
+ ctime[3] = time.hour;
+ ctime[4] = time.minute;
+ ctime[5] = time.second;
+}
+void sp_set_bcdtime(uint8 ctime[6])
+{
+ _SystemTime time;
+ memset(&time,0,sizeof time);
+ time.year = ctime[0];
+ time.month = ctime[1];
+ time.day = ctime[2];
+ time.hour = ctime[3];
+ time.minute = ctime[4];
+ time.second = ctime[5];
+
+ rtc_set_time(&time);
+}
+uint8 sp_check_time_valid(uint8 ctime[6])
+{
+ if(BCD2Dec(ctime[0]) < 18)
+ return 1;
+ if(BCD2Dec(ctime[1]) > 12)
+ return 1;
+ if(BCD2Dec(ctime[2]) > 31)
+ return 1;
+ if(BCD2Dec(ctime[3]) > 23)
+ return 1;
+ if(BCD2Dec(ctime[4]) > 59)
+ return 1;
+ if(BCD2Dec(ctime[5]) > 59)
+ return 1;
+
+ return 0;
+}
+uint8 sp_crc_sum(uint8 buf[],uint8 len)
+{
+ uint8 i;
+ uint8 sum = 0;
+ //¼ÆËãУÑéºÍ
+ for(i = 0; i < len; i++)
+ {
+ sum = sum + buf[i];
+ }
+ return sum;
+}
+
+int8 isFF(uint8 buf[],uint16 len)
+{
+ uint16 i;
+ for(i = 0; i < len; i++)
+ {
+ if(0xFF != buf[i])
+ {
+ return -1;
+ }
+ }
+ return 0;
+}
+
+//ms
+uint32 sp_get_ticker(void)
+{
+ return timer_get_ticker();
+}
+
+void Delay_ms(uint32 ms)
+{
+ uint32 t = sp_get_ticker();
+ while(sp_get_ticker() - t < ms);
+}
+void sp_valve_on(void)
+{
+ valve_sta_set(valve_state_on);
+ valve_ctrl();
+}
+void sp_valve_off(void)
+{
+ valve_sta_set(valve_state_off);
+ valve_ctrl();
+}
+uint8 sp_valve_state(void)
+{
+ return valve_sta_get();
+}
+
+int16 get_2byte_int(uint8 value_str[2])
+{
+ int32 r = 0, t = 0;
+ t = value_str[0];
+ r = t << 8;
+ r |= value_str[1];
+ return (int16)r;
+}
+int32 get_3byte_int(uint8 value_str[3])
+{
+ int32 r = 0, t = 0;
+ t = value_str[0];
+ r = t << 16;
+ t = value_str[1];
+ r |= t << 8;
+ r |= value_str[2];
+ return r;
+}
+int32 get_4byte_int(uint8 value_str[4])
+{
+ int32 r = 0, t = 0;
+ t = value_str[0];
+ r = t << 24;
+ t = value_str[1];
+ r |= t << 16;
+ t = value_str[2];
+ r |= t << 8;
+ r |= value_str[3];
+ return r;
+}
+void set_2byte_int(uint8 value_str[2], int num)
+{
+ value_str[0] = (num >> 8) & 0xFF;
+ value_str[1] = num & 0xFF;
+}
+void set_3byte_int(uint8 value_str[3], int num)
+{
+ value_str[0] = (num >> 16) & 0xFF;
+ value_str[1] = (num >> 8) & 0xFF;
+ value_str[2] = num & 0xFF;
+}
+void set_4byte_int(uint8 value_str[4], int num)
+{
+ value_str[0] = (num >> 24) & 0xFF;
+ value_str[1] = (num >> 16) & 0xFF;
+ value_str[2] = (num >> 8) & 0xFF;
+ value_str[3] = num & 0xFF;
+}
+
+//»ñµÃµ¥×Ö½ÚÖÐijһλµÄÖµ
+int32 Get1Bit(uint8 buf, int n)
+{
+ return (buf >> n) & 0x01;
+}
+
+int16 get_2byte_int_le(uint8 value_str[2])
+{
+ int32 r = 0, t = 0;
+ t = value_str[1];
+ r = t << 8;
+ r |= value_str[0];
+ return (int16)r;
+}
+//С×Ö½ÚÐò
+int32 get_3byte_int_le(uint8 value_str[3])
+{
+ int32 r = 0, t = 0;
+ t = value_str[2];
+ r = t << 16;
+ t = value_str[1];
+ r |= t << 8;
+ r |= value_str[0];
+ return r;
+}
+//С×Ö½ÚÐò
+int32 get_4byte_int_le(uint8 value_str[4])
+{
+ int32 r = 0, t = 0;
+ t = value_str[3];
+ r = t << 24;
+ t = value_str[2];
+ r |= t << 16;
+ t = value_str[1];
+ r |= t << 8;
+ r |= value_str[0];
+ return r;
+}
+
+void set_2byte_int_le(uint8 value_str[2], int num)
+{
+ value_str[1] = (num >> 8) & 0xFF;
+ value_str[0] = num & 0xFF;
+}
+
+void set_3byte_int_le(uint8 value_str[3], int num)
+{
+ value_str[2] = (num >> 16) & 0xFF;
+ value_str[1] = (num >> 8) & 0xFF;
+ value_str[0] = num & 0xFF;
+}
+
+/*¼ÆËã´Óbcd starttime µ½ÏÖÔÚµÄÃëÊý*/
+uint32 diff_time(uint8 starttime[6])
+{
+ uint8 ctime[6];
+ uint32 start_second;
+ uint32 end_second;
+
+ sp_get_bcdtime(ctime);
+ start_second = format_time_covert_secs(starttime);
+ end_second = format_time_covert_secs(ctime);
+ if(end_second < start_second)
+ {
+ return 0;
+ }
+ return (end_second - start_second);
+}
+
+void mycpy(void* dest, const void* src, uint32 len)
+{
+ char* tmp_dest = (char*)dest;
+ char* tmp_src = (char*)src;
+ while(len--)
+ {
+ *tmp_dest = *tmp_src++;
+ tmp_dest++;
+ }
+}
+
+void sp_bcd2asc(const uint8 bcdbuf[], uint8 bcdlen, uint8* ascstr)
+{
+ uint8 i;
+ uint8 lch, hch;
+ for(i = 0; i < bcdlen; i++)
+ {
+ hch = (bcdbuf[i] & 0x0F);
+ lch = (bcdbuf[i] & 0xF0);
+ lch = lch >> 4;
+ ascstr[2 * i] = lch + '0';
+ ascstr[2 * i + 1] = hch + '0';
+ }
+ ascstr[2*i] = 0;
+}
+int32 sp_atoi(const char* src)
+{
+ int i = 0;
+ while(*src != 0)
+ {
+ i = i * 10 + *src - '0';
+ src++;
+ }
+ return i;
+}
+/**
+**2000.0.0:0.0.0ʱ¼äΪ»ùÊý
+**/
+static int MINUTE_SECS = 60;
+static int HOUR_SECS = 3600;
+static int DAY_SECS = 24*3600;
+static int YEAR_SECS = 365*24*3600;
+static int FOURYEAR_SECS = (365*3+366)*24*3600;
+static int norMoth[] = {0,31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
+static int leapMoth[] = {0,31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
+/*time: string(yyyyMMddHHmmss) to int */
+int format_time_covert_secs(uint8 ctime[6])
+{
+ int secs;
+ int i;
+ int remain;
+ int year = BCD2Dec(ctime[0]);
+ int month = BCD2Dec(ctime[1]);
+ int day = BCD2Dec(ctime[2]);
+ int hour = BCD2Dec(ctime[3]);
+ int minute = BCD2Dec(ctime[4]);
+ int second = BCD2Dec(ctime[5]);
+
+ secs = year/4 *FOURYEAR_SECS;
+ remain = year%4;
+ secs += remain*YEAR_SECS;
+
+ if(remain == 0)
+ {
+ for(i = 0; i < month; ++i)
+ {
+ secs += leapMoth[i] *DAY_SECS;
+ }
+ }
+ else
+ {
+ for(i = 0; i < month; ++i)
+ {
+ secs += norMoth[i] *DAY_SECS;
+ }
+ }
+ secs += day*DAY_SECS;
+ secs += hour *HOUR_SECS;
+ secs += minute*MINUTE_SECS;
+ secs += second;
+ return secs;
+}
+
+uint8 sp_check_passwd(sp_pos_t* pos,const char* hint,uint8 passwd[6])
+{
+ uint8 temp[6];
+ uint8 offset = 0;
+ uint8 kcode;
+ uint32 ticker = sp_get_ticker();
+
+ show_manage_passwd(pos,hint,temp,offset);
+ while(sp_get_ticker() -ticker < DELAY_TIME60s)
+ {
+ sp_feed_dog();
+ kcode = sp_get_key();
+ if(kcode != SP_KEY_NONE)
+ {
+ switch(kcode)
+ {
+ case SP_KEY_0:
+ case SP_KEY_1:
+ case SP_KEY_2:
+ case SP_KEY_3:
+ case SP_KEY_4:
+ case SP_KEY_5:
+ case SP_KEY_6:
+ case SP_KEY_7:
+ case SP_KEY_8:
+ case SP_KEY_9:
+ if(offset < 6)
+ {
+ temp[offset++] = (uint8)(kcode-SP_KEY_0);
+ show_manage_passwd(pos,hint,temp,offset);
+ }
+ if(offset >= 6)
+ {
+ if(0 == MEMCMP(temp,passwd,6))
+ {
+ return 0;
+ }
+ else
+ {
+ disp_hint_info_two(pos,hint,"ÃÜÂë´íÎó",DELAY_TIME2s);
+ MEMCLEAR(temp, sizeof temp);
+ offset = 0;
+ }
+ }
+ break;
+ case SP_KEY_CLEAR:
+ if(offset == 0)
+ {
+ return 1;
+ }
+ --offset;
+ temp[offset] = 0;
+ show_manage_passwd(pos,hint,temp,offset);
+ break;
+ }
+ }
+ }
+ return 1;
+}
diff --git a/supwisdom/sp_util.h b/supwisdom/sp_util.h
new file mode 100644
index 0000000..d54b929
--- /dev/null
+++ b/supwisdom/sp_util.h
@@ -0,0 +1,70 @@
+#ifndef _SP_UTIL_H_
+#define _SP_UTIL_H_
+
+#include "string.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "sp_config.h"
+
+#define DELAY_TIME100ms 100
+#define DELAY_TIME200ms 200
+#define DELAY_TIME1s 1000
+#define DELAY_TIME2s 2000
+#define DELAY_TIME3s 3000
+#define DELAY_TIME15s 15000
+#define DELAY_TIME60s 60000
+#define COMM_WAIT_TIME 5000
+
+#define STR_COPY_N(x,y,z) do{snprintf(x,z+1,"%s",y);}while(0);
+#define MEMCLEAR(x,z) memset(x,0,z)
+#define MEMCMP(x,y,z) memcmp(x,y,z)
+#define MEMCPY(x,y,z) memcpy(x,y,z)
+#define IS_KEY(expect,val) (strncmp(expect,val,strlen(expect)) == 0)
+
+#define Dec2BCD(x) (((x) / 10) * 16 + (x) % 10)
+#define BCD2Dec(x) (((x) / 16) * 10 + (x) % 16)
+
+void sp_get_bcdtime(uint8 ctime[6]);
+void sp_set_bcdtime(uint8 ctime[6]);
+uint8 sp_check_time_valid(uint8 ctime[6]);
+uint8 sp_crc_sum(uint8 buf[],uint8 len);
+uint32 sp_get_ticker(void);
+void Delay_ms(uint32 ms);
+void sp_valve_on(void);
+void sp_valve_off(void);
+uint8 sp_valve_state(void);
+int16 get_2byte_int(uint8 value_str[2]);
+int32 get_3byte_int(uint8 value_str[3]);
+int32 get_4byte_int(uint8 value_str[4]);
+void set_2byte_int(uint8 value_str[2], int num);
+void set_3byte_int(uint8 value_str[3], int num);
+void set_4byte_int(uint8 value_str[4], int num);
+//»ñµÃµ¥×Ö½ÚÖÐijһλµÄÖµ
+int32 Get1Bit(uint8 buf, int n);
+int16 get_2byte_int_le(uint8 value_str[2]);
+//С×Ö½ÚÐò
+int32 get_3byte_int_le(uint8 value_str[3]);
+//С×Ö½ÚÐò
+int32 get_4byte_int_le(uint8 value_str[4]);
+void set_2byte_int_le(uint8 value_str[2], int num);
+void set_3byte_int_le(uint8 value_str[3], int num);
+/*¼ÆËã´Óstarttime µ½ÏÖÔÚµÄÃëÊý*/
+uint32 diff_time(uint8 starttime[6]);
+void mycpy(void* dest, const void* src, uint32 len);
+int32 sp_atoi(const char* src);
+void sp_bcd2asc(const uint8 bcdbuf[], uint8 bcdlen, uint8* ascstr);
+int format_time_covert_secs(uint8 ctime[6]);
+void sp_protocol_crc(const uint8* buf, uint16 len, uint8 crc[2]);
+void sp_protocol_crc_init(const uint8* buf, uint16 len,uint8 init[2], uint8 crc[2]);
+uint8 sp_get_key(void);
+uint8 sp_key_init(void);
+void sp_key_calibrate(void);
+void sp_reset(void);
+void sp_bcd_to_str(const uint8* bcd, uint8 bcd_len, char* str);
+void sp_str_to_bcd(const char* str, uint8 str_len, uint8* bcd);
+void sp_str_to_hex(const char* str,const uint16 len,uint8* hex);
+void sp_hex_to_str(const uint8* hex,const uint8 len,char* str);
+uint8 sp_check_passwd(sp_pos_t* pos,const char* hint,uint8 passwd[6]);
+int8 isFF(uint8 buf[],uint16 len);
+
+#endif
diff --git a/sys_hw/Crc.c b/sys_hw/Crc.c
new file mode 100644
index 0000000..1797439
--- /dev/null
+++ b/sys_hw/Crc.c
@@ -0,0 +1,83 @@
+#include "crc.h"
+
+static u16 const crc_table[] =
+{
+ //CRCTB1: ;?256??
+ 0x00000,0x01021,0x02042,0x03063,
+ 0x04084,0x050a5,0x060c6,0x070e7,
+ 0x08108,0x09129,0x0a14a,0x0b16b,
+ 0x0c18c,0x0d1ad,0x0e1ce,0x0f1ef,
+ 0x01231,0x00210,0x03273,0x02252,
+ 0x052b5,0x04294,0x072f7,0x062d6,
+ 0x09339,0x08318,0x0b37b,0x0a35a,
+ 0x0d3bd,0x0c39c,0x0f3ff,0x0e3de,
+ 0x02462,0x03443,0x00420,0x01401,
+ 0x064e6,0x074c7,0x044a4,0x05485,
+ 0x0a56a,0x0b54b,0x08528,0x09509,
+ 0x0e5ee,0x0f5cf,0x0c5ac,0x0d58d,
+ 0x03653,0x02672,0x01611,0x00630,
+ 0x076d7,0x066f6,0x05695,0x046b4,
+ 0x0b75b,0x0a77a,0x09719,0x08738,
+ 0x0f7df,0x0e7fe,0x0d79d,0x0c7bc,
+ 0x048c4,0x058e5,0x06886,0x078a7,
+ 0x00840,0x01861,0x02802,0x03823,
+ 0x0c9cc,0x0d9ed,0x0e98e,0x0f9af,
+ 0x08948,0x09969,0x0a90a,0x0b92b,
+ 0x05af5,0x04ad4,0x07ab7,0x06a96,
+ 0x01a71,0x00a50,0x03a33,0x02a12,
+ 0x0dbfd,0x0cbdc,0x0fbbf,0x0eb9e,
+ 0x09b79,0x08b58,0x0bb3b,0x0ab1a,
+ 0x06ca6,0x07c87,0x04ce4,0x05cc5,
+ 0x02c22,0x03c03,0x00c60,0x01c41,
+ 0x0edae,0x0fd8f,0x0cdec,0x0ddcd,
+ 0x0ad2a,0x0bd0b,0x08d68,0x09d49,
+ 0x07e97,0x06eb6,0x05ed5,0x04ef4,
+ 0x03e13,0x02e32,0x01e51,0x00e70,
+ 0x0ff9f,0x0efbe,0x0dfdd,0x0cffc,
+ 0x0bf1b,0x0af3a,0x09f59,0x08f78,
+ //CRCTB2: ;?256??
+ 0x09188,0x081a9,0x0b1ca,0x0a1eb,
+ 0x0d10c,0x0c12d,0x0f14e,0x0e16f,
+ 0x01080,0x000a1,0x030c2,0x020e3,
+ 0x05004,0x04025,0x07046,0x06067,
+ 0x083b9,0x09398,0x0a3fb,0x0b3da,
+ 0x0c33d,0x0d31c,0x0e37f,0x0f35e,
+ 0x002b1,0x01290,0x022f3,0x032d2,
+ 0x04235,0x05214,0x06277,0x07256,
+ 0x0b5ea,0x0a5cb,0x095a8,0x08589,
+ 0x0f56e,0x0e54f,0x0d52c,0x0c50d,
+ 0x034e2,0x024c3,0x014a0,0x00481,
+ 0x07466,0x06447,0x05424,0x04405,
+ 0x0a7db,0x0b7fa,0x08799,0x097b8,
+ 0x0e75f,0x0f77e,0x0c71d,0x0d73c,
+ 0x026d3,0x036f2,0x00691,0x016b0,
+ 0x06657,0x07676,0x04615,0x05634,
+ 0x0d94c,0x0c96d,0x0f90e,0x0e92f,
+ 0x099c8,0x089e9,0x0b98a,0x0a9ab,
+ 0x05844,0x04865,0x07806,0x06827,
+ 0x018c0,0x008e1,0x03882,0x028a3,
+ 0x0cb7d,0x0db5c,0x0eb3f,0x0fb1e,
+ 0x08bf9,0x09bd8,0x0abbb,0x0bb9a,
+ 0x04a75,0x05a54,0x06a37,0x07a16,
+ 0x00af1,0x01ad0,0x02ab3,0x03a92,
+ 0x0fd2e,0x0ed0f,0x0dd6c,0x0cd4d,
+ 0x0bdaa,0x0ad8b,0x09de8,0x08dc9,
+ 0x07c26,0x06c07,0x05c64,0x04c45,
+ 0x03ca2,0x02c83,0x01ce0,0x00cc1,
+ 0x0ef1f,0x0ff3e,0x0cf5d,0x0df7c,
+ 0x0af9b,0x0bfba,0x08fd9,0x09ff8,
+ 0x06e17,0x07e36,0x04e55,0x05e74,
+ 0x02e93,0x03eb2,0x00ed1,0x01ef0
+};
+
+u16 calcCRC( u8 *pBuffer, u16 BufferLength)
+{
+ u16 crc_reg = 0;
+
+ while (BufferLength--)
+ {
+ crc_reg = (crc_reg << 8) ^ crc_table[(crc_reg>>8) ^ *pBuffer++];
+ }
+
+ return crc_reg;
+}
diff --git a/sys_hw/Crc.h b/sys_hw/Crc.h
new file mode 100644
index 0000000..d385121
--- /dev/null
+++ b/sys_hw/Crc.h
@@ -0,0 +1,8 @@
+#ifndef __crc_h__
+#define __crc_h__
+
+#include "stm32f10x.h"
+
+extern u16 calcCRC( u8 *pBuffer, u16 BufferLength);
+
+#endif /* __crc_h__ */
diff --git a/sys_hw/Prj_FlashCfg.H b/sys_hw/Prj_FlashCfg.H
new file mode 100644
index 0000000..7c9beee
--- /dev/null
+++ b/sys_hw/Prj_FlashCfg.H
@@ -0,0 +1,1036 @@
+/*
+**************************************************************************************************************
+* FLASH Åä Öà ÎÄ ¼þ ¶¨ Òå
+*
+* Ãè Êö£ºFLASHÅäÖã»ÔÚʵ¼ÊÓ¦ÓÃÖУ¬×¢ÒâËùÑ¡ÐͺŵľßÌåÅäÖá£Èç¹û²»ÄÜÕý³£µÄÅäÖ㬲ο¼¾ßÌåµÄ²ÎÊýÏîÏÞÖÆ¡£
+*
+* Ãû ³Æ£ºPrj_FlashCfg.H
+*
+* °æ ±¾£ºV3.1
+*
+* ×÷ ÕߣºÕŽø
+*
+* ʱ ÆÚ£º2010/07/03
+*
+* Copyright (c) 2008-2009 Brand-NEW C.A.P Electronics Technology CO.,LTD
+**************************************************************************************************************
+*/
+
+#ifndef __Prj_FlashCfg_H__
+#define __Prj_FlashCfg_H__
+
+/*
+**************************************************************************************************************
+* Keil ²Ëµ¥ÅäÖÿªÊ¼
+**************************************************************************************************************
+*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+
+// <e>FLASHÅäÖÃ ©ï©ï©ï °æ±¾: V3.2 (2010/07/03) ©ï©ï©ï
+// =============================
+// <i> Enable or disable FLASHÅäÖÃ
+#define FLASH_CFG_ENABLE 1
+//
+//=============================================>> (1) <<======================================================
+// <e>1. FLASHÓ²¼þÅäÖÃ
+// <i> Enable or disable FLASHÓ²¼þÅäÖÃ
+#define FLASH_HW_CFG_ENABLE 1
+// ============================
+//
+// <s.15>FLASHÐͺÅ
+// <i> ¶¨ÒåËùʹÓõÄFLASHÐͺţ¬ÏÔʾÖÕ¶ËÐÅϢʱʹÓá£
+// <i> È磺AT45DB161D ÒªÇóСÓÚ15×Ö½Ú
+// <i> ĬÈÏ: "AT45DB161D"
+#define DEF_FLASH_NAME "W25X32"
+//
+// <o>FLASHÊÙÃü <5000=> 5000´Î <10000=> 1Íò´Î <20000=> 2Íò´Î
+// <30000=> 3Íò´Î <40000=> 4Íò´Î <50000=> 5Íò´Î
+// <60000=> 6Íò´Î <70000=> 7Íò´Î <80000=> 8Íò´Î
+// <90000=> 9Íò´Î <100000=> 10Íò´Î<10=> 10´Î
+// <i> ¶¨ÒåFLASHµÄÓÐЧÊÙÃü£¬Ó¦ÓÃÖÐÒÔ´ËÀ´½øÐÐÊÙÃü¼ÆËã
+// <i> ĬÈÏ: 50000
+#define DEF_FLASH_LimTimes 80000
+//
+// <o>FLASH×ÜÒ³Êý(Ò³) <1024-8192:1><#/1>
+// <i> ¶¨ÒåFLASHоƬµÄ×ÜÒ³Êý
+// <i> ĬÈÏ: 4096
+#define DEF_FLASH_Pages 1024
+//
+// <o>FLASHÒ³´óС(×Ö½Ú) <256-4096:1><#/1>
+// <i> ¶¨ÒåFLASHÒ»Ò³µÄ×Ö½ÚÊý
+// <i> ĬÈÏ: 528
+#define DEF_FLASH_PageSize 4096
+// </e>
+
+//=============================================>> (2) <<======================================================
+// <e>2. ºº×Ö¿âÅäÖÃ
+#define FLASH_GB1624_ENABLE 1
+
+//=============>> ºº×Ö¿âÇøÓò
+//=================>> 16*16×Ö¿â
+// <e>01. 16*16ºº×Ö¿â
+#define DEF_FLASH_GB1616_ENABLE 1
+
+#define DEF_FLASH_GB1616PageSize ( 67 ) //ÕâÀï¹Ì¶¨Öµ ×Ö¿â
+#define DEF_FLASH_GB1616StartAdd ( 0x00000000ul )
+//×ֿ⿪ʼµØÖ·
+#define DEF_FLASH_GB1616EndAdd ( DEF_FLASH_GB1616StartAdd + ( DEF_FLASH_GB1616PageSize * DEF_FLASH_PageSize * DEF_FLASH_GB1616_ENABLE ) )
+//×Ö¿â½áÊøµØÖ· ²»°üÀ¨´ËµØÖ·
+//=============>> ͼÐÎͼ±ê×Ö¿âÇøÓò
+#define DEF_FLASH_PhotoLibPageSize ( 5 ) //ÕâÀï¹Ì¶¨Öµ ͼÐÎͼ±ê
+#define DEF_FLASH_PhotoLibStartAdd ( DEF_FLASH_GB1616EndAdd )
+//ͼÐÎͼ±ê¿â¿ªÊ¼µØÖ·
+#define DEF_FLASH_PhotoLibEndAdd ( DEF_FLASH_PhotoLibStartAdd + ( DEF_FLASH_PhotoLibPageSize * DEF_FLASH_PageSize * DEF_FLASH_GB1616_ENABLE ) )
+//ͼÐÎͼ±ê¿â½áÊøµØÖ·
+// </e>
+
+//=================>> 24*24×Ö¿â
+// <e>02. 24*24ºº×Ö¿â
+#define DEF_FLASH_GB2424_ENABLE 1
+
+#define DEF_FLASH_GB2424PageSize ( 75 ) //24*24×Ö¿â
+
+#define DEF_FLASH_GB2424StartAdd ( DEF_FLASH_PhotoLibEndAdd )
+//×ֿ⿪ʼµØÖ·
+#define DEF_FLASH_GB2424EndAdd ( DEF_FLASH_GB2424StartAdd + ( DEF_FLASH_GB2424PageSize * DEF_FLASH_PageSize * DEF_FLASH_GB2424_ENABLE ) )
+// </e>
+
+
+// </e>
+
+//=============================================>> (3) <<======================================================
+// <e>3. IAPÉý¼¶¿Õ¼äÅäÖÃ
+#define FLASH_IAP_AppCode_ENABLE 1
+#define DEF_FLASH_IAP_AppCodeStartAdd ( DEF_FLASH_GB2424EndAdd )
+//Ó¦ÓôúÂë´æ´¢¿ªÊ¼µØÖ·
+//=====================
+//
+// <o>Éý¼¶´æ´¢Ó¦ÓôúÂë¿Õ¼ä´óС(Ò³) <3-1000:1><#/1>
+// <i>ĬÈÏ£º504
+#define DEF_FLASH_IAP_AppCodePageSize 128
+
+
+#define DEF_FLASH_IAP_AppCodeEndAdd ( DEF_FLASH_IAP_AppCodeStartAdd + \
+ ( DEF_FLASH_IAP_AppCodePageSize * \
+ DEF_FLASH_PageSize )*FLASH_IAP_AppCode_ENABLE )
+//Ó¦ÓôúÂë´æ´¢½áÊøµØÖ·
+// </e>
+
+//=============================================>> (4) <<======================================================
+// <e>4. FLASHÓû§ÎļþÅäÖÃ
+// <i> Enable or disable FLASH½»Ò׼ǼÅäÖÃ
+#define FLASH_UseFile_CFG_ENABLE 1
+
+#define DefCfg_UseFileStaAdd ( DEF_FLASH_IAP_AppCodeEndAdd )
+//FLASH½»Ò׼Ǽ´æ´¢µÄ¿ªÊ¼µØÖ·
+// ============================
+// <e>01. FLASHÓû§Îļþ01Çø
+#define DefCfg_UseFileBlock01_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile01_DirPageSize 4
+// ============================
+#define DefCfg_UseFile01_StaAdd ( DefCfg_UseFileStaAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile01_EndAdd ( DefCfg_UseFile01_StaAdd + \
+ ( DefCfg_UseFile01_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock01_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>02. FLASHÓû§Îļþ02Çø
+#define DefCfg_UseFileBlock02_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile02_DirPageSize 4
+// ============================
+#define DefCfg_UseFile02_StaAdd ( DefCfg_UseFile01_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile02_EndAdd ( DefCfg_UseFile02_StaAdd + \
+ ( DefCfg_UseFile02_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock02_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>03. FLASHÓû§Îļþ03Çø
+#define DefCfg_UseFileBlock03_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile03_DirPageSize 4
+// ============================
+#define DefCfg_UseFile03_StaAdd ( DefCfg_UseFile02_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile03_EndAdd ( DefCfg_UseFile03_StaAdd + \
+ ( DefCfg_UseFile03_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock03_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>04. FLASHÓû§Îļþ04Çø
+#define DefCfg_UseFileBlock04_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile04_DirPageSize 4
+// ============================
+#define DefCfg_UseFile04_StaAdd ( DefCfg_UseFile03_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile04_EndAdd ( DefCfg_UseFile04_StaAdd + \
+ ( DefCfg_UseFile04_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock04_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>05. FLASHÓû§Îļþ05Çø
+#define DefCfg_UseFileBlock05_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile05_DirPageSize 4
+// ============================
+#define DefCfg_UseFile05_StaAdd ( DefCfg_UseFile04_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile05_EndAdd ( DefCfg_UseFile05_StaAdd + \
+ ( DefCfg_UseFile05_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock05_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>06. FLASHÓû§Îļþ06Çø
+#define DefCfg_UseFileBlock06_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile06_DirPageSize 2
+// ============================
+#define DefCfg_UseFile06_StaAdd ( DefCfg_UseFile05_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile06_EndAdd ( DefCfg_UseFile06_StaAdd + \
+ ( DefCfg_UseFile06_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock06_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>07. FLASHÓû§Îļþ07Çø
+#define DefCfg_UseFileBlock07_Sta 1
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile07_DirPageSize 2
+// ============================
+#define DefCfg_UseFile07_StaAdd ( DefCfg_UseFile06_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile07_EndAdd ( DefCfg_UseFile07_StaAdd + \
+ ( DefCfg_UseFile07_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock07_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>08. FLASHÓû§Îļþ08Çø
+#define DefCfg_UseFileBlock08_Sta 0
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile08_DirPageSize 1
+// ============================
+#define DefCfg_UseFile08_StaAdd ( DefCfg_UseFile07_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile08_EndAdd ( DefCfg_UseFile08_StaAdd + \
+ ( DefCfg_UseFile08_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock08_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>09. FLASHÓû§Îļþ09Çø
+#define DefCfg_UseFileBlock09_Sta 0
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile09_DirPageSize 1
+// ============================
+#define DefCfg_UseFile09_StaAdd ( DefCfg_UseFile08_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile09_EndAdd ( DefCfg_UseFile09_StaAdd + \
+ ( DefCfg_UseFile09_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock09_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+// ============================
+// <e>10. FLASHÓû§Îļþ10Çø
+#define DefCfg_UseFileBlock10_Sta 0
+// ============================
+// <o>Óû§ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_UseFile10_DirPageSize 1
+// ============================
+#define DefCfg_UseFile10_StaAdd ( DefCfg_UseFile09_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_UseFile10_EndAdd ( DefCfg_UseFile10_StaAdd + \
+ ( DefCfg_UseFile10_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_UseFileBlock10_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// </e>
+
+
+#define DefCfg_UseFileEndAdd ( DefCfg_UseFile10_EndAdd )
+//FLASH½»Ò׼Ǽ´æ´¢µÄ½áÊøµØÖ·
+// </e>
+
+//=============================================>> (5) <<======================================================
+// <e>5. FLASH½»Ò׼ǼÅäÖÃ
+// <i> Enable or disable FLASH½»Ò׼ǼÅäÖÃ
+#define FLASH_Log_CFG_ENABLE 1
+
+#define DefCfg_LogFileStaAdd ( DefCfg_UseFileEndAdd )
+//FLASH½»Ò׼Ǽ´æ´¢µÄ¿ªÊ¼µØÖ·
+// ============================
+// <e>01. FLASH½»Ò׼Ǽ01Çø
+#define DefCfg_LogBlock01_Sta 1
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile01_DirPageSize 36
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile01_PageSize 400
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile01_PageRVS 2
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile01_RecLength 91
+// ============================
+#define DefCfg_LogDirFile01_StaAdd ( DefCfg_LogFileStaAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile01_EndAdd ( DefCfg_LogDirFile01_StaAdd + \
+ ( DefCfg_LogFile01_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock01_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile01_StaAdd ( DefCfg_LogDirFile01_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile01_EndAdd ( DefCfg_LogFile01_StaAdd + \
+ ( DefCfg_LogFile01_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock01_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock01_Sta )
+#if( DefCfg_LogFile01_PageSize <= DefCfg_LogFile01_PageRVS )
+#error "1:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>02. FLASH½»Ò׼Ǽ02Çø
+#define DefCfg_LogBlock02_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile02_DirPageSize 256
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile02_PageSize 1200
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile02_PageRVS 10
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile02_RecLength 70
+// ============================
+#define DefCfg_LogDirFile02_StaAdd ( DefCfg_LogFile01_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile02_EndAdd ( DefCfg_LogDirFile02_StaAdd + \
+ ( DefCfg_LogFile02_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock02_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile02_StaAdd ( DefCfg_LogDirFile02_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile02_EndAdd ( DefCfg_LogFile02_StaAdd + \
+ ( DefCfg_LogFile02_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock02_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock02_Sta )
+#if( DefCfg_LogFile02_PageSize <= DefCfg_LogFile02_PageRVS )
+#error "2:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>03. FLASH½»Ò׼Ǽ03Çø
+#define DefCfg_LogBlock03_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile03_DirPageSize 10
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile03_PageSize 20
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile03_PageRVS 3
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile03_RecLength 70
+// ============================
+#define DefCfg_LogDirFile03_StaAdd ( DefCfg_LogFile02_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile03_EndAdd ( DefCfg_LogDirFile03_StaAdd + \
+ ( DefCfg_LogFile03_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock03_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile03_StaAdd ( DefCfg_LogDirFile03_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile03_EndAdd ( DefCfg_LogFile03_StaAdd + \
+ ( DefCfg_LogFile03_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock03_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock03_Sta )
+#if( DefCfg_LogFile03_PageSize <= DefCfg_LogFile03_PageRVS )
+#error "3:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>04. FLASH½»Ò׼Ǽ04Çø
+#define DefCfg_LogBlock04_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile04_DirPageSize 10
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile04_PageSize 20
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile04_PageRVS 3
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile04_RecLength 70
+// ============================
+#define DefCfg_LogDirFile04_StaAdd ( DefCfg_LogFile03_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile04_EndAdd ( DefCfg_LogDirFile04_StaAdd + \
+ ( DefCfg_LogFile04_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock04_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile04_StaAdd ( DefCfg_LogDirFile04_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile04_EndAdd ( DefCfg_LogFile04_StaAdd + \
+ ( DefCfg_LogFile04_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock04_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock04_Sta )
+#if( DefCfg_LogFile04_PageSize <= DefCfg_LogFile04_PageRVS )
+#error "4:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>05. FLASH½»Ò׼Ǽ05Çø
+#define DefCfg_LogBlock05_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile05_DirPageSize 10
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile05_PageSize 20
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile05_PageRVS 3
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile05_RecLength 70
+// ============================
+#define DefCfg_LogDirFile05_StaAdd ( DefCfg_LogFile04_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile05_EndAdd ( DefCfg_LogDirFile05_StaAdd + \
+ ( DefCfg_LogFile05_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock05_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile05_StaAdd ( DefCfg_LogDirFile05_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile05_EndAdd ( DefCfg_LogFile05_StaAdd + \
+ ( DefCfg_LogFile05_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock05_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock05_Sta )
+#if( DefCfg_LogFile05_PageSize <= DefCfg_LogFile05_PageRVS )
+#error "5:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>06. FLASH½»Ò׼Ǽ06Çø
+#define DefCfg_LogBlock06_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile06_DirPageSize 6
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile06_PageSize 5
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile06_PageRVS 3
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile06_RecLength 130
+// ============================
+#define DefCfg_LogDirFile06_StaAdd ( DefCfg_LogFile05_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile06_EndAdd ( DefCfg_LogDirFile06_StaAdd + \
+ ( DefCfg_LogFile06_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock06_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile06_StaAdd ( DefCfg_LogDirFile06_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile06_EndAdd ( DefCfg_LogFile06_StaAdd + \
+ ( DefCfg_LogFile06_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock06_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock06_Sta )
+#if( DefCfg_LogFile06_PageSize <= DefCfg_LogFile06_PageRVS )
+#error "6:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>07. FLASH½»Ò׼Ǽ07Çø
+#define DefCfg_LogBlock07_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile07_DirPageSize 5
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile07_PageSize 6
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile07_PageRVS 3
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile07_RecLength 140
+// ============================
+#define DefCfg_LogDirFile07_StaAdd ( DefCfg_LogFile06_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile07_EndAdd ( DefCfg_LogDirFile07_StaAdd + \
+ ( DefCfg_LogFile07_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock07_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile07_StaAdd ( DefCfg_LogDirFile07_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile07_EndAdd ( DefCfg_LogFile07_StaAdd + \
+ ( DefCfg_LogFile07_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock07_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock07_Sta )
+#if( DefCfg_LogFile07_PageSize <= DefCfg_LogFile07_PageRVS )
+#error "7:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>08. FLASH½»Ò׼Ǽ08Çø
+#define DefCfg_LogBlock08_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile08_DirPageSize 5
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile08_PageSize 10
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile08_PageRVS 4
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile08_RecLength 250
+// ============================
+#define DefCfg_LogDirFile08_StaAdd ( DefCfg_LogFile07_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile08_EndAdd ( DefCfg_LogDirFile08_StaAdd + \
+ ( DefCfg_LogFile08_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock08_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile08_StaAdd ( DefCfg_LogDirFile08_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile08_EndAdd ( DefCfg_LogFile08_StaAdd + \
+ ( DefCfg_LogFile08_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock08_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock08_Sta )
+#if( DefCfg_LogFile08_PageSize <= DefCfg_LogFile08_PageRVS )
+#error "8:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>09. FLASH½»Ò׼Ǽ09Çø
+#define DefCfg_LogBlock09_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile09_DirPageSize 3
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile09_PageSize 10
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile09_PageRVS 4
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile09_RecLength 280
+// ============================
+#define DefCfg_LogDirFile09_StaAdd ( DefCfg_LogFile08_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile09_EndAdd ( DefCfg_LogDirFile09_StaAdd + \
+ ( DefCfg_LogFile09_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock09_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile09_StaAdd ( DefCfg_LogDirFile09_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile09_EndAdd ( DefCfg_LogFile09_StaAdd + \
+ ( DefCfg_LogFile09_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock09_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock09_Sta )
+#if( DefCfg_LogFile09_PageSize <= DefCfg_LogFile09_PageRVS )
+#error "9:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+
+// <e>10. FLASH½»Ò׼Ǽ10Çø
+#define DefCfg_LogBlock10_Sta 0
+// ============================
+// <o>¼Ç¼Ŀ¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile10_DirPageSize 3
+// <o>¼Ç¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_LogFile10_PageSize 10
+// <o>¼Ç¼ÎļþÔ¤Áô´óС(Ò³) <1-10:1><#/1>
+#define DefCfg_LogFile10_PageRVS 3
+// <o>ÿһÌõ¼Ç¼³¤¶È,°üÀ¨CRC(×Ö½Ú) <3-300:1><#/1>
+#define DefCfg_LogFile10_RecLength 300
+// ============================
+#define DefCfg_LogDirFile10_StaAdd ( DefCfg_LogFile09_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogDirFile10_EndAdd ( DefCfg_LogDirFile10_StaAdd + \
+ ( DefCfg_LogFile10_DirPageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock10_Sta ) ) //¼Ç¼½áÊøµØÖ·
+// ============================
+#define DefCfg_LogFile10_StaAdd ( DefCfg_LogDirFile10_EndAdd ) //¼Ç¼¿ªÊ¼µØÖ·
+#define DefCfg_LogFile10_EndAdd ( DefCfg_LogFile10_StaAdd + \
+ ( DefCfg_LogFile10_PageSize * \
+ DEF_FLASH_PageSize * \
+ DefCfg_LogBlock10_Sta ) ) //¼Ç¼½áÊøµØÖ·
+#if( DefCfg_LogBlock10_Sta )
+#if( DefCfg_LogFile10_PageSize <= DefCfg_LogFile10_PageRVS )
+#error "10:·ÖÅäµÄ¼Ç¼×Ü´óС±ØÐë´óÓÚÔ¤Áô¼Ç¼´óС"
+#endif
+#endif
+// </e>
+#define DefCfg_LogFileEndAdd ( DefCfg_LogFile10_EndAdd )
+//FLASH½»Ò׼Ǽ´æ´¢µÄ½áÊøµØÖ·
+// </e>
+
+//=============================================>> (6) <<======================================================
+// <e>6. FLASHºÚÃûµ¥ÇøÅäÖÃ
+// <i> Enable or disable ºÚÃûµ¥ÇøÅäÖÃ
+#define BLACKLIST_CFG_ENABLE 1
+
+#define BLACKLIST_START_ADDRESS ( DefCfg_LogFileEndAdd )
+//ºÚÃûµ¥´æ´¢¿ªÊ¼µØÖ·
+#define FLASH_PAGE_SIZE ( DEF_FLASH_PageSize )
+
+//<e>1. µÚÒ»ºÚÃûµ¥ÇøÅäÖÃ
+// <i> Enable or disable ºÚÃûµ¥Çø¿éÅäÖã¨Ã¿¿éºÚÃûµ¥Çø°üº¬ÓжàÉÙ¿éFLASH¿é£©
+#define BLACKLIST1_CFG_ENABLE 1
+
+
+// <o>ºÚÃûµ¥Ä¿Â¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_BlkFile01_DirPageSize 20
+
+#define DefCfg_BlackFile01_StaAdd ( BLACKLIST_START_ADDRESS ) //ºÚÃû1µ¥¿ªÊ¼µØÖ·
+#define DefCfg_BlackFile01_EndAdd DefCfg_BlackFile01_StaAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST1_CFG_ENABLE * \
+ DefCfg_BlkFile01_DirPageSize )
+//ºÚÃû1µ¥½áÊøµØÖ·
+#define BLACKLIST1_START_ADDRESS DefCfg_BlackFile01_EndAdd
+
+//
+// <o>ÿ¸öºÚÃûµ¥¿é°üº¬Flash¿éÒ³Êý <1=> 1Ò³ <2=> 2Ò³ <3=> 3Ò³ <4=> 4Ò³
+// <5=> 5ҳ <6=> 6ҳ <7=> 7ҳ
+// <i> ¶¨ÒåFLASHµÄÓÐЧÊÙÃü£¬Ó¦ÓÃÖÐÒÔ´ËÀ´½øÐÐÊÙÃü¼ÆËã
+// <i> ĬÈÏ: 10
+#define BLACKLIST1_PAGE_SIZE 1
+
+// <o>ºÚÃûµ¥ÇøËù·ÖÅäµÄºÚÃûµ¥¿éÊý <6-1000:2><#/1>
+// <i>ºÚÃûµ¥ÇøËù·ÖÅäµÄ´óС
+// <i>ĬÈÏ£º800
+#define BLACKLIST1_SECTION_SIZE 210
+
+// <o>ÿ¸öºÚÃûµ¥µÄ³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST1_LENGTH 4
+
+// <o>ºÚÃûµ¥±È½Ï³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST1_COMPARE_LENGTH 4
+
+// <o>ºÚÃûµ¥¶ÔÆë·½·¨ <0=> ×ó¶ÔÆë <1=> ÓÒ¶ÔÆë
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º1
+#define BLACKLIST1_FLUSH_METHOD 1
+
+// </e>
+
+
+//<e>2. µÚ¶þºÚÃûµ¥ÇøÅäÖÃ
+// <i> Enable or disable ºÚÃûµ¥Çø¿éÅäÖã¨Ã¿¿éºÚÃûµ¥Çø°üº¬ÓжàÉÙ¿éFLASH¿é£©
+#define BLACKLIST2_CFG_ENABLE 1
+
+
+//
+// <o>ºÚÃûµ¥Ä¿Â¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_BlkFile02_DirPageSize 6
+
+#define DefCfg_BlackFile02_StaAdd DefCfg_BlackFile01_EndAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST1_CFG_ENABLE * \
+ BLACKLIST1_PAGE_SIZE * \
+ BLACKLIST1_SECTION_SIZE )
+//ºÚÃû1µ¥¿ªÊ¼µØÖ·
+#define DefCfg_BlackFile02_EndAdd DefCfg_BlackFile02_StaAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST2_CFG_ENABLE * \
+ DefCfg_BlkFile02_DirPageSize )
+//ºÚÃû1µ¥½áÊøµØÖ·
+#define BLACKLIST2_START_ADDRESS DefCfg_BlackFile02_EndAdd
+
+
+
+// <o>ÿ¸öºÚÃûµ¥¿é°üº¬Flash¿éÊýÁ¿ <1=> 1Ò³ <2=> 2Ò³ <3=> 3Ò³ <4=> 4Ò³
+// <5=> 5ҳ <6=> 6ҳ <7=> 7ҳ
+// <i> ¶¨ÒåFLASHµÄÓÐЧÊÙÃü£¬Ó¦ÓÃÖÐÒÔ´ËÀ´½øÐÐÊÙÃü¼ÆËã
+// <i> ĬÈÏ: 10
+#define BLACKLIST2_PAGE_SIZE 1
+
+// <o>ºÚÃûµ¥ÇøËù·ÖÅäµÄºÚÃûµ¥¿éÊý <6-1000:2><#/1>
+// <i>ºÚÃûµ¥ÇøËù·ÖÅäµÄ´óС
+// <i>ĬÈÏ£º6
+#define BLACKLIST2_SECTION_SIZE 10
+
+// <o>ÿ¸öºÚÃûµ¥µÄ³¤¶È <2=> 2×Ö½Ú <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST2_LENGTH 2
+
+// <o>ºÚÃûµ¥±È½Ï³¤¶È <2=> 2×Ö½Ú <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST2_COMPARE_LENGTH 2
+
+// <o>ºÚÃûµ¥¶ÔÆë·½·¨ <0=> ×ó¶ÔÆë <1=> ÓÒ¶ÔÆë
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º1
+#define BLACKLIST2_FLUSH_METHOD 1
+
+// </e>
+
+//<e>3. µÚÈýºÚÃûµ¥ÇøÅäÖÃ
+// <i> Enable or disable ºÚÃûµ¥Çø¿éÅäÖã¨Ã¿¿éºÚÃûµ¥Çø°üº¬ÓжàÉÙ¿éFLASH¿é£©
+#define BLACKLIST3_CFG_ENABLE 0
+
+//
+// <o>ºÚÃûµ¥Ä¿Â¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_BlkFile03_DirPageSize 3
+
+#define DefCfg_BlackFile03_StaAdd DefCfg_BlackFile02_EndAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST2_CFG_ENABLE * \
+ BLACKLIST2_PAGE_SIZE * \
+ BLACKLIST2_SECTION_SIZE )
+//ºÚÃû1µ¥¿ªÊ¼µØÖ·
+#define DefCfg_BlackFile03_EndAdd DefCfg_BlackFile03_StaAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST3_CFG_ENABLE * \
+ DefCfg_BlkFile03_DirPageSize )
+//ºÚÃû1µ¥½áÊøµØÖ·
+#define BLACKLIST3_START_ADDRESS DefCfg_BlackFile03_EndAdd
+
+// <o>ÿ¸öºÚÃûµ¥¿é°üº¬Flash¿éÊýÁ¿ <4=> 4¿é <5=> 5¿é <6=> 6¿é <7=> 7¿é
+// <8=> 8¿é <9=> 9¿é <10=> 10¿é
+// <i> ¶¨ÒåFLASHµÄÓÐЧÊÙÃü£¬Ó¦ÓÃÖÐÒÔ´ËÀ´½øÐÐÊÙÃü¼ÆËã
+// <i> ĬÈÏ: 10
+#define BLACKLIST3_PAGE_SIZE 10
+
+// <o>ºÚÃûµ¥ÇøËù·ÖÅäµÄºÚÃûµ¥¿é´óС <6-1000:2><#/1>
+// <i>ºÚÃûµ¥ÇøËù·ÖÅäµÄ´óС
+// <i>ĬÈÏ£º6
+#define BLACKLIST3_SECTION_SIZE 8
+
+// <o>ÿ¸öºÚÃûµ¥µÄ³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST3_LENGTH 4
+
+// <o>ºÚÃûµ¥±È½Ï³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST3_COMPARE_LENGTH 4
+
+// <o>ºÚÃûµ¥¶ÔÆë·½·¨ <0=> ×ó¶ÔÆë <1=> ÓÒ¶ÔÆë
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º1
+#define BLACKLIST3_FLUSH_METHOD 1
+
+// </e>
+
+//<e>4. µÚËĺÚÃûµ¥ÇøÅäÖÃ
+// <i> Enable or disable ºÚÃûµ¥Çø¿éÅäÖã¨Ã¿¿éºÚÃûµ¥Çø°üº¬ÓжàÉÙ¿éFLASH¿é£©
+#define BLACKLIST4_CFG_ENABLE 0
+
+//
+// <o>ºÚÃûµ¥Ä¿Â¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_BlkFile04_DirPageSize 3
+
+#define DefCfg_BlackFile04_StaAdd DefCfg_BlackFile03_EndAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST3_CFG_ENABLE * \
+ BLACKLIST3_PAGE_SIZE * \
+ BLACKLIST3_SECTION_SIZE )
+//ºÚÃû1µ¥¿ªÊ¼µØÖ·
+#define DefCfg_BlackFile04_EndAdd DefCfg_BlackFile04_StaAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST4_CFG_ENABLE * \
+ DefCfg_BlkFile04_DirPageSize )
+//ºÚÃû1µ¥½áÊøµØÖ·
+#define BLACKLIST4_START_ADDRESS DefCfg_BlackFile04_EndAdd
+
+// <o>ÿ¸öºÚÃûµ¥¿é°üº¬Flash¿éÊýÁ¿ <4=> 4¿é <5=> 5¿é <6=> 6¿é <7=> 7¿é
+// <8=> 8¿é <9=> 9¿é <10=> 10¿é
+// <i> ¶¨ÒåFLASHµÄÓÐЧÊÙÃü£¬Ó¦ÓÃÖÐÒÔ´ËÀ´½øÐÐÊÙÃü¼ÆËã
+// <i> ĬÈÏ: 10
+#define BLACKLIST4_PAGE_SIZE 10
+
+// <o>ºÚÃûµ¥ÇøËù·ÖÅäµÄºÚÃûµ¥¿é´óС <6-1000:2><#/1>
+// <i>ºÚÃûµ¥ÇøËù·ÖÅäµÄ´óС
+// <i>ĬÈÏ£º6
+#define BLACKLIST4_SECTION_SIZE 8
+
+// <o>ÿ¸öºÚÃûµ¥µÄ³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST4_LENGTH 4
+
+// <o>ºÚÃûµ¥±È½Ï³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST4_COMPARE_LENGTH 4
+
+// <o>ºÚÃûµ¥¶ÔÆë·½·¨ <0=> ×ó¶ÔÆë <1=> ÓÒ¶ÔÆë
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º1
+#define BLACKLIST4_FLUSH_METHOD 1
+
+// </e>
+
+//<e>5. µÚÎåºÚÃûµ¥ÇøÅäÖÃ
+// <i> Enable or disable ºÚÃûµ¥Çø¿éÅäÖã¨Ã¿¿éºÚÃûµ¥Çø°üº¬ÓжàÉÙ¿éFLASH¿é£©
+#define BLACKLIST5_CFG_ENABLE 0
+
+//
+// <o>ºÚÃûµ¥Ä¿Â¼ÎļþËù·ÖÅäµÄ×Ü´óС(Ò³) <1-8196:1><#/1>
+#define DefCfg_BlkFile05_DirPageSize 3
+
+#define DefCfg_BlackFile05_StaAdd DefCfg_BlackFile04_EndAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST4_CFG_ENABLE * \
+ BLACKLIST4_PAGE_SIZE * \
+ BLACKLIST4_SECTION_SIZE )
+//ºÚÃû1µ¥¿ªÊ¼µØÖ·
+#define DefCfg_BlackFile05_EndAdd DefCfg_BlackFile05_StaAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST5_CFG_ENABLE * \
+ DefCfg_BlkFile05_DirPageSize )
+//ºÚÃû1µ¥½áÊøµØÖ·
+#define BLACKLIST5_START_ADDRESS DefCfg_BlackFile05_EndAdd
+
+// <o>ÿ¸öºÚÃûµ¥¿é°üº¬Flash¿éÊýÁ¿ <2=> 2¿é <4=> 4¿é <6=> 6¿é
+// <8=> 8¿é <10=> 10¿é <12=> 12¿é
+// <14=> 14¿é <16=> 16¿é <18=> 18¿é
+// <20=> 20¿é
+// <4096=> 4096Bytes <65536=> 64KBytes
+// <i> ¶¨ÒåFLASHµÄÓÐЧÊÙÃü£¬Ó¦ÓÃÖÐÒÔ´ËÀ´½øÐÐÊÙÃü¼ÆËã
+// <i> ĬÈÏ: 10
+#define BLACKLIST5_PAGE_SIZE 10
+
+// <o>ºÚÃûµ¥ÇøËù·ÖÅäµÄºÚÃûµ¥¿é´óС <6-1000:2><#/1>
+// <i>ºÚÃûµ¥ÇøËù·ÖÅäµÄ´óС
+// <i>ĬÈÏ£º6
+#define BLACKLIST5_SECTION_SIZE 8
+
+// <o>ÿ¸öºÚÃûµ¥µÄ³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST5_LENGTH 4
+
+// <o>ºÚÃûµ¥±È½Ï³¤¶È <3=> 3×Ö½Ú <4=> 4×Ö½Ú <5=> 5×Ö½Ú
+// <6=> 6×Ö½Ú <7=> 7×Ö½Ú <8=> 8×Ö½Ú
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º6
+#define BLACKLIST5_COMPARE_LENGTH 4
+
+// <o>ºÚÃûµ¥¶ÔÆë·½·¨ <0=> ×ó¶ÔÆë <1=> ÓÒ¶ÔÆë
+// <i>ºÚÃûµ¥ÇøÊýÁ¿£¬À´Ó¦Óü¸¸öºÚÃûµ¥
+// <i>ĬÈÏ£º1
+#define BLACKLIST5_FLUSH_METHOD 1
+
+// </e>
+
+#define BLACKLIST_END_ADDRESS DefCfg_BlackFile05_EndAdd + ( FLASH_PAGE_SIZE * \
+ BLACKLIST5_CFG_ENABLE * \
+ BLACKLIST5_PAGE_SIZE * \
+ BLACKLIST5_SECTION_SIZE )
+
+//ºÚÃûµ¥´æ´¢½áÊøµØÖ·
+
+
+
+// </e>
+
+//=============================================>> (7) <<======================================================
+
+//=============================================>> (end) <<====================================================
+
+// </e>
+//------------- <<< end of configuration section >>> -----------------------
+
+/*
+**************************************************************************************************************
+* Keil ²Ëµ¥ÅäÖýáÊø
+**************************************************************************************************************
+*/
+
+/*
+**************************************************************************************************************
+* ¸¨ Öú Åä ÖÃ
+**************************************************************************************************************
+*/
+//========>>FLASH Ê£Óà
+#define DEF_FLASH_ResStartAdd ( BLACKLIST_END_ADDRESS )
+//Ê£ÓàFLASH¿Õ¼äµÄ¿ªÊ¼µØÖ·
+#define DEF_FLASH_ResEndAdd ( DEF_FLASH_Pages * DEF_FLASH_PageSize )
+//Ê£ÓàFLASH¿Õ¼äµÄ½áÊøµØÖ·
+#define DEF_FLASH_ResSize ( DEF_FLASH_ResEndAdd - DEF_FLASH_ResStartAdd )
+//Óû§¿ÉÒÔʹÓÃ×Ö½ÚÊý
+
+
+//========>>×î´ó¼Ç¼³¤¶È
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile01_RecLength * DefCfg_LogBlock01_Sta )
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile02_RecLength * DefCfg_LogBlock02_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile02_RecLength * DefCfg_LogBlock02_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile03_RecLength * DefCfg_LogBlock03_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile03_RecLength * DefCfg_LogBlock03_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile04_RecLength * DefCfg_LogBlock04_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile04_RecLength * DefCfg_LogBlock04_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile05_RecLength * DefCfg_LogBlock05_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile05_RecLength * DefCfg_LogBlock05_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile06_RecLength * DefCfg_LogBlock06_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile06_RecLength * DefCfg_LogBlock06_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile07_RecLength * DefCfg_LogBlock07_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile07_RecLength * DefCfg_LogBlock07_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile08_RecLength * DefCfg_LogBlock08_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile08_RecLength * DefCfg_LogBlock08_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile09_RecLength * DefCfg_LogBlock09_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile09_RecLength * DefCfg_LogBlock09_Sta )
+#endif
+
+#if( DEF_FLASH_MaxRecLength < ( DefCfg_LogFile10_RecLength * DefCfg_LogBlock10_Sta ) )
+#undef DEF_FLASH_MaxRecLength
+#define DEF_FLASH_MaxRecLength ( DefCfg_LogFile10_RecLength * DefCfg_LogBlock10_Sta )
+#endif
+
+//========>>×î´óºÚÃûµ¥»º³åÇø³¤¶È
+#define DEF_FLASH_MaxBlkBufSize ( BLACKLIST1_CFG_ENABLE * BLACKLIST1_PAGE_SIZE * DEF_FLASH_PageSize )
+
+#if( DEF_FLASH_MaxBlkBufSize < ( BLACKLIST2_CFG_ENABLE * BLACKLIST2_PAGE_SIZE * DEF_FLASH_PageSize ) )
+#undef DEF_FLASH_MaxBlkBufSize
+#define DEF_FLASH_MaxBlkBufSize ( BLACKLIST2_CFG_ENABLE * BLACKLIST2_PAGE_SIZE * DEF_FLASH_PageSize )
+#endif
+
+#if( DEF_FLASH_MaxBlkBufSize < ( BLACKLIST3_CFG_ENABLE * BLACKLIST3_PAGE_SIZE * DEF_FLASH_PageSize ) )
+#undef DEF_FLASH_MaxBlkBufSize
+#define DEF_FLASH_MaxBlkBufSize ( BLACKLIST3_CFG_ENABLE * BLACKLIST3_PAGE_SIZE * DEF_FLASH_PageSize )
+#endif
+
+#if( DEF_FLASH_MaxBlkBufSize < ( BLACKLIST4_CFG_ENABLE * BLACKLIST4_PAGE_SIZE * DEF_FLASH_PageSize ) )
+#undef DEF_FLASH_MaxBlkBufSize
+#define DEF_FLASH_MaxBlkBufSize ( BLACKLIST4_CFG_ENABLE * BLACKLIST4_PAGE_SIZE * DEF_FLASH_PageSize )
+#endif
+
+#if( DEF_FLASH_MaxBlkBufSize < ( BLACKLIST5_CFG_ENABLE * BLACKLIST5_PAGE_SIZE * DEF_FLASH_PageSize ) )
+#undef DEF_FLASH_MaxBlkBufSize
+#define DEF_FLASH_MaxBlkBufSize ( BLACKLIST5_CFG_ENABLE * BLACKLIST5_PAGE_SIZE * DEF_FLASH_PageSize )
+#endif
+
+//========>>ÿ¿é¼Ç¼Çø×î´æ´¢¼Ç¼ÊýÁ¿ ÀíÂÛÁ¿´óÖµ
+#define DEF_Rec01_MaxRecNum ( ( DefCfg_LogFile01_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile01_RecLength )
+#define DEF_Rec02_MaxRecNum ( ( DefCfg_LogFile02_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile02_RecLength )
+#define DEF_Rec03_MaxRecNum ( ( DefCfg_LogFile03_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile03_RecLength )
+#define DEF_Rec04_MaxRecNum ( ( DefCfg_LogFile04_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile04_RecLength )
+#define DEF_Rec05_MaxRecNum ( ( DefCfg_LogFile05_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile05_RecLength )
+#define DEF_Rec06_MaxRecNum ( ( DefCfg_LogFile06_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile06_RecLength )
+#define DEF_Rec07_MaxRecNum ( ( DefCfg_LogFile07_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile07_RecLength )
+#define DEF_Rec08_MaxRecNum ( ( DefCfg_LogFile08_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile08_RecLength )
+#define DEF_Rec09_MaxRecNum ( ( DefCfg_LogFile09_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile09_RecLength )
+#define DEF_Rec10_MaxRecNum ( ( DefCfg_LogFile10_PageSize * DEF_FLASH_PageSize )/DefCfg_LogFile10_RecLength )
+
+
+
+
+
+//=========>>¿Õ¼äÓÃÊÇʹÓÃÍê
+#if( DEF_FLASH_ResStartAdd > DEF_FLASH_Pages * DEF_FLASH_PageSize )
+#error "FLASH·ÖÅä¿Õ¼ä³¬ÏÞ"
+#endif
+
+
+/*
+**************************************************************************************************************
+* ¶Ô²¿·ÖÅäÖÃÐÅÏ¢½øÐмì²â
+*
+* ×¢ Ò⣺ ¶ÔÅäÖÃÐÅÏ¢½øÐмì²âÖ»ÊǼòµ¥µÄ¼ì²â£¬²»ÒªÍêÈ«ÒÀÀµ´Ë¼ì²â¡£ÓÐЩ´íÎóÊDz»Äܼì²âµ½µÄ£¬½øÐÐÅäÖÃʱӦÌرðÁôÒâ¡£
+*
+**************************************************************************************************************
+*/
+
+//======================================>> ºÚÃûµ¥ÅäÖüì²â
+#if( ( BLACKLIST1_SECTION_SIZE % 2 ) != 0 )
+#error "µÚÒ»ºÚÃûµ¥Çø¿éÊý²»ÊÇżÊý£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+#if( ( BLACKLIST2_SECTION_SIZE % 2 ) != 0 )
+#error "µÚ¶þºÚÃûµ¥Çø¿éÊý²»ÊÇżÊý£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+#if( ( BLACKLIST3_SECTION_SIZE % 2 ) != 0 )
+#error "µÚÈýºÚÃûµ¥Çø¿éÊý²»ÊÇżÊý£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+#if( ( BLACKLIST4_SECTION_SIZE % 2 ) != 0 )
+#error "µÚËĺÚÃûµ¥Çø¿éÊý²»ÊÇżÊý£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+#if( ( BLACKLIST5_SECTION_SIZE % 2 ) != 0 )
+#error "µÚÎåºÚÃûµ¥Çø¿éÊý²»ÊÇżÊý£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+
+#if( ( ( FLASH_PAGE_SIZE * BLACKLIST1_PAGE_SIZE ) % BLACKLIST1_LENGTH ) != 0 )
+#error "µÚÒ»ºÚÃûµ¥Çøÿ¿é²»ÄÜ´æÕûÊý¸öºÚÃûµ¥£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( ( ( FLASH_PAGE_SIZE * BLACKLIST2_PAGE_SIZE ) % BLACKLIST2_LENGTH ) != 0 )
+#error "µÚ¶þºÚÃûµ¥Çøÿ¿é²»ÄÜ´æÕûÊý¸öºÚÃûµ¥£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( ( ( FLASH_PAGE_SIZE * BLACKLIST3_PAGE_SIZE ) % BLACKLIST3_LENGTH ) != 0 )
+#error "µÚÈýºÚÃûµ¥Çøÿ¿é²»ÄÜ´æÕûÊý¸öºÚÃûµ¥£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( ( ( FLASH_PAGE_SIZE * BLACKLIST4_PAGE_SIZE ) % BLACKLIST5_LENGTH ) != 0 )
+#error "µÚËĺÚÃûµ¥Çøÿ¿é²»ÄÜ´æÕûÊý¸öºÚÃûµ¥£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( ( ( FLASH_PAGE_SIZE * BLACKLIST5_PAGE_SIZE ) % BLACKLIST5_LENGTH ) != 0 )
+#error "µÚÎåºÚÃûµ¥Çøÿ¿é²»ÄÜ´æÕûÊý¸öºÚÃûµ¥£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+
+
+#if( BLACKLIST1_COMPARE_LENGTH > BLACKLIST1_LENGTH )
+#error "µÚÒ»ºÚÃûµ¥ÇøºÚÃûµ¥±È½Ï³¤¶È±ÈºÚÃûµ¥³¤¶È´ó£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( BLACKLIST2_COMPARE_LENGTH > BLACKLIST2_LENGTH )
+#error "µÚ¶þºÚÃûµ¥ÇøºÚÃûµ¥±È½Ï³¤¶È±ÈºÚÃûµ¥³¤¶È´ó£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( BLACKLIST3_COMPARE_LENGTH > BLACKLIST3_LENGTH )
+#error "µÚÈýºÚÃûµ¥ÇøºÚÃûµ¥±È½Ï³¤¶È±ÈºÚÃûµ¥³¤¶È´ó£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( BLACKLIST4_COMPARE_LENGTH > BLACKLIST4_LENGTH )
+#error "µÚËĺÚÃûµ¥ÇøºÚÃûµ¥±È½Ï³¤¶È±ÈºÚÃûµ¥³¤¶È´ó£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+#if( BLACKLIST5_COMPARE_LENGTH > BLACKLIST5_LENGTH )
+#error "µÚÎåºÚÃûµ¥ÇøºÚÃûµ¥±È½Ï³¤¶È±ÈºÚÃûµ¥³¤¶È´ó£¡Çëµ÷ÕûºÚÃûµ¥ÅäÖÃ"
+#endif
+
+
+
+
+#endif
+
diff --git a/sys_hw/data_tools.c b/sys_hw/data_tools.c
new file mode 100644
index 0000000..6ca8143
--- /dev/null
+++ b/sys_hw/data_tools.c
@@ -0,0 +1,247 @@
+#include "data_tools.h"
+
+u8 int2array(u32 val, void* dest, u8 len)
+{
+ u8 index = 0;
+
+ if(len>4) return 1;
+
+ for(index=0;index<len;index++)
+ *((u8 *)dest+index) = (u32)val>>((len-1-index)<<3);
+
+ return 0;
+}
+
+u8 array2int(void* src, void* pval, u8 len)
+{
+ u8 index = 0;
+
+ if(len>4) return 1;
+
+ for(index=0;index<len;index++)
+ {
+ *((u8*)pval+len-1-index) = *((u8 *)src+index);
+ }
+ return 0;
+}
+
+u8 mem_test(void* src, u8 val, int count)
+{
+ if(!count) return 0;
+
+ while(count--){
+ if(*(char *)src != val) return 1;
+ src = (char *)src +1;
+ }
+ return 0;
+}
+
+u8 mem_reverse(void* src, int count)
+{
+ u8 temp;
+ int i;
+ u8* pbuff = (u8 *)src;
+
+ if(!count) return 0;
+
+ for(i=0;i<count/2;i++)
+ {
+ temp = *(pbuff + i);
+ *(pbuff + i) = *(pbuff + count - 1 -i);
+ *(pbuff + count - 1 -i) = temp;
+ }
+ return 0;
+}
+
+/**********************************************
+bcdÊý¾Ýת»»ÎªhexÊý¾Ý
+***********************************************/
+void bcd2hex(void* bcd, u32 len)
+{
+ u32 i;
+ u8* pbuff = (u8 *)bcd;
+
+ for(i=0;i<len;i++)
+ {
+ *pbuff=((*pbuff)/16)*10+(*pbuff)%16;
+ pbuff++;
+ }
+}
+
+/*********************************************
+hexÊý¾Ýת»»Îªbcd
+**********************************************/
+void hex2bcd(void* hex, u32 len)
+{
+ u32 i;
+ u8* pbuff = (u8 *)hex;
+
+ for(i=0;i<len;i++)
+ {
+ *pbuff =(*pbuff/10)*16+(*pbuff)%10 ;
+ pbuff++ ;
+ }
+}
+
+static int char2bin(u8 c, u8* bin)
+{
+ if((c>='0') && (c<='9'))
+ {
+ *bin = c - '0';
+ }
+ else if((c>='a') && (c<='f'))
+ {
+ *bin = c - 'a' + 0x0A;
+ }
+ else if((c>='A') && (c<='F'))
+ {
+ *bin = c - 'A' + 0x0A;
+ }
+ else
+ {
+ return 1;
+ }
+ return 0;
+}
+
+int hex2bin(u8* in_buff, u8* out_buf, u32 len)
+{
+ u32 i;
+ u8 temp[2];
+
+ if(len&0x01) return 1;
+ for(i=0;i<len;)
+ {
+ char2bin(*(in_buff + i), &temp[0]);
+ char2bin(*(in_buff + i + 1), &temp[1]);
+ *(out_buf+(i>>1)) = (temp[0]<<4) + temp[1];
+ i += 2;
+ }
+ return 0;
+}
+
+int get_repetition_count(unsigned char* src, unsigned int src_left)
+{
+ unsigned int count = 0;
+ unsigned int i = 0;
+
+ while(i < src_left)
+ {
+ if(*src == *(src+i))
+ {
+ if(count<127)
+ {
+ count++;
+ }
+
+ }
+ else
+ {
+ break;
+ }
+ i ++;
+ }
+ return count;
+}
+
+int get_non_repetition_count(unsigned char* src, unsigned int src_left)
+{
+ unsigned int count = 0;
+
+ while(count < src_left)
+ {
+ if(get_repetition_count(src+count, src_left-count)<3)
+ {
+ if(count<127)
+ {
+ count++;
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+ return count;
+
+}
+
+/*
+ rle½âѹËõ
+*/
+int rle_decode(unsigned char *in_buf, int in_sz, unsigned char *out_buf, int out_buf_sz)
+{
+ unsigned char *src = in_buf;
+ int i;
+ int dec_sz = 0;
+
+ while(src < (in_buf + in_sz))
+ {
+ unsigned char sign = *src++;
+ int count = sign & 0x7F;
+ if((dec_sz + count) > out_buf_sz) /*Êä³ö»º³åÇø¿Õ¼ä²»¹»ÁË*/
+ {
+ return -1;
+ }
+ if((sign & 0x80) == 0x80) /*Á¬ÐøÖظ´Êý¾Ý±êÖ¾*/
+ {
+ for(i = 0; i < count; i++)
+ {
+ out_buf[dec_sz++] = *src;
+ }
+ src++;
+ }
+ else
+ {
+ for(i = 0; i < count; i++)
+ {
+ out_buf[dec_sz++] = *src++;
+ }
+ }
+ }
+
+ return dec_sz;
+}
+
+/*
+ rleѹËõ
+*/
+int rle_encode(unsigned char *in_buf, int in_sz, unsigned char *out_buf, int out_buf_sz)
+{
+ unsigned char *src = in_buf;
+ int i;
+ int enc_sz = 0;
+ int src_left = in_sz;
+
+ while(src_left > 0)
+ {
+ int count = get_repetition_count(src, src_left);
+
+ if(count>2) /*ÊÇ·ñÁ¬ÐøÈý¸ö×Ö½ÚÊý¾ÝÏàͬ£¿*/
+ {
+ if((enc_sz + 2) > out_buf_sz) /*Êä³ö»º³åÇø¿Õ¼ä²»¹»ÁË*/
+ {
+ return -1;
+ }
+ out_buf[enc_sz++] = count | 0x80;
+ out_buf[enc_sz++] = *src;
+ src += count;
+ src_left -= count;
+ }
+ else
+ {
+ count = get_non_repetition_count(src, src_left);
+ if((enc_sz + count + 1) > out_buf_sz) /*Êä³ö»º³åÇø¿Õ¼ä²»¹»ÁË*/
+ {
+ return -1;
+ }
+ out_buf[enc_sz++] = count;
+ for(i = 0; i < count; i++) /*Öð¸ö¸´ÖÆÕâЩÊý¾Ý*/
+ {
+ out_buf[enc_sz++] = *src++;;
+ }
+ src_left -= count;
+ }
+ }
+ return enc_sz;
+}
diff --git a/sys_hw/data_tools.h b/sys_hw/data_tools.h
new file mode 100644
index 0000000..018dc0d
--- /dev/null
+++ b/sys_hw/data_tools.h
@@ -0,0 +1,20 @@
+#ifndef __data_tools_h__
+#define __data_tools_h__
+
+#include "stm32f10x.h"
+
+extern u8 int2array(u32 val, void * dest, u8 len);
+extern u8 array2int(void * src, void* pval, u8 len);
+
+extern u8 mem_reverse(void * src, int count);
+extern u8 mem_test(void * src, u8 val, int count);
+
+extern void hex2bcd(void* hex, u32 len);
+extern void bcd2hex(void* bcd, u32 len);
+extern int hex2bin(u8* in_buff, u8* out_buf, u32 len);
+
+extern int rle_encode(unsigned char *in_buf, int in_sz, unsigned char *out_buf, int out_buf_sz);
+extern int rle_decode(unsigned char *in_buf, int in_sz, unsigned char *out_buf, int out_buf_sz);
+
+#endif /* __data_tools_h__ */
+
diff --git a/sys_hw/drv_adc.c b/sys_hw/drv_adc.c
new file mode 100644
index 0000000..ad54096
--- /dev/null
+++ b/sys_hw/drv_adc.c
@@ -0,0 +1,321 @@
+#include "drv_adc.h"
+#include "stm32f10x.h"
+#include "keypad.h"
+#include "string.h"
+#include "../supwisdom/sp_util.h"
+#include "../supwisdom/sp_flash.h"
+
+//#include "mifare_one_hw_lib.h"
+#include "timer.h"
+#include "data_tools.h"
+//#include "crc.h"
+//#include "dbg.h"
+
+#define PDDThreshod_Votage 80
+#define PDDThreshod_ADCVal (PDDThreshod_Votage*4095L/713L)
+
+#define Reset_Votage 74 //TPS54160Í£Ö¹¹¤×÷µçѹ7.1V
+#define Reset_ADCVal (Reset_Votage*4095L/713L)
+
+
+typedef void (*adc_timer_tick_t)(void);
+
+volatile uint8_t adc_timer;
+volatile uint8_t ch_idx;
+volatile uint16_t adc_val_vdd=4095;
+volatile uint16_t adc_val;
+dac_para_t dac_para = {890, 890, 890, 890, 890, 890, 890, 890, 890, 890, 890, 890, 0}; //dacÊä³öµçѹĬÈÏ3.3V
+adc_timer_tick_t p_adc_timer_tick = 0;
+volatile uint16_t adc_buff[ADC_MAX_CH_NUM];
+static const uint8_t adc_ch_tbl[ADC_MAX_CH_NUM] =
+{
+ ADC_Channel_9, //key_adc1,pb1
+ ADC_Channel_4, //key_adc2,pa4
+ ADC_Channel_1, //key_adc3,pa1
+ ADC_Channel_8, //key_adc4,pb0
+ ADC_Channel_3, //key_adc5,pa3
+ ADC_Channel_0, //key_adc6,pa0
+ ADC_Channel_15, //key_adc7,pc5
+ ADC_Channel_2, //key_adc8,pa2
+ ADC_Channel_13, //key_adc9,pc3
+ ADC_Channel_11, //key_adc10,pc1
+ ADC_Channel_10, //key_adc11,pc0
+ ADC_Channel_12, //key_adc12,pc2
+ ADC_Channel_6, //vcc_adc_in,pa6
+ ADC_Channel_14, //fa_adc_in,pc4
+ ADC_Channel_7 //hall_adc_in,pa7
+};
+
+void adc_timer_tick(void);
+static void timer4_init(void);
+
+static void adc_gpio_init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |
+ RCC_APB2Periph_GPIOB |
+ RCC_APB2Periph_GPIOC, ENABLE);
+
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 |
+ GPIO_Pin_1 |
+ GPIO_Pin_2 |
+ GPIO_Pin_3 |
+ GPIO_Pin_4 |
+ GPIO_Pin_6 |
+ GPIO_Pin_7;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 |
+ GPIO_Pin_1;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 |
+ GPIO_Pin_1 |
+ GPIO_Pin_2 |
+ GPIO_Pin_3 |
+ GPIO_Pin_4 |
+ GPIO_Pin_5;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+}
+
+static void adc_channels_init(void)
+{
+ ADC_InitTypeDef ADC_InitStructure;
+
+ RCC_ADCCLKConfig(RCC_PCLK2_Div6);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+
+ ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
+ ADC_InitStructure.ADC_ScanConvMode = DISABLE;
+ ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
+ ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+ ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+ ADC_InitStructure.ADC_NbrOfChannel = 1;
+ ADC_Init(ADC1, &ADC_InitStructure);
+ ADC1->CR2 |= 0x0010000;
+
+ //key adc 1 - 12
+ ch_idx = 0;
+ ADC_RegularChannelConfig(ADC1, adc_ch_tbl[ch_idx], 1,
+ ADC_SampleTime_239Cycles5);
+ ADC_Cmd(ADC1, ENABLE);
+
+ ADC_ResetCalibration(ADC1);
+ while(ADC_GetResetCalibrationStatus(ADC1));
+
+ ADC_StartCalibration(ADC1);
+ while(ADC_GetCalibrationStatus(ADC1));
+ ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+ p_adc_timer_tick = adc_timer_tick;
+}
+
+static void adc_dma_init(void)
+{
+}
+
+static void adc_nvic_init(void)
+{
+
+}
+
+static void dac_init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+ DAC_DeInit();
+
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
+
+ DAC->CR |= 0x00010000;
+ DAC_SetChannel2Data(DAC_Align_12b_R, dac_para.val[0]);
+}
+/**
+**У׼°´¼ü
+**/
+void calibrate_key(uint8 cache_enable)
+{
+ const uint8 len = sizeof(dac_para) +2;
+ uint8 buf[len];
+ if(cache_enable)
+ {
+ uint8 crc[2];
+ sp_flash_read(ADDR_KEY_PARA,buf,len);
+ sp_protocol_crc(buf ,len -2,crc);
+ if(memcmp(buf +len -2,crc,2) == 0)
+ {
+ memcpy((uint8*)&dac_para,buf,sizeof(dac_para));
+ return;
+ }
+ }
+ dac_para_auto_set();
+ memcpy(buf,(uint8*)&dac_para,sizeof(dac_para));
+ sp_protocol_crc(buf,len -2,buf +len -2);
+ sp_flash_erase(ADDR_KEY_PARA);
+ sp_flash_write(ADDR_KEY_PARA,buf,len);
+}
+
+void adc_init(void)
+{
+ timer4_init();
+ dac_init();
+ adc_gpio_init();
+ adc_nvic_init();
+ adc_dma_init();
+ adc_channels_init();
+ calibrate_key(1);
+}
+
+uint16_t adc_get_val(uint8_t ch)
+{
+ if(ch<ADC_MAX_CH_NUM)
+ {
+ return adc_buff[ch];
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+void adc_timer_tick(void)
+{
+ adc_timer ++;
+ if(adc_timer>=8)
+ {
+ adc_timer = 0;
+ }
+ if(adc_timer==0)
+ {
+ adc_buff[ch_idx] = ADC_GetConversionValue(ADC1);
+ ch_idx ++;
+ if(ch_idx >= ADC_MAX_CH_NUM)
+ {
+ keypad_scan();
+ ch_idx = 0;
+ }
+
+ if(ch_idx < 12)
+ {
+ DAC_SetChannel2Data(DAC_Align_12b_R, dac_para.val[ch_idx]);
+ }
+ }
+ else if(adc_timer == 7)
+ {
+ ADC_RegularChannelConfig(ADC1, adc_ch_tbl[ch_idx], 1,
+ ADC_SampleTime_239Cycles5);
+ ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+ }
+}
+
+void adc_timer_task(void)
+{
+ if(p_adc_timer_tick)
+ {
+ //ÒѾ³õʼ»¯Íê³É
+ p_adc_timer_tick();
+ }
+}
+
+void dac_para_auto_set(void)
+{
+ uint8_t i;
+ uint16_t dac_val = 4095;
+ uint8_t adj_flags[12];
+
+ p_adc_timer_tick = 0;
+ delay_ms(10);
+ memset(adj_flags, 1, sizeof(adj_flags));
+ while((dac_val*3300ul*66/40950) > 2000) //ÔË·ÅÊä³ö²»µÍÓÚ2V
+ {
+ for(i=0; i<12; i++)
+ {
+ if(adj_flags[i])
+ {
+ dac_para.val[i] = dac_val;
+ }
+ DAC_SetChannel2Data(DAC_Align_12b_R, dac_val);
+ delay_ms(6);
+ ADC_RegularChannelConfig(ADC1, adc_ch_tbl[i], 1, ADC_SampleTime_239Cycles5);
+ ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+ delay_ms(2);
+ if(ADC_GetConversionValue(ADC1) < 300ul)
+ {
+ adj_flags[i] = 0;
+ }
+ else
+ {
+ adj_flags[i] = 1;
+ }
+ }
+
+ if(mem_test(adj_flags, 0, sizeof(adj_flags)) == 0)
+ {
+ break;
+ }
+ dac_val -= 124;
+ }
+ p_adc_timer_tick = adc_timer_tick;
+
+}
+
+static void timer4_init(void)
+{
+ uint16_t PrescalerValue = 0;
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+ TIM_OCInitTypeDef TIM_OCInitStructure;
+
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* TIM4 clock enable */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
+
+ /* GPIOA and GPIOB clock enable */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB|RCC_APB2Periph_AFIO, ENABLE);
+
+ /*GPIOB Configuration: TIM4 channel3 and 4 */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ PrescalerValue = (uint16_t)(SystemCoreClock / 72000000) - 1;
+ /* Time base configuration */
+ TIM_TimeBaseStructure.TIM_Period = 719;
+ TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+
+ TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
+
+ /* PWM1 Mode configuration: Channel1 */
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_Pulse = 359;
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OC3Init(TIM4, &TIM_OCInitStructure);
+ TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable);
+
+ /* PWM1 Mode configuration: Channel2 */
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_Pulse = 359;
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
+ TIM_OC4Init(TIM4, &TIM_OCInitStructure);
+ TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable);
+
+ TIM_ARRPreloadConfig(TIM4, ENABLE);
+
+ /* TIM4 enable counter */
+ TIM_Cmd(TIM4, ENABLE);
+}
diff --git a/sys_hw/drv_adc.h b/sys_hw/drv_adc.h
new file mode 100644
index 0000000..9de4c5d
--- /dev/null
+++ b/sys_hw/drv_adc.h
@@ -0,0 +1,29 @@
+#ifndef __adc_h__
+#define __adc_h__
+
+#include "stm32f10x.h"
+
+#define ADC_MAX_CH_NUM (15u)
+
+#pragma pack(push)
+#pragma pack(1)
+
+typedef struct
+{
+ volatile uint16_t val[12];
+ uint16_t crc;
+} dac_para_t;
+
+#pragma pack(pop)
+
+extern dac_para_t dac_para;
+
+extern volatile uint16_t adc_buff[ADC_MAX_CH_NUM];
+
+extern void adc_init(void);
+extern void adc_timer_task(void);
+extern uint16_t adc_get_val(uint8_t ch);
+extern void dac_para_auto_set(void);
+extern void calibrate_key(uint8_t force);
+
+#endif
diff --git a/sys_hw/drv_usart.h b/sys_hw/drv_usart.h
new file mode 100644
index 0000000..8cb22df
--- /dev/null
+++ b/sys_hw/drv_usart.h
@@ -0,0 +1,15 @@
+#ifndef __drv_usart_h__
+#define __drv_usart_h__
+
+#include "../../st_fw_lib/stm32f10x.h"
+#include "string.h"
+
+#define G401_UART5_FW_VER (0x0001)
+
+extern void usart_init(void);
+extern void usart_send(u8* buf, u8 len);
+extern u16 usart_read(u8* dest, u16 sz);
+extern void usart_isr_proc(void);
+extern void ComOverTimeProceed(void);
+
+#endif
diff --git a/sys_hw/keypad.c b/sys_hw/keypad.c
new file mode 100644
index 0000000..5599c40
--- /dev/null
+++ b/sys_hw/keypad.c
@@ -0,0 +1,195 @@
+#include "keypad.h"
+#include "string.h"
+#include "../supwisdom/sp_util.h"
+#include "drv_adc.h"
+//#include "timer.h"
+//#include "Include_All.H"
+//#include "glcd.h"
+//#include "dbg.h"
+
+#define __key_dbg_en__ 0
+#if(__key_dbg_en__)
+#define key_dbg(...) dbg(__VA_ARGS__)
+#else
+#define key_dbg(...)
+#endif
+
+#define KEY_DOWN_THRESHOLD 300u
+#define KEY_UP_THRESHOLD 100u
+
+struct key_sta_t
+{
+ volatile uint16_t adc_val_pre;
+ volatile uint16_t adc_val_last;
+ volatile uint16_t adc_val_now;
+ volatile uint16_t down_timer;
+ volatile uint8_t adc_chg_cnt;
+ volatile uint8_t is_pressed;
+ volatile uint8_t is_pressed_long;
+ volatile uint8_t long_pressed_timer;
+};
+
+struct
+{
+ volatile uint8_t is_inited;
+ volatile uint8_t lock;
+ volatile uint16_t key_value;
+ struct key_sta_t key_sta[MAX_KEY_NUM];
+} keypad;
+
+uint8_t keypad_init(void)
+{
+ uint8_t i;
+
+ keypad.is_inited = 0;
+ memset(&keypad, 0, sizeof(keypad));
+ Delay_ms(500);
+ for(i=0; i<MAX_KEY_NUM; i++)
+ {
+ keypad.key_sta[i].adc_val_pre = adc_get_val(i);
+ }
+ keypad.is_inited = 1;
+ return 0;
+}
+
+__weak void keypad_cb_on_preesed(uint8_t key_val)
+{
+
+}
+
+uint8_t keypad_get_key(void)
+{
+ if(keypad.key_value != KEY_NONE)
+ {
+ uint8_t temp = keypad.key_value;
+
+ keypad.key_value = KEY_NONE;
+ keypad_cb_on_preesed(temp);
+ return temp;
+ }
+ return KEY_NONE;
+}
+
+void keypad_scan(void)
+{
+ uint8_t i;
+ uint16_t max_delt = 0;
+ uint8_t key_idx = MAX_KEY_NUM;
+
+ key_dbg("\r\nsys_tick:%u\r\n", sys_timer_tick);
+ for(i=0; i<MAX_KEY_NUM; i++)
+ {
+ keypad.key_sta[i].adc_val_now = adc_get_val(i);
+ if(keypad.key_sta[i].adc_val_pre == 0)
+ {
+ keypad.key_sta[i].adc_val_pre = adc_get_val(i);
+ return;
+ }
+ if(keypad.key_sta[i].adc_val_last == 0)
+ {
+ keypad.key_sta[i].adc_val_last = adc_get_val(i);
+ return;
+ }
+
+ if(keypad.key_sta[i].down_timer)
+ {
+ keypad.key_sta[i].down_timer --;
+ if(!keypad.key_sta[i].down_timer)
+ {
+ keypad.key_sta[i].is_pressed = 0;
+ keypad.key_value = i+1;
+ keypad.key_sta[i].adc_val_last = keypad.key_sta[i].adc_val_now;
+ keypad.key_sta[i].adc_val_pre = keypad.key_sta[i].adc_val_now;
+ keypad.lock = 0;
+ }
+ }
+
+ if((keypad.key_sta[i].adc_val_now > keypad.key_sta[i].adc_val_last)&&(!keypad.key_sta[i].is_pressed)&&(!keypad.lock))
+ {
+ uint16_t temp_delt = keypad.key_sta[i].adc_val_now - keypad.key_sta[i].adc_val_last;
+
+ if(temp_delt > KEY_DOWN_THRESHOLD)
+ {
+ if(keypad.key_sta[i].adc_chg_cnt<10)
+ {
+ keypad.key_sta[i].adc_chg_cnt ++;
+ }
+
+ if(temp_delt>max_delt)
+ {
+ max_delt = temp_delt;
+ key_idx = i;
+ }
+ else
+ {
+ keypad.key_sta[i].adc_chg_cnt = 0;
+ }
+ }
+ else
+ {
+ keypad.key_sta[i].adc_val_last = keypad.key_sta[i].adc_val_pre;
+ keypad.key_sta[i].adc_val_pre = keypad.key_sta[i].adc_val_now;
+ keypad.key_sta[i].adc_chg_cnt = 0;
+ keypad.key_sta[i].is_pressed_long = 0;
+ }
+ }
+ else
+ {
+ if(keypad.key_sta[i].is_pressed)
+ {
+ if(keypad.key_sta[i].adc_val_now < keypad.key_sta[i].adc_val_pre)
+ {
+ if((keypad.key_sta[i].adc_val_pre - keypad.key_sta[i].adc_val_now) > KEY_UP_THRESHOLD)
+ {
+ keypad.key_sta[i].adc_chg_cnt ++;
+ }
+ }
+ else
+ {
+ keypad.key_sta[i].adc_chg_cnt = 0;
+ }
+
+ if(keypad.key_sta[i].adc_chg_cnt > 1)
+ {
+ keypad.key_value = i+1;
+ keypad.key_sta[i].adc_val_last = keypad.key_sta[i].adc_val_pre;
+ keypad.key_sta[i].adc_val_pre = keypad.key_sta[i].adc_val_now;
+ keypad.key_sta[i].adc_chg_cnt = 0;
+ keypad.key_sta[i].is_pressed = 0;
+ keypad.key_sta[i].down_timer = 0;
+ keypad.key_sta[i].is_pressed_long = 0;
+ keypad.lock = 0;
+ }
+ }
+ else
+ {
+ keypad.key_sta[i].adc_val_last = keypad.key_sta[i].adc_val_pre;
+ keypad.key_sta[i].adc_val_pre = keypad.key_sta[i].adc_val_now;
+ keypad.key_sta[i].adc_chg_cnt = 0;
+ keypad.key_sta[i].is_pressed_long = 0;
+ }
+ }
+ key_dbg("%02u:%4hu,%4hu,%4hu,%4hu,%4hhu,%4hhu,%4hhu,%4hhu\r\n", i,
+ keypad.key_sta[i].adc_val_pre,
+ keypad.key_sta[i].adc_val_last,
+ keypad.key_sta[i].adc_val_now,
+ keypad.key_sta[i].down_timer,
+ keypad.key_sta[i].adc_chg_cnt,
+ keypad.key_sta[i].is_pressed,
+ keypad.key_sta[i].is_pressed_long,
+ keypad.key_sta[i].long_pressed_timer);
+ }
+
+ if(key_idx<MAX_KEY_NUM)
+ {
+ if(keypad.key_sta[key_idx].adc_chg_cnt>0)
+ {
+ keypad.key_sta[key_idx].is_pressed = 1;
+ keypad.key_sta[key_idx].down_timer = 9; //°´¼üɨÃèÖÜÆÚ112ms£¬112*9ԼΪ1008ms
+ keypad.key_sta[key_idx].adc_chg_cnt = 0;
+ keypad.lock = 1;
+
+ keypad.key_sta[key_idx].adc_val_pre = keypad.key_sta[key_idx].adc_val_now;
+ }
+ }
+}
diff --git a/sys_hw/keypad.h b/sys_hw/keypad.h
new file mode 100644
index 0000000..65fd08f
--- /dev/null
+++ b/sys_hw/keypad.h
@@ -0,0 +1,27 @@
+#ifndef __keypad_h__
+#define __keypad_h__
+
+#include "stdint.h"
+
+#define MAX_KEY_NUM (12u)
+
+#define KEY_NONE ( 0u) //空é²ç¶æ??
+#define KEY_DIG0 (10u) //æ°åé?0
+#define KEY_DIG1 ( 1u) //æ°åé?1
+#define KEY_DIG2 ( 2u) //æ°åé?2
+#define KEY_DIG3 ( 3u) //æ°åé?3
+#define KEY_DIG4 ( 4u) //æ°åé?4
+#define KEY_DIG5 ( 5u) //æ°åé?5
+#define KEY_DIG6 ( 6u) //æ°åé?6
+#define KEY_DIG7 ( 7u) //æ°åé?7
+#define KEY_DIG8 ( 8u) //æ°åé?8
+#define KEY_DIG9 ( 9u) //æ°åé?9
+#define KEY_ENTER (12u) //确认é?
+#define KEY_CANCEL (11u) //åæ¶é?
+
+extern uint8_t keypad_init(void);
+extern uint8_t keypad_get_key(void);
+extern void keypad_scan(void);
+extern void keypad_cb_on_preesed(uint8_t key_val);
+
+#endif
diff --git a/sys_hw/rtc.c b/sys_hw/rtc.c
new file mode 100644
index 0000000..61f263c
--- /dev/null
+++ b/sys_hw/rtc.c
@@ -0,0 +1,165 @@
+#include "rtc.h"
+#include "time.h"
+#include "data_tools.h"
+#include "string.h"
+#include "timer.h"
+
+uint32_t CrystalStartErrFlag;
+
+static uint8_t rtc_wait_flag(uint32_t* reg, uint32_t mask, uint32_t flag, uint32_t timeout)
+{
+ uint32_t t = timeout/100;
+
+ while(((*reg)&mask) != flag)
+ {
+ delay_ms(100);
+ t --;
+ if(t == 0)
+ return 1;
+ }
+
+ return 0;
+}
+
+uint32_t rtc_get_counter(void)
+{
+ return (uint32_t)((RTC->CNTH << 16) | RTC->CNTL);
+}
+
+static uint8_t rtc_set_counter(uint32_t cnt)
+{
+ PWR->CR |= PWR_CR_DBP; // ʹÄÜ·ÃÎÊRTC, BDC ¼Ä´æÆ÷
+ RTC->CRL |=RTC_CRL_CNF; // ÉèÖÃRTCÅäÖñê¼Ç,ÔÊÐíÅäÖÃ
+ RTC->CNTH = (cnt>>16)&0xffff;
+ RTC->CNTL = cnt&0xffff ;
+ RTC->CRL &= ~RTC_CRL_CNF; // ÉèÖÃRTCÅäÖñê¼Ç,²»ÔÊÐíÅäÖÃ
+ if(rtc_wait_flag((uint32_t*)&RTC->CRL, RTC_FLAG_RTOFF, RTC_FLAG_RTOFF, 4000ul)) //µÈ´ýÅäÖÃÍê³É
+ {
+ PWR->CR &= ~PWR_CR_DBP; // ²»ÔÊÐíÅäÖÃRTC¡¢BDC¼Ä´æÆ÷
+ return 1;
+ }
+ PWR->CR &= ~PWR_CR_DBP; // ²»ÔÊÐíÅäÖÃRTC¡¢BDC¼Ä´æÆ÷
+ return 0;
+}
+
+void rtc_init(void)
+{
+ CrystalStartErrFlag = 0;
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+
+ //RTCÊ×´ÎÉϵç»òʱÖÓ¶ªÊ§
+ if(BKP_ReadBackupRegister(BKP_DR1) != 0x5A5A)
+ {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_BKP, ENABLE);
+ PWR_BackupAccessCmd(ENABLE);
+ BKP_DeInit();
+ RCC_LSEConfig(RCC_LSE_ON);
+
+ //²ÎÕÕstm32f10x datasheet£¬LES startup time
+ //tsu(lse) = 3S (Typ)
+ //´Ë´¦µÈ´ýLSEÆðÕñÑÓʱԼ4S
+ if(rtc_wait_flag((uint32_t*)&RCC->BDCR, 0x02, 0x02, 4000ul))
+ CrystalStartErrFlag = 1;
+
+ if(!CrystalStartErrFlag)
+ {
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+ RCC_RTCCLKCmd(ENABLE);
+ /* Clear RSF flag */
+ RTC->CRL &= (u16)~RTC_FLAG_RSF;
+ /* Loop until RSF flag is set */
+ if(rtc_wait_flag((uint32_t*)&RTC->CRL, RTC_FLAG_RSF, RTC_FLAG_RSF, 4000ul))
+ CrystalStartErrFlag = 1;
+
+ //rtc wait for last task
+ if(rtc_wait_flag((uint32_t*)&RTC->CRL, RTC_FLAG_RTOFF, RTC_FLAG_RTOFF, 4000ul))
+ CrystalStartErrFlag = 1;
+
+ RTC_SetPrescaler(32767);
+ //rtc wait for last task
+ if(rtc_wait_flag((uint32_t*)&RTC->CRL, RTC_FLAG_RTOFF, RTC_FLAG_RTOFF, 4000ul))
+ CrystalStartErrFlag = 1;
+
+ BKP_WriteBackupRegister(BKP_DR1, 0x5A5A);
+ }
+ PWR_BackupAccessCmd(DISABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_BKP, DISABLE);
+ }
+ else
+ {
+ /* Clear RSF flag */
+ RTC->CRL &= (u16)~RTC_FLAG_RSF;
+ /* Loop until RSF flag is set */
+ if(rtc_wait_flag((uint32_t*)&RTC->CRL, RTC_FLAG_RSF, RTC_FLAG_RSF, 4000ul))
+ CrystalStartErrFlag = 1;
+ else
+ {
+ //0x386D4380ul 2000Äê1ÔÂ1ÈÕÃëÊý
+ if(rtc_get_counter()<0x386D4380ul)
+ {
+ rtc_set_counter(0x386D4380ul);
+ }
+
+// rtc_get_time(&SystemTime);
+ }
+ }
+}
+
+uint32_t rtc_mk_time(_SystemTime* t)
+{
+ struct tm temp_time;
+ _SystemTime temp_time_hex;
+
+ memcpy(&temp_time_hex, t, sizeof(_SystemTime));
+ bcd2hex(&temp_time_hex, sizeof(temp_time_hex));
+ temp_time.tm_year = temp_time_hex.year+100; //´Ó1900Ä꿪ʼ
+ temp_time.tm_mon = temp_time_hex.month-1;
+ temp_time.tm_mday = temp_time_hex.day;
+ temp_time.tm_wday = temp_time_hex.week;
+ temp_time.tm_hour = temp_time_hex.hour;
+ temp_time.tm_min = temp_time_hex.minute;
+ temp_time.tm_sec = temp_time_hex.second;
+
+ return mktime(&temp_time);
+}
+
+uint8_t rtc_set_time(_SystemTime* t)
+{
+ uint8_t ret = 0;
+ time_t seconds = rtc_mk_time(t);
+
+ ret = rtc_set_counter(seconds);
+
+ return ret;
+}
+
+uint8_t rtc_get_time(_SystemTime* t)
+{
+ struct tm* temp_time;
+ _SystemTime temp_time_bcd;
+ time_t seconds = rtc_get_counter();
+
+ temp_time = localtime(&seconds);
+ if(temp_time->tm_year<100)
+ temp_time_bcd.year = 0;
+ else
+ temp_time_bcd.year = temp_time->tm_year - 100;
+
+ temp_time_bcd.month = temp_time->tm_mon+1;
+ temp_time_bcd.day = temp_time->tm_mday;
+ temp_time_bcd.week = temp_time->tm_wday;
+ temp_time_bcd.hour = temp_time->tm_hour;
+ temp_time_bcd.minute = temp_time->tm_min;
+ temp_time_bcd.second = temp_time->tm_sec;
+ hex2bcd(&temp_time_bcd, sizeof(temp_time_bcd));
+ memcpy(t, &temp_time_bcd, sizeof(temp_time_bcd));
+ return 0;
+}
+
+uint32_t rtc_time_diff(void* t1, void* t2)
+{
+ uint32_t t1_sec = rtc_mk_time((_SystemTime*)t1);
+ uint32_t t2_sec = rtc_mk_time((_SystemTime*)t2);
+
+ return (t1_sec-t2_sec);
+}
diff --git a/sys_hw/rtc.h b/sys_hw/rtc.h
new file mode 100644
index 0000000..c62efc3
--- /dev/null
+++ b/sys_hw/rtc.h
@@ -0,0 +1,27 @@
+#ifndef __rtc_h__
+#define __rtc_h__
+
+#include "stm32f10x.h"
+
+//ϵͳʱ¼ä½á¹¹
+typedef struct
+{
+ uint8_t year; //Äê
+ uint8_t month; //ÔÂ
+ uint8_t day; //ÈÕ
+ uint8_t week; //ÐÇÆÚ
+ uint8_t hour; //ʱ
+ uint8_t minute; //·Ö
+ uint8_t second; //Ãë
+}_SystemTime ;
+
+//extern _SystemTime SystemTime,SystemTimeBak;
+
+extern void rtc_init(void);
+extern uint8_t rtc_set_time(_SystemTime* t);
+extern uint8_t rtc_get_time(_SystemTime* t);
+//extern uint32_t rtc_mk_time(_SystemTime* t);
+//extern uint32_t rtc_time_diff(void* t1, void* t2);
+//extern uint32_t rtc_get_counter(void);
+
+#endif
diff --git a/sys_hw/timer.c b/sys_hw/timer.c
new file mode 100644
index 0000000..b66ec32
--- /dev/null
+++ b/sys_hw/timer.c
@@ -0,0 +1,43 @@
+#include "timer.h"
+#include "icc_apdu_lib_v02.h"
+#include "HW_CAN_LIB.H"
+#include "drv_adc.h"
+#include "drv_valve.h"
+#include "drv_flowsensor.h"
+#include "drv_usart.h"
+
+//static vu32 timertick = 0;
+vu32 timertick = 0;
+
+void SysTick_cfg(void)
+{
+ SysTick_Config(SystemCoreClock/1000ul);
+}
+
+void TimerTick(void)
+{
+
+ update_sam_ticker();
+
+ adc_timer_task();
+
+ ComOverTimeProceed();
+ hw_can_sta_proc();
+
+ timertick++;
+
+ flowsensor_update_count();
+
+ valve_timer_dec();
+}
+
+u32 timer_get_ticker(void)
+{
+ return timertick;
+}
+void delay_ms(u32 t)
+{
+ u32 temp = timertick;
+
+ while((timertick - temp) < t);
+}
diff --git a/sys_hw/timer.h b/sys_hw/timer.h
new file mode 100644
index 0000000..072bdba
--- /dev/null
+++ b/sys_hw/timer.h
@@ -0,0 +1,11 @@
+#ifndef __timer_h__
+#define __timer_h__
+
+#include "stm32f10x.h"
+
+//extern void SysTick_cfg(void);
+extern void TimerTick(void);
+extern u32 timer_get_ticker(void);
+extern void delay_ms(u32 t);
+
+#endif
diff --git a/zk/gb2312_16.c b/zk/gb2312_16.c
new file mode 100644
index 0000000..579a90a
--- /dev/null
+++ b/zk/gb2312_16.c
@@ -0,0 +1,227 @@
+#include "glcd.h"
+//#include "timer.h"
+#include "../nec_hardware.h"
+#include "gb2312_16.h"
+#include "string.h"
+#include "stdio.h"
+
+uint8_t gb2312_16x16_draw_char(uint8_t x, uint8_t y, uint8_t buf[32])
+{
+ uint8_t i,j;
+
+ for(i=0;i<16;i++)
+ {
+ for(j=0;j<2;j++)
+ {
+ uint8_t dat,bit;
+
+ dat = buf[2*i+j];
+
+ if(glcd_get_reverse_sta())
+ dat = ~dat;
+
+ for(bit=0;bit<8;bit++)
+ {
+ if (dat & (0x80>>bit))
+ {
+ glcd_set_pixel(x+j*8+bit, y+i, BLACK);
+ }
+ else
+ {
+ glcd_set_pixel(x+j*8+bit, y+i,WHITE);
+ }
+ }
+ }
+ }
+
+ return 16;
+}
+
+void gb2312_16x16_get_data(uint8_t xy[2], uint8_t buf[32])
+{
+ uint32_t offset;
+
+ if((xy[0]<0xa1) || (xy[1])<0xa1)
+ return;
+
+ offset = (94*(xy[0] - 0xa1) + (xy[1] - 0xa1))*32ul;
+
+ HW_Flash_Read(offset+256, 32, buf);
+}
+
+uint8_t gb2312_16x8_draw_char(uint8_t x, uint8_t y, uint8_t buf[16])
+{
+ uint8_t i;
+
+ for(i=0;i<16;i++)
+ {
+ uint8_t dat,bit;
+
+ dat = buf[i];
+
+ if(glcd_get_reverse_sta())
+ dat = ~dat;
+ for(bit=0;bit<8;bit++)
+ {
+ if (dat & (0x80>>bit))
+ {
+ glcd_set_pixel(x+bit, y+i, BLACK);
+ }
+ else
+ {
+ glcd_set_pixel(x+bit, y+i,WHITE);
+ }
+ }
+ }
+
+ return 8;
+}
+
+void gb2312_16x8_get_data(uint8_t c, uint8_t buf[16])
+{
+ uint32_t offset;
+
+ offset = c*16ul + 0x43000;
+
+ HW_Flash_Read(offset, 16, buf);
+}
+
+void gb2312_16x16_test(void)
+{
+ uint32_t i,j;
+
+ HW_Flash_Init();
+ glcd_init();
+ glcd_clear();
+
+ for(i=0xa1;i<0xfe;i++)
+ {
+ uint8_t xy[2];
+
+ xy[0] = i;
+ for(j=0xa1;j<0xfe;j++)
+ {
+ uint8_t buf[32];
+
+ xy[1] = j;
+
+ gb2312_16x16_get_data(xy, buf);
+ gb2312_16x16_draw_char(0, 0, buf);
+ glcd_write();
+ delay_ms(100);
+ }
+ }
+}
+
+
+void gb2312_16x8_test(void)
+{
+ uint32_t i;
+
+ HW_Flash_Init();
+ glcd_init();
+ glcd_clear();
+
+ for(i=0;i<256;i++)
+ {
+ uint8_t buf[32];
+
+ gb2312_16x8_get_data(i, buf);
+ gb2312_16x8_draw_char(0, 0, buf);
+ glcd_write();
+ delay_ms(50);
+ }
+}
+
+uint8_t gb2312_16_get_ver(uint8_t ver[3])
+{
+ uint8_t temp_buff[20];
+
+ if(HW_Flash_Read(0, sizeof(temp_buff), temp_buff))
+ return 1;
+
+ if(memcmp(temp_buff, sk_font_id, 9))
+ return 2;
+
+ memcpy(ver, temp_buff+9, 3);
+ ver[0] -= '0';
+ ver[1] -= '0';
+
+ return 0;
+}
+
+void gb2312_16_draw_str(uint8_t x, uint8_t y, char* s)
+{
+ uint8_t i=0,j=0;
+
+ while(*s)
+ {
+ uint8_t buf[32];
+
+#if 1
+ if(x>=GLCD_LCD_WIDTH || y>=GLCD_LCD_HEIGHT)
+ return ;
+#else
+ if(x+i >= GLCD_LCD_WIDTH)
+ {
+ j += 16; //»»ÐÐ
+ i = 0; //»Ø³µ
+ }
+ if(y+j >= GLCD_LCD_HEIGHT)
+ {
+ j = 0;
+ i = 0;
+ }
+#endif
+ if((uint8_t)(*s)<128)
+ {
+ gb2312_16x8_get_data((uint8_t)*s, buf);
+ i += gb2312_16x8_draw_char(x+i, y+j, buf);
+ }
+ else
+ {
+ gb2312_16x16_get_data((uint8_t *)s, buf);
+ i += gb2312_16x16_draw_char(x+i, y+j, buf);
+ s ++;
+ }
+ s ++;
+ }
+}
+
+uint8_t gb2312_16_verify(void)
+{
+ const uint8_t font_01[32] =
+ {
+ 0x01, 0x00, 0x01, 0x00, 0x01, 0x08, 0x01, 0x10, 0x7D, 0x20, 0x05, 0xC0, 0x05, 0x40, 0x09, 0x20,
+ 0x09, 0x20, 0x11, 0x10, 0x11, 0x18, 0x21, 0x0E, 0xC1, 0x04, 0x01, 0x00, 0x05, 0x00, 0x02, 0x00
+ };
+ const uint8_t font_02[32] =
+ {
+ 0x10, 0x00, 0x10, 0x20, 0x10, 0x10, 0xFD, 0xFE, 0x11, 0x04, 0x10, 0x50, 0x14, 0x8C, 0x19, 0x04,
+ 0x30, 0x00, 0xD1, 0xFC, 0x10, 0x20, 0x10, 0x20, 0x10, 0x20, 0x10, 0x20, 0x53, 0xFE, 0x20, 0x00
+ };
+ const uint8_t font_03[16] =
+ {
+ 0x00, 0x00, 0x10, 0x38, 0x6C, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00
+ };
+ const uint8_t font_04[16] =
+ {
+ 0x00, 0x00, 0xFC, 0x66, 0x66, 0x66, 0x7C, 0x66, 0x66, 0x66, 0x66, 0xFC, 0x00, 0x00, 0x00, 0x00
+ };
+ uint8_t buf[32];
+
+ gb2312_16x16_get_data("ˮ", buf);
+ if(memcmp(buf, font_01, sizeof(font_01)))
+ return 1;
+ gb2312_16x16_get_data("¿Ø", buf);
+ if(memcmp(buf, font_02, sizeof(font_02)))
+ return 2;
+ gb2312_16x8_get_data('A', buf);
+ if(memcmp(buf, font_03, sizeof(font_03)))
+ return 3;
+ gb2312_16x8_get_data('B', buf);
+ if(memcmp(buf, font_04, sizeof(font_04)))
+ return 4;
+
+ return 0;
+}
diff --git a/zk/gb2312_16.h b/zk/gb2312_16.h
new file mode 100644
index 0000000..d41d8d9
--- /dev/null
+++ b/zk/gb2312_16.h
@@ -0,0 +1,15 @@
+#ifndef __gb2312_16_h__
+#define __gb2312_16_h__
+
+#include "stdint.h"
+#include "glcd.h"
+
+#define sk_font_id (char*)"sk_zk_16_v"
+
+extern uint8_t gb2312_16x8_draw_char(uint8_t x, uint8_t y, uint8_t buf[16]);
+extern uint8_t gb2312_16x16_draw_char(uint8_t x, uint8_t y, uint8_t buf[32]);
+extern void gb2312_16_draw_str(uint8_t x, uint8_t y, char* s);
+extern uint8_t gb2312_16_verify(void);
+extern uint8_t gb2312_16_get_ver(uint8_t ver[3]);
+
+#endif
diff --git a/zk/sk_zk_16_10A.hex b/zk/sk_zk_16_10A.hex
new file mode 100644
index 0000000..c5876eb
--- /dev/null
+++ b/zk/sk_zk_16_10A.hex
@@ -0,0 +1,8709 @@
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diff --git a/zk/sk_zk_16_10A.upf b/zk/sk_zk_16_10A.upf
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diff --git a/zk/sk_zk_16_15A.upf b/zk/sk_zk_16_15A.upf
new file mode 100644
index 0000000..1e8b6f2
--- /dev/null
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